JPH0227464A - Shared memory control system for multi-processor system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a shared memory management method in a multiprocessor system in which a plurality of processors are connected to a common system bus and a shared memory is placed on the system bus. It is related to.

[Prior art and its problems]

A conventional multiprocessor system of this type is configured as shown in FIG. 4, and the shared memory is accessed from each of the processors O to (2) via a system bus (2).

Each of the processors O to [F] has an independent memory management unit, and each processor independently manages the shared memory.

Therefore, when attempting to manage memory by paging an area on the shared memory, management methods are considered depending on where in the physical memory the page table is placed.

The first method is to place the page table ◎ in its own local memory area within the memory management unit MMU of each processor, as shown in FIG. (Refer to Japanese Unexamined Patent Publication No. 62-263538.) However, since this method results in the existence of multiple page tables for shared memory ■, a certain processor rewrites page table ◎ for shared memory ■. In this case, the page tables for shared memory managed by all processors must also be changed at the same time to maintain consistency between each page table, so is this a significant problem? 1! Requires complicated software processing.

Therefore, as a second method, a method was considered in which the page table (2) for the shared memory was placed on the shared memory as shown in FIG.

(Refer to Japanese Unexamined Patent Publication No. 115554/1982) This second method means that there is only one page table from the perspective of each processor, and management of multiple page tables as described in the first method is not possible. This problem is eliminated, and practical application is easy.

However, in this case as well, the memory management function itself is located on each processor side, and it is necessary to provide a translation look-aside buffer (hereinafter referred to as TLB) in each processor.
Similar to the above method, complex hardware and software processing is required.

Therefore, the present invention aims to provide an easy-to-implement and efficient method for managing shared memory in a multiprocessor system as described above.

[Means to solve the problem]

As a method for solving the above problems, the present invention provides a memory management unit MMU equipped with a page table ■ and an address conversion mechanism in a shared memory circuit connected to a system bus ■, as shown in FIG. One of the processors is used as a shared memory management processor.

In order to maintain consistency in memory management, the address translation mechanism sends a page absence signal a and an access restart signal s to each processor as described later, and the memory management processor sends a page absence processing end signal d to the address translation mechanism. death,
It is effective if the access abort signal C is simultaneously sent from each processor other than the memory management processor to the address translation mechanism and the memory management processor.

[For production]

As can be seen from FIG. 1, the method according to the present invention differs from the conventional method in that the memory management function of the shared memory itself is located on the shared memory. When accessing shared memory from each processor, the address physically issued on the system bus is a logical address, and when accessing shared memory, that logical address is used as a memory management address for shared memory. The mechanism converts it into a physical address and accesses it as a shared memory address.

Therefore, in this case, since the memory management mechanism itself is only in one place, it becomes easy to perform memory management while maintaining consistency.

As a specific implementation method, a memory management processor is installed as a memory management mechanism for shared memory, and instead of each processor on the system bus managing the shared memory, By issuing commands to perform memory management of the shared memory, consistency in memory management of the shared memory can be easily achieved.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which the processor IA
When a user attempts to access the shared memory, the address in the page table F is first given to the page table F via the page table address bus H by the address translation mechanism G.

If the corresponding page address of the page table is found, the address translation mechanism G
Notify. At the same time, a page address is given to the shared memory through the page address bus. Also, the intra-page offset value for the shared memory is determined by the address bus L.
is given by an address bus branched from .

As a result, read/write operations on the shared memory are executed according to the state of the control bus D.

If the corresponding page address of page table F is
If the page is not found on the page table, the address translation mechanism G is notified of the absence of the page via the control signal bus 0. As a result, the address translation mechanism G determines that the processor I that requested access to the shared memory
A command to temporarily suspend access is sent to A via the control bus D. At the same time, it notifies the processor in charge of memory management in the shared memory via the control bus D that a page-missing access has occurred.

The processor that performs memory management takes appropriate action and notifies the address translation mechanism G of the content of the action and the result of completion.

If execution of processor IA can be resumed,
The address translation mechanism G issues a restart command to the processor IA, and access to the shared memory E is restarted.

If restart is not possible, processor IA is notified that restart is not possible, and the current access to the shared memory from processor IA is terminated.

FIG. 3 shows, among the control bus signals in FIG. 2, signals that are exchanged between the processor and the address translation mechanism G when a page absence occurs. This is a signal to notify processor A, which requested access to shared memory E, of the absence when the corresponding page no longer exists.

When processor A, which requested access, receives the absence signal, it temporarily suspends access and releases the system bus.

At the same time, when the memory management processor X (of which there is only one in the system) learns that the absence signal has occurred, it executes a processing process for it. At this time, information regarding the address where the page failure has occurred is held in the address translation mechanism G, and the memory management processor X can access this information.

When the page absence processing process is completed, the memory management processor X notifies the address conversion mechanism G by using a page absence processing completion signal d.

If it is possible to resume access, processor A, which had suspended access, resumes access in response to the access restart signal.

If restart is not possible, access abort signal C is used to notify that restart is not possible.

Since processor A, which had requested access, is unable to access the shared memory, an interrupt is generated to a processing routine that cannot access the shared memory.

〔Effect of the invention〕

According to the method of the present invention, memory management of the shared memory can be performed safely and efficiently in a multiprocessor system having a shared memory that can be accessed through a common system bus.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the basic configuration of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, and Fig. 3 shows the exchange of signals between the processor and the address translation mechanism in the embodiment. An explanatory diagram, FIG. 4 is a block diagram showing the configuration of a conventional multiprocessor system, and FIGS. 5 and 6 are
The figures are block diagrams of conventional shared memory management methods,
Fig. 1 is a block diagram showing the basic configuration of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, and Fig. 3 shows the exchange of signals between the processor and the address translation mechanism in the embodiment. It is an explanatory diagram. ■... Shared memory ■... System bus ■... Processor 1 ■... Processor 2 ■... Processor n [F]... Memory management unit ■... Page table A... Processor I B... Address bus C... Data bus D... Control bus E... Shared memory F... Page table G... Address conversion mechanism H... Page table address bus I... Page address bus J...Data bus K...Data bus L...Address bus M...Control bus N...Processor 20...Control signal bus P...Shared memory circuit X...・Memory management processor A...Processor I B...Address bus C...Data bus D...Control bus E...Shared memory F...Page table G...Address conversion mechanism H...・Page table address bus Summer...Page address bus J...Data bus K...Data bus L...Address bus M...Control bus N...Processor 2 0...Control signal bus P ...Coexistence memory circuit X...Memory management processor

Claims (2)

[Claims] (1) In a multiprocessor system in which multiple processors are connected to a common system bus and a shared memory is placed on the system bus, the shared memory circuit including the shared memory, page table, and address conversion mechanism is connected to the system bus. 1. A shared memory management method in a multiprocessor system, characterized in that one processor in the system is connected to a shared memory management processor. (2) The address translation mechanism sends a page absence signal a and an access restart signal b to each processor, and the memory management processor sends a page absence processing end signal d to the address translation mechanism, and each processor other than the memory management processor 2. A shared memory management system in a multiprocessor system according to claim 1, wherein an access abort signal c is simultaneously sent from said address translation mechanism and said memory management processor.