JPH06301643A - Bus arbitration circuit - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] The present invention relates to a bus arbitration circuit of a complete interrupt type in a parallel processing type multiprocessor system, so that interrupt processing can be evenly distributed in a parallel processing type system. The purpose is to prevent uneven load. [Configuration] A bus arbitration circuit of each processor for arbitrating bus access contention, which decodes a control signal or the like from the CPU 31 and requests bus acquisition, and a normal bus access or interrupt A decoding unit 32 for generating a bus access discrimination signal for discriminating a bus access and a bus 36 for receiving a bus request signal.
A bus arbitration unit 33 that executes bus arbitration for bus acquisition, an interrupt bus access management unit 34 that sets / resets an interrupt bus access priority bit based on a bus access determination signal, A normal bus access management unit 35 for setting / resetting a priority bit for normal bus access is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system of parallel processing type multiprocessor, and a bus of a complete interrupt type in which an interrupt request coming from a slave I / O board or the like is evenly distributed to each processor and processed. It relates to an arbitration circuit.

As a device having a parallel processing type multiprocessor configuration, there are various control devices for wireless communication, for example. In these control devices, interrupt requests coming from slave I / O boards and the like are evenly distributed to each processor. It is desirable to be able to evenly distribute the load applied to each processor by distributing and processing the above.

In order for the processor to start the interrupt processing in response to the interrupt request, it is necessary to acquire the interrupt vector from the slave I / O board or the like on the common bus. Therefore, in order to evenly distribute the loads of the processors as described above, it is necessary that the processors of the multiprocessor configuration system can evenly obtain the interrupt vector from the I / O board or the like on the common bus. .

[0004]

2. Description of the Related Art FIG. 6 shows a parallel processing type multiprocessor.
A system configuration example is shown. As shown in the figure, the common bus 20 has a plurality of processors and slave memories and I / Os.
The board is connected.

In this system, for example, when an interrupt request is issued from the I / O board, this interrupt request is transmitted to each processor via the common bus 20. Although there is only one processor that processes this interrupt request, in order for that processor to start interrupt processing in response to the interrupt request, an interrupt vector must be acquired from the I / O board via the common bus 20. It is necessary to acquire the right to use the common bus because it has to be. However, since a plurality of processors cannot use the common bus 20 at the same time, it is necessary to perform arbitration for using the common bus so as not to compete with other processors, and each processor has a bus arbitration circuit.

FIG. 7 shows an operation flow of this bus arbitration circuit. When a common bus use request is generated based on an interrupt request or the like, each processor waits for the common bus to be released at the end of use, and then its own panel ID (identification number) and AC.
Sends the (acquisition) signal to the common bus and arbitrates bus usage so that it does not conflict with other processors.

Here, the transmission of the own panel ID from each processor to the common bus is performed through a negative logic wired OR circuit. Therefore, even if a plurality of processors simultaneously send their own panel IDs to the common bus, the ID placed on the common bus is the ID of the processor that sends the largest ID among these processors. That is, the ID of each processor having the larger value is prioritized and placed on the common bus.

Therefore, when the ID on the common bus matches the own panel ID, the processor has the largest ID value and the right to acquire the bus has the highest priority, so that the common bus can be acquired. Start using the common bus as.

On the other hand, if they do not match, I on the common bus
If D is larger than the own panel ID, the other processor has the right to acquire the bus, so abandon the acquisition of the bus at the present time and set the priority bit to enable the acquisition of the bus at the next arbitration. It sets and waits, and performs bus arbitration again when it finishes using the common bus.

Here, this priority bit is set to one digit higher than the most significant bit of its own panel ID. Therefore, an ID for which the priority bit is set is an ID for which it is not set. The higher the value, the higher the priority for bus acquisition.

If the own panel ID is larger than the ID on the common bus in the case of a mismatch, it is considered that another processor is currently using the common bus. Wait for the end of use and perform bus arbitration again.

[0012]

The case of accessing the common bus in order to acquire an interrupt vector in response to an interrupt request from I / O or the like has been described above, but the access to the common bus is caused by this interrupt. In addition to the above, there is also a case of a normal common bus access for accessing between the memories at a normal time. In the above-described conventional technique, the same priority bit is used regardless of whether the common bus access is caused by the normal bus access or the common bus access caused by the interrupt, and the use of the common bus is evenly distributed to the processors. I am trying to do it.

Therefore, a processor performs common bus arbitration to acquire the interrupt vector, and the priority bit is set because the bus cannot be acquired. However, the common bus access for this interrupt is followed by the normal common bus access.
If an access occurs and the processor acquires the common bus in the normal common bus access, the priority bit set for the common bus access of the interrupt is reset. Therefore, even if the common bus is accessed to acquire the interrupt vector from the next time onward, the possibility that the common bus can be acquired becomes small because the priority bit is not set.

As a result, the possibility of acquisition of the interrupt vector is biased depending on the running state of the software, the even distribution of the interrupt processing to each processor cannot be guaranteed, and the load applied to each processor is different. It is biased depending on the processor.

The present invention has been made in view of the above problems, and an object of the present invention is to enable interrupt processing to be evenly distributed to each processor in a parallel processing type multiprocessor system. The goal is to ensure that the loads applied by the individual processors are not biased.

[0016]

FIG. 1 is a diagram illustrating the principle of the present invention. In order to solve the above-mentioned problems, the present invention relates to a bus arbitration circuit provided in each processor for arbitrating bus access contention in a parallel processing type multiprocessor system, which is a control signal from a CPU 31. And the like, and generates a bus request signal for requesting bus acquisition based on the decoding result and a bus access determination signal for determining whether the bus access is a normal bus access or an interrupt bus access. When,
When a bus request signal is received, a bus arbitration unit 33 that executes bus arbitration for bus acquisition on the bus 36 while appropriately exercising priority bits, and an interrupt for bus access based on the bus access determination signal An interrupt bus access management unit 34 for setting / resetting a priority bit for bus access, and a normal bus access for setting / resetting a priority bit for normal bus access with respect to a normal bus access based on a bus access determination signal A bus arbitration circuit including a management unit 35 is provided.

In the above bus arbitration circuit, the interrupt bus access management unit 34 sets the priority bit for interrupt bus access when the bus acquisition by the interrupt bus access fails and resets it when it succeeds. And the normal bus access management unit 35,
The priority bit for normal bus access can be set when the bus acquisition by the normal bus access fails and reset when succeeding.

In the bus arbitration circuit described above, the interrupt bus access management unit 34 resets the interrupt bus access priority bit on condition that the ACK signal is received from the bus 36 for the interrupt bus access. Can be configured to.

In the bus arbitration circuit described above, the CPU
An interrupt level decoder which decodes the interrupt response level of the interrupt bus access based on the control signal from 31 and a comparator which compares the interrupt response level from the interrupt level decoder with the interrupt response level of the interrupt signal on the bus The interrupt bus access management unit 34 can be configured to reset the interrupt bus access priority bit on condition that the comparison results of the comparison unit match.

Further, according to the present invention, there is provided a bus arbitration method for arbitrating bus access contention in a parallel processing type multiprocessor system, wherein priority bit management for equalizing opportunities for bus acquisition is performed. ,
Interrupt bus for interrupt request from slave board
There is provided a bus arbitration method characterized in that an interrupt priority bit used for access and a normal priority bit used for normal bus access are separately performed.

[0021]

The decoding section 32 decodes the control signal and the like from the CPU 31 and determines whether the bus request signal for requesting bus acquisition and the bus access are normal bus access or interrupt bus access based on the decoding result. And a bus access determination signal. The bus arbitration unit 33 includes the decoding unit 32.
When the bus request signal is received from the bus 36, bus arbitration for bus acquisition is executed for the bus 36 while appropriately exercising priority bits.

At this time, the interrupt bus access management unit 34
If the bus access determination signal indicates an interrupt bus access, the priority bit for interrupt bus access is set, for example, when bus acquisition by interrupt bus access fails, and reset when successful. .

Similarly, if the bus access determination signal indicates a normal bus access, the normal bus access management unit 35 fails to acquire the priority bit for normal bus access, for example, bus acquisition by normal bus access. Set when done and reset when successful.

By doing so, the management of priority bits for equalizing the opportunities for bus acquisition is exercised at the time of interrupt bus access for interrupt requests from slave ports.
Bits and normal priority bits used for normal bus access can be divided and performed separately. This allows the bus acquisition opportunity of each processor to the interrupt request from the slave board to the normal bus access. The load on each processor can be evenly distributed regardless of the presence or absence of the load.

Further, the interrupt bus access management unit 34
ACKs from bus 36 for interrupt bus access
If the priority bit for interrupt bus access is reset on the condition that a signal is received, the bus arbitration unit is activated more than other processors in response to an interrupt request due to a difference in software running state. Even if there is a delay, the interrupt bus access priority bit is not reset unless the processor executes interrupt processing, so interrupt distribution is more strictly realized.

Further, the interrupt bus access management unit 34 is
By configuring the interrupt bus access priority bit to be reset on the condition that the comparison result of the comparison unit matches, the bus arbitration unit is activated in response to an interrupt request due to a difference in software running state. Is delayed compared to other processors, the interrupt processing is passed to the other processors and the interrupt signal on the bus becomes OF.
When F is set, the interrupt bus access priority bit is not reset, so that interrupt distribution is more strictly realized.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a completely distributed interrupt arbitration circuit as an embodiment of the present invention. In FIG. 2, reference numeral 1 is a CPU (central processing unit). The CPU 1 monitors signals on the common bus 20 and issues an instruction for processing for acquiring an interrupt vector in response to an interrupt request from an I / O board or the like.

2 is a decoder, and this decoder 2 is C
A BR (Bus) requesting a common bus arbitration unit, which will be described later, to acquire a common bus based on an address and a control signal from PU1.
Request) signal or a signal that determines whether the common bus access is a normal bus access or an interrupt bus access based on a split.

Reference numeral 3 is a common bus arbitration unit. When the common bus arbitration unit 3 receives a BR signal from the decoder 2, it sends its own panel ID and AC signal to the common bus 20 to execute arbitration for acquiring the common bus. It is a circuit to do. At that time, when the priority signal (NP signal or IP signal) is input, the operation is performed to set the priority bit in the own panel ID. Also, the ID on the common bus is constantly monitored, and if the ID on the common bus matches the own panel ID, the WIN signal is output, and if it is larger than the own panel number, the> ID signal is output. When the bus acquisition is successful, a BG (bus Grant) signal is output, and when it fails, a LOSE signal is output.

Reference numeral 4 is a flip-flop for managing the priority bit NP for normal bus access, and 5
Is a flip-flop for managing the priority bit IP for interrupt access. Further, 6 to 14 are AND gates, and 15 and 16 are OR gates.

Here, the normal bus access signal and>
The output signal of the AND gate 6 to which the ID signal is input is input to the set terminal S of the flip-flop 4, and the AND gate 7 to which the normal bus access signal and the WIN signal are input.
Output signal of each of the AND gates 8 is input to the reset terminal R of the flip-flop 4, and the normal bus access signal and the output signal Q of the flip-flop 4 are input.
Is output to the common bus arbitration unit 3 via the OR gate 15 as a normal bus access priority bit NP.

Also, interrupt bus access signals and>
The output signal of the AND gate 9 to which the ID signal is input is set to the set terminal S of the flip-flop 5, and the output signal of the AND gate 10 to which the interrupt bus access signal and the WIN signal are input are the reset terminal R of the flip-flop 5.
The output signal of the AND gate 11 to which the interrupt bus access signal and the output signal Q of the flip-flop 5 are respectively input to the common bus arbitration unit 3 as the interrupt bus access priority bit IP via the OR gate 15. Entered in.

Further, the BERR (bus
The error signal and the output signal of the AND gate 13 to which the BG signal from the common bus arbitration unit 3 is input are the OR gate 1
The output signal of the AND gate 12 to which the ACK signal from the common bus 20 and the BG signal from the common bus arbitration unit 3 are input to the BERR terminal of the CPU 1 via C 6 is C
It is input to the ACK terminal of PU1. Further interrupt bus
The output signal of the AND gate 14 to which the access signal and the LOSE signal from the common bus arbitration unit 3 are input is input to the BERR terminal of the CPU 1 via the OR gate 16.

The operation of the circuit of this embodiment will be described below.
The decoder 2 decodes a control signal such as an address or a function code output from the CPU 1, and when it decodes the control signal as a common bus access request, sends a BR signal to the common bus arbitration unit 3. The common bus arbitration by the common bus arbitration unit 3 is activated. At the same time, the decoder 2 determines whether the common bus access request is a normal bus access or an interrupt bus access, and activates the corresponding signal line according to the determination result.

As a result, when the priority bit is used for bus arbitration, either NP or IP is selected and used according to the type of access. This operation is described below, for example, assuming that the access is an interrupt bus access.

Now that there is an interrupt bus access and the common bus arbitration unit 3 has started the bus arbitration, the ID on the common bus
Since it does not match the own panel ID, it is assumed that the current bus acquisition is abandoned. In this case, the common bus arbitration unit 3
Outputs a> ID signal. As a result, a set signal is output from the AND gate 9 and "1" is set to the flip-flop 5 as a priority bit for interrupt bus access. As a result, the AND gate 11
When an interrupt bus access signal is input to
The gate 11 is opened, and the interrupt bus access priority bit IP of the flip-flop 5 can be input to the common bus arbitration unit 3 via the OR gate 15.

The next common bus access will be the interrupt bus
If it is an access, the AND bus 11 is opened by the interrupt bus access signal, and the priority bit IP is input from the flip-flop 5 to the common bus arbitration unit 3, so that the common bus arbitration unit 3 performs its own panel operation. Set the priority bit in the ID to activate bus arbitration. This is my own panel I with high priority
Since D is used, there is a high possibility that a common bus can be acquired.

When the acquisition of the common bus is successful, the common bus arbitration unit 3 outputs the WIN signal and the BG signal. The AND gate 10 is opened by this WIN signal, the interrupt bus access signal is input to the reset terminal R of the flip-flop 5, and the interrupt bus access priority bit IP held therein is reset.
Therefore, transmission of the priority bit IP for interrupt bus access from the AND gate 11 is stopped, and the common bus arbitration unit 3 cancels the setting of the priority bit.

On the other hand, when the next common bus access described above is a normal bus access, the same operation as described above is performed on the normal bus access flip-flop 4 side, and the flip-flop 4 at that time is operated. The normal bus access priority bit NP is transmitted or stopped in accordance with the held contents. In this case, since the interrupt bus access signal is not output, the AND gate 9,
10 is in the closed state, so that the flip-flop 5 has the priority bit I for interrupt bus access.
Even if P is set, it will not be reset by the WIN signal generated for a normal bus access.

Therefore, for example, when the next common bus access is the interrupt bus access, the priority bit IP is input to the common bus arbitration unit 3 by the input of the interrupt bus access signal. The bus arbitration unit 3 can activate the bus arbitration by setting the priority bit.

As described above, according to the circuit of this embodiment, the common bus arbitration unit 3 can alternately repeat the setting and resetting of the priority bit for each bus acquisition operation for the interrupt bus access. Load of each processor can be evenly distributed.

It should be noted that when the bus is successfully acquired, the slave I /
When the slave board such as O is accessed and the I / O board or the like passes the correct interrupt vector, an ACK signal is returned from the I / O board or the like via the common bus 20, and this ACK signal is ANDed. CPU through gate 12
Input to 1.

If the bus acquisition fails, the common bus arbitration unit 3 generates a LOSE signal, and the LOSE signal is transmitted via the AND gate 14 and the OR gate 16 to the CPU 1
A spurious interrupt vector is generated by inputting the input to, and the access for acquiring the interrupt vector is terminated.

FIG. 3 shows an operation flow of the circuit of the above embodiment. The operation of the embodiment circuit will be described with reference to FIG. 3. When a common bus use request occurs, if it is a normal bus access, bus arbitration is performed through the same operation flow (FIG. 7) as in the conventional case. As a result, when the common bus cannot be acquired, if the own panel ID is smaller than the ID on the common bus, the priority bit NP for normal bus access is set, and next time normal bus access is arbitrated. This priority bit NP is exercised when an action needs to be taken.

If the common bus use request is an interrupt vector acquisition access, arbitration is performed through the same operation flow (FIG. 7) as the conventional one. As a result, if the common bus cannot be acquired, the own panel ID is the ID on the common bus.
If it is smaller than the above, the priority bit IP for the interrupt is set, and this interrupt vector acquisition access at this time is terminated by giving the spurious interrupt vector, and when the next interrupt occurs and the interrupt vector acquisition access occurs. Uses this interrupt processing priority bit IP.

As a result, the bus usage for the normal bus access and the bus usage for the interrupt vector acquisition access are equally given to the respective processors independently of the running state of the software, so that the loads on the respective processors are equalized. .

FIG. 4 shows a bus arbitration circuit as another embodiment of the present invention. 4, the schematic configuration of this embodiment circuit is almost the same as that of the above-described embodiment circuit of FIG.
Circuits having the same functions as in FIG. 2 are given the same reference numerals. The difference is that, instead of the WIN signal from the common bus arbitration unit 3, the ACK signal from the common bus 20 is input as an input to the AND gate 10 on the flip-flop 5 side via the AND gate 12.

The reason for having such a configuration is as follows. The individual processors have different times until the interrupt bus access is activated in response to the interrupt request, depending on the running state and the like. Therefore, if the activation of the interrupt bus access is delayed by another processor due to the running state of software, the slave I / O board of the interrupt source has already notified the other processor of the interrupt vector and turned off the interrupt. May have In such a case, a BERR signal or the like is returned from the I / O boat to the processor, a spurious interrupt is given, and the interrupt bus access ends.

However, if the processor sends its own panel ID later than the other processors by that time, there is no competing other panel ID, so the ID on the common bus 20 matches the own panel ID, Therefore, the common bus arbitration unit 3 outputs the WIN signal, and there is a possibility that the flip-flop 5 for interrupt bus access may be reset although the interrupt processing is not executed. Therefore, when the strictness of interrupt distribution is further enhanced, the priority bit IP is set to OF in the above case.
Since it should not be F, the ACK signal to be sent when the slave I / O board has passed the correct vector is AN.
The AND gate 10 is opened and closed by inputting it to the AND gate 10 via the D gate 12, and the flip-flop 5 is reset. As a result, the local processor succeeds in the access to obtain the interrupt vector, and the I / O
The flip-flop 5 is reset only when the ACK signal is returned from the boat.

FIG. 5 shows a bus arbitration circuit as another embodiment of the present invention. Similar to the embodiment of FIG. 4 described above, this embodiment is designed to further ensure the strictness of interrupt distribution.

Comparing this embodiment circuit with the embodiment circuit of FIG. 3, the interrupt level decoder 19 and the AND gate 1
The AND gate 18 has a WIN signal and an A signal.
The output signal of the ND gate 17 is input to the AND gate 1
AND gate 1 instead of WIN signal as input to 0
The difference is that eight output signals are used. Here, the interrupt level decoder 18 is a circuit that decodes the interrupt response level of the CPU based on the address and control signal of the CPU 1, and the AND gate 17 is the interrupt level decoder 1.
This circuit compares the interrupt response level decoded in 8 with the interrupt response level of the interrupt signal on the common bus, and outputs "1" when they match.

In this way, the reset signal comes into the flip-flop 5 which manages the priority bit IP only when the response interrupt level of the CPU is active on the common bus during the interrupt bus access. Therefore, when the slave I / O board has already passed the interrupt vector to another processor and turned off the interrupt signal at the time of accessing the interrupt bus, the comparison result in the AND gate 17 becomes a non-coincidence. 18, 10 are closed and the priority bit IP of flip-flop 5 is not reset.

[0053]

As described above, according to the present invention, the equality of bus usage is guaranteed independently of normal bus access and interrupt bus access regardless of the running state of software. Therefore, the load applied to each processor in the multiprocessor configuration system is evenly distributed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a bus arbitration circuit as an embodiment of the present invention.

FIG. 3 is a diagram showing an operation flow of an embodiment circuit.

FIG. 4 is a diagram showing a bus arbitration circuit as another embodiment of the present invention.

FIG. 5 is a diagram showing a bus arbitration circuit as another embodiment of the present invention.

FIG. 6 is a diagram showing a multiprocessor configuration system.

FIG. 7 is a diagram showing an operation flow of a conventional bus arbitration circuit.

[Explanation of symbols]

1 CPU (Central Processing Unit) 2 Decoder 3 Common Bus Arbitration Unit 4 Flip-Flop for Managing Priority Bits for Normal Bus Access 5 Flip-Flops for Managing Priority Bits for Interrupt Bus Access 6-14, 17 AND Gate 15 , 16 OR gate 20 common bus

Claims (5)

[Claims] 1. A bus arbitration circuit provided in each processor for arbitrating bus access contention in a parallel processing type multiprocessor system, which decodes a control signal or the like from a CPU (31). The bus request signal that requests bus acquisition based on the decoding result and the bus access are normal bus access or interrupt bus
A decoding unit (32) that generates a bus access determination signal that determines whether it is an access, and when the bus request signal is received, bus arbitration for bus acquisition is applied to the bus (36) and priority bits are appropriately used. And a bus arbitration unit (33) for executing interrupt bus access priority based on the bus access determination signal.
An interrupt bus access management unit (34) that sets / resets a bit, and a normal bus access management unit (34) that sets / resets a priority bit for normal bus access for normal bus access based on the bus access determination signal ( Three
5) A bus arbitration circuit comprising: 2. The interrupt bus access management unit is configured to set a priority bit for interrupt bus access when bus acquisition by interrupt bus access fails and reset when the bus acquisition is successful. 2. The bus arbitration circuit according to claim 1, wherein the bus access management unit is configured to set the priority bit for normal bus access when the bus acquisition by the normal bus access fails and to reset it when it succeeds. 3. The interrupt bus access management unit is configured to reset the interrupt bus access priority bit on condition that an ACK signal is received from the bus for the interrupt bus access. The bus arbitration circuit according to claim 1 or 2. 4. An interrupt level decoder for decoding an interrupt response level of interrupt bus access based on a control signal from a CPU, an interrupt response level from the interrupt level decoder and an interrupt response level of an interrupt signal on the bus. The interrupt bus access management unit is configured to reset the interrupt bus access priority bit on condition that the comparison results of the comparison unit match. The bus arbitration circuit described in 1 or 2. 5. A bus arbitration method for arbitrating bus access contention in a parallel processing multiprocessor system, wherein priority bit management for equalizing opportunities for bus acquisition is managed from a slave board. Bus arbitration method, which is characterized in that the interrupt priority bit used for interrupt bus access to the above interrupt request and the normal priority bit used for normal bus access are separately performed.