JPH06302767A - Test pattern - Google Patents

Abstract

(57) [Abstract] [Purpose] To determine whether or not the transistor characteristic variation factor is the gate length dimension, and accurately evaluate / analyze the characteristics of the miniaturized MOS transistor in a short period of time. In the MOS transistor characteristic measuring test pattern, a diffusion layer pattern 101 and the diffusion layer 10 are provided.
1 and a gate electrode pattern 102 that intersects 1, and both ends of the diffusion layer 101, both ends of the gate electrode 102, and measurement pads of five terminals of the substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern for evaluating / analyzing the characteristics of a semiconductor device, and more particularly to a test pattern for evaluating / analyzing the characteristics of a miniaturized MOS transistor.

[0002]

2. Description of the Related Art In recent years, in order to achieve high integration of LSIs, miniaturization of processing dimensions has been advanced. Regarding the processing dimension of the gate length (L) of MOS transistors, even in the mass production level of factories, it is in the sub-micron era of less than 1 μm.
The characteristics of the MOS transistor are affected by various conditions such as pattern size and heat treatment history. In particular, the influence of the gate length (L) size is very large. For evaluation / analysis of transistor characteristics, it is very important to separate whether the characteristic variation is due to the gate length (L) dimension. Therefore, various test patterns for evaluating the gate length (L) have been conventionally developed.

An example of the above-mentioned conventional test pattern will be described below with reference to the drawings. FIG. 4 is a schematic diagram of a conventional test pattern. Figure 4 (a) shows MOS
This is a test pattern for measuring transistor characteristics.
FIG. 4B is a test pattern for measuring gate electrode wiring resistance.

In FIG. 4A, the gate length (L) is 1.
An N-type MOS transistor of 0 μm and a gate width of 20 μm is installed. The N-type diffusion layer 401 is separated by a gate electrode 402 into two regions to be a source / drain. Aluminum wiring 4 is formed on the separated N-type diffusion layer 401 through contact holes 403b and 403c, respectively.
04b and 404c are connected. On the other hand, the aluminum wiring 4 is formed on the gate electrode through the contact hole 403a.
04a is connected. An aluminum wiring 404d is connected to a P-type diffusion layer 406 for taking a potential of the P-type substrate via a contact hole 403d. Aluminum wirings 404a-404d are probe pads 405a-
It is connected to 405d. In FIG. 4B, a gate electrode wiring resistor 409 having a length of 1 mm and a width of 1.0 μm is installed. Both ends 410 of the gate electrode wiring pattern
a and 410b are contact holes 411a and 41, respectively.
It is connected to the probe pads 412a and 412b via 1b.

With respect to the test pattern configured as described above, its measurement and evaluation method will be described below. Figure 4
In (a), probe pads 405a to 405d
Gate, source, drain, substrate potential to
Measure the transistor characteristics. On the other hand, the sheet resistance of the gate electrode wiring pattern is obtained from the fan-de-apo pattern (not shown).

In FIG. 4B, the probe pad 4 is used.
The gate electrode wiring resistance R is obtained by applying a constant current (for example, 10 μA) between 12a and 412b and measuring the potential difference generated between the probe pads 412a and 412b.

The gate electrode wiring resistance R is expressed by (Equation 1). ρ is the sheet resistance of the gate electrode wiring pattern, L
Indicates the gate electrode wiring pattern wiring length (1 mm in this example) of FIG. 4B, and W indicates the gate electrode wiring pattern width (design value 1.0 μm) of FIG. 4B.

[0008]

[Equation 1]

The equation (1) is transformed into the equation (2), and in the equation (2), the sheet resistance ρ of the gate electrode obtained from the fan-deapo pattern, the gate electrode wiring length L in FIG. The gate electrode wiring resistance R is substituted. As a result, the effective gate electrode wiring pattern width W is obtained.

[0010]

[Equation 2]

A correlation between the transistor characteristic and the gate electrode wiring width is obtained from the transistor characteristic (for example, saturation current) measured in FIG. 4A and the gate electrode wiring pattern width W obtained in FIG. 4B. When the saturation current fluctuates due to the fluctuation of the gate electrode wiring width, the larger the saturation current, the smaller the gate electrode wiring width. The width of the gate electrode wiring increases as the saturation current decreases. On the other hand, if the transistor characteristics are fluctuating due to causes other than the fluctuation of the gate electrode wiring width, this relationship is not established. Therefore, by evaluating both the saturation current value of the transistor and the gate electrode wiring width using the test patterns of FIG. 4A and FIG. 4B, whether the transistor characteristic variation is caused by the gate length dimension. Please be able to separate.

[0012]

However, in the above structure, the pattern of FIG. 4A is used for measuring the transistor characteristics, and the pattern of FIG. 4B is used for measuring the gate electrode processing dimension.
Pattern is used. Since the pattern for measuring the transistor characteristics is different from the pattern for measuring the gate electrode processing dimension, the gate processing dimension of the pattern in which the transistor characteristics are actually measured cannot be measured. The pattern density of the gate electrode pattern is different between the pattern for measuring the transistor characteristics and the pattern for measuring the processing size of the gate electrode, and therefore the difference in size conversion during resist pattern formation and etching is different in each pattern. This difference is remarkable in submicron devices, which are becoming finer. Therefore, the conventional method has a problem that the size conversion difference due to the pattern density becomes large, and the error in estimating the transistor gate length size from the gate electrode wiring resistance becomes large. In addition, the conventional method has a problem that two types of patterns are required for measurement and a large area is required.

In view of the above problems, the present invention provides a test pattern capable of highly accurately evaluating / analyzing the correlation between the transistor characteristics and the gate electrode wiring width even in a submicron device in which miniaturization progresses.

[0014]

In order to solve the above problems, a test pattern of the present invention is a test pattern for measuring MOS transistor characteristics, which comprises a diffusion layer pattern,
A gate electrode pattern that intersects with the diffusion layer, and both ends of the diffusion layer, both ends of the gate electrode, and 5 of the substrate.
It is provided with a pad for measuring terminals.

[0015]

According to the present invention, since the single transistor characteristic measurement and the transistor gate electrode resistance measurement are performed using the same test pattern with the above-described configuration, it is isolated whether the transistor characteristic variation is due to the gate length dimension. be able to. As a result, the characteristics of the miniaturized MOS transistor can be accurately evaluated / analyzed in a short period of time.

[0016]

【Example】

(Embodiment 1) A test pattern according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic diagram of a test pattern in an embodiment of the present invention.

In FIG. 1, the gate length (L) is 0.5 μ
An N-type MOS transistor having m and a gate width (W) of 10 μm is installed. The N-type diffusion layer 101 is the gate electrode 102.
Are separated into two regions to be the source / drain. Aluminum wires 104b and 104c are connected to the separated N-type diffusion layer 101 through contact holes 103b and 103c, respectively. On the other hand, contact holes 103a and 10 are formed at both ends of the gate electrode, respectively.
Aluminum wirings 104a and 104e are connected via 3e. P-type diffusion layer 10 for taking the potential of the P-type substrate
Aluminum wiring 104d is connected to 6 through a contact hole 103d. Aluminum wiring 104a-10
4e is connected to each of the probe pads 105a to 105e.

With respect to the test pattern configured as described above, its measurement and evaluation method will be described below. Figure 1
In, the gate, source, drain, and substrate potentials are applied to the probe pads 105a to 105d, respectively, and the characteristics of the single transistor are measured. Next, the probe pad 1
The gate electrode wiring resistance R is obtained by applying a constant current (for example, 10 μA) between 05a and 105e and measuring the potential difference generated between the probe pads 105a and 105e. Further, the sheet resistance of the gate electrode is obtained from the fan-de-apo pattern (not shown) of the gate electrode. The gate electrode wiring resistance R is expressed by (Equation 3).

[0019]

[Equation 3]

Ρ is the sheet resistance of the gate electrode, L is the gate length in the N-type MOS transistor of FIG. 1, and shows the gate electrode wiring pattern wiring width at the time of resistance measurement. W is the gate width in the N-type MOS transistor of FIG.
The gate electrode wiring pattern wiring length at the time of resistance measurement is shown.
(Equation 3) is transformed into (Equation 4), and in (Equation 4), the sheet resistance ρ of the gate electrode obtained from the fan-de-apo pattern, the gate width W in FIG. 1, and the measured gate electrode wiring resistance R are shown. substitute.

[0021]

[Equation 4]

As a result, the effective gate electrode wiring pattern width L is obtained. A correlation between the transistor characteristic and the gate electrode wiring width is obtained from the transistor characteristic (for example, saturation current) measured using this test pattern and the gate electrode wiring pattern width L previously obtained. When the saturation current fluctuates due to the fluctuation of the gate electrode wiring width, the larger the saturation current, the smaller the gate electrode wiring width. The width of the gate electrode wiring increases as the saturation current decreases. On the other hand, if the transistor characteristics are fluctuating due to causes other than the fluctuation of the gate electrode wiring width, this relationship is not established.

As described above, according to the present embodiment, by evaluating both the saturation current value of the transistor and the gate electrode wiring width using the test pattern of FIG. 1, the transistor characteristic variation is caused by the gate length dimension. You can separate whether you are doing.

Although the N-type MOS transistor is used as the transistor in this embodiment, it may be a P-type MOS transistor. Along with this, the diffusion layer 101 is N-type, but may be P-type. The gate electrode 102 may be N-type, P-type polysilicon, or metal. Wiring 10
Although 4a to 104e are made of aluminum, other metals may be used as long as they have a lower resistance than the gate electrode.

(Embodiment 2) A test pattern according to an embodiment of the present invention will be described below with reference to the drawings. In Example 1, by evaluating both the saturation current value of the transistor and the gate electrode wiring width using the test pattern of FIG. 1, it is possible to separate whether the transistor characteristic variation is due to the gate length dimension. showed that. One test pattern in FIG. 1 is sufficient for qualitatively detecting the characteristic variation between lots. However, the one test pattern of FIG. 1 is not sufficient to quantitatively detect this variation and quantify the variation of the gate electrode size. In the present embodiment, the same configuration as the test pattern of FIG. 1 is used and only the gate length (L) is 0.4 μm to 0.8 μm.
Five types of test patterns differing by 1 μm are prepared, and the same evaluation as in Example 1 is performed for each.

FIG. 2 shows the relationship between the saturation current value and the gate resistance of each test pattern having different gate lengths (L). There is a strong correlation between the saturation current value and the gate resistance. These measurement points are data obtained from the same wafer and differ only in the gate length (L). A shows the measured data of the test pattern of L = 0.5 μm. L is thin in the B direction (L <0.
5 μm) test pattern data, and in the C direction, L is thick (L> 0.5 μm) test pattern data. Therefore, when the processed size of the gate electrode of the test pattern having the gate length L = 0.5 μm is smaller than the prescribed 0.5 μm, the test pattern measurement result moves in the B direction on this straight line. When it becomes thicker than 0.5 μm, it moves in the C direction. That is, when the transistor characteristic is fluctuating due to the fluctuation of the gate electrode wiring width, the transistor moves on this straight line. This relationship is not established when the transistor characteristics fluctuate due to causes other than the fluctuation of the gate electrode wiring width. Therefore, it deviates from this straight line. Further, when the measurement result is on this straight line, the gate electrode processing dimension can be quantitatively estimated from the value of the gate electrode resistance. FIG. 3 shows the relationship between the reciprocal of the gate electrode resistance measurement value in the test pattern of each gate length (L) dimension and the estimated gate electrode dimension obtained from the equation (2). From FIG. 3, the gate electrode processing dimension can be quantitatively estimated from the value of the gate electrode resistance.

As described above, according to this embodiment, only the gate length (L) is 0.4 with the same structure as the test pattern of FIG.
By preparing 5 types of test patterns that differ by 0.1 μm from μm to 0.8 μm and evaluating both the saturation current value of the transistor and the width of the gate electrode wiring, is it possible that the transistor characteristic fluctuation is caused by the gate length dimension? Please separate quantitatively.

Although the N-type MOS transistor is used as the transistor in this embodiment, it may be a P-type MOS transistor. Along with this, various diffusion layers, gate electrodes, wiring metals, etc. can be selected as in the first embodiment.

Although the foregoing invention has been described in detail by way of illustration and example method for clarity of understanding, it is obvious that certain changes and modifications may be made within the scope of the appended claims.

[0030]

As described above, the present invention provides a test pattern for measuring MOS transistor characteristics, which comprises a diffusion layer pattern and a gate electrode pattern which intersects with the diffusion layer, and which includes both ends of the diffusion layer and the gate electrode. By providing the measuring pads on both ends and the five terminals of the substrate, it is possible to separate whether or not the variation in the transistor characteristics is due to the gate length dimension. As a result, the characteristics of the miniaturized MOS transistor can be accurately evaluated / analyzed in a short period of time.

[Brief description of drawings]

FIG. 1 is a schematic layout diagram of a test pattern according to a first embodiment of the present invention.

FIG. 2 is a gate length (L) in the second embodiment of the present invention.
Diagram showing the relationship between the saturation current value and the gate resistance of each test pattern of different

FIG. 3 is a diagram showing the relationship between the reciprocal of the gate electrode resistance measurement value of the test pattern of each gate length (L) dimension and the estimated gate electrode dimension obtained from the equation (2) in the example.

FIG. 4 is a schematic layout diagram of a conventional test pattern.

[Explanation of symbols]

 101 N-type diffusion layer 102 Gate electrode 103a-e Contact hole 104a-e Aluminum wiring 105a-e Pad 106 P-type diffusion layer

Claims (4)

[Claims] 1. A test pattern for measuring MOS transistor characteristics, comprising a diffusion layer pattern and a gate electrode pattern intersecting the diffusion layer, and measuring both ends of the diffusion layer, both ends of the gate electrode, and five terminals of a substrate. A test pattern characterized by having a pad for use. 2. A test pattern, wherein the ratio (W / L) of the gate length L and the gate width W of the MOS transistor according to claim 1 is 10 or more. 3. A test pattern comprising a plurality of test patterns having a constant gate width W and different gate lengths L of the MOS transistor according to claim 1. 4. A test pattern comprising a structure in which a plurality of contact holes are provided at both ends of the gate electrode pattern of the MOS transistor according to claim 1, and the MOS transistor is connected to a metal wiring layer.