JPH0630355A - Afc circuit for bs tuner - Google Patents

Afc circuit for bs tuner

Info

Publication number
JPH0630355A
JPH0630355A JP4118261A JP11826192A JPH0630355A JP H0630355 A JPH0630355 A JP H0630355A JP 4118261 A JP4118261 A JP 4118261A JP 11826192 A JP11826192 A JP 11826192A JP H0630355 A JPH0630355 A JP H0630355A
Authority
JP
Japan
Prior art keywords
tuner
afc
aftv
channel
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4118261A
Other languages
Japanese (ja)
Inventor
Yoshishiro Yukiyoshi
良白 雪吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4118261A priority Critical patent/JPH0630355A/en
Publication of JPH0630355A publication Critical patent/JPH0630355A/en
Pending legal-status Critical Current

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  • Television Receiver Circuits (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE:To prevent the deterioration in reception performance at the time of selection of a MUSE signal channel. CONSTITUTION:The circuit is provided with a BS tuner 1 receiving a keyed AFC pulse AFCP in a High Vision broadcast and with a BSCPU2 receiving AFT voltages AFTV(+), AFTV(-) obtained by detecting a 2nd intermediate frequency signal outputted from the BS tuner 1, receiving channel selection data SD to select a channel and inputting a clock CLK based on the channel selection data SD and the AFT voltages AFTV(+), AFTV(-) to the BS tuner 1, and the BSCPU2 latches the channel selection data till the keyed AFC pulse AFCP is inputted to the BS tuner 1 in the case of MUSE signal channel selection to stop the AFC operation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はハイビジョン放送を受信
するBS (衛星放送) チューナのAFC 回路に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AFC circuit of a BS (satellite broadcast) tuner for receiving high-definition broadcast.

【0002】[0002]

【従来の技術】ハイビジョン放送を受信する従来のBSチ
ューナのAFC(自動周波数制御) 回路方式では、図1に示
す如くMUSE信号チャンネル選局直後の約1秒間、即ちチ
ャンネル選局時点t0 から外部機器である例えばMUSEデ
コーダ又はMUSE/NTSCコンバータ等からキードAFC パル
スが入力される時点t1 までの期間は、BSチューナが平
均値AFC 動作をする。そのためMUSE信号の送信内容によ
り、BSチューナの局部発振周波数が2〜MHz 以上変化す
る場合がある。いま、局部発振周波数が仮に高い方向へ
変化して、受信性能が低下し始める局部発振周波数fH
を超えると、BSチューナの第2中間周波数がFM復調帯域
の中心からズレるためハイビジョン放送の受信性能が低
下し易くなる。
2. Description of the Related Art In the conventional AFC (automatic frequency control) circuit system of a BS tuner for receiving high-definition broadcasting, as shown in FIG. 1, the MUSE signal channel is selected for about 1 second, that is, from the channel selection time t 0 to the outside. The BS tuner operates as an average value AFC until the time t 1 when a keyed AFC pulse is input from a device such as a MUSE decoder or MUSE / NTSC converter. Therefore, the local oscillation frequency of the BS tuner may change by 2MHz or more depending on the contents of the MUSE signal. Now, if the local oscillation frequency fluctuates to a higher direction and the reception performance begins to deteriorate, the local oscillation frequency f H
If it exceeds, the second intermediate frequency of the BS tuner deviates from the center of the FM demodulation band, and thus the reception performance of high-definition broadcasting tends to deteriorate.

【0003】[0003]

【発明が解決しようとする課題】前述したようにMUSE信
号チャンネル選局時に、受信性能が低下すると、映像信
号系のトランケーションノイズ、S/N 、PCM 音声データ
のビットエラー等が現れるという問題がある。本発明は
斯かる問題に鑑み、MUSE信号チャンネル選局時に受信性
能が低下することがないBSチューナのAFC 回路を提供す
ることを目的とする。
As described above, when the MUSE signal channel is selected, if the reception performance is deteriorated, truncation noise of the video signal system, S / N, bit error of PCM audio data, etc. appear. . In view of such a problem, it is an object of the present invention to provide an AFC circuit for a BS tuner that does not deteriorate the reception performance when selecting a MUSE signal channel.

【0004】[0004]

【課題を解決するための手段】本発明に係るBSチューナ
のAFC 回路は、ハイビジョン放送におけるキードAFCパ
ルスが入力されるBSチューナのAFC 回路において、前記
BSチューナの中間周波数を検波して得たAFT 電圧が入力
され、該AFT 電圧及びチャンネルを選局する選局データ
に関連するクロックを、BSチューナへ入力するCPU を備
え、前記CPU に選局データを与えた時点から前記キード
AFC パルスが入力されるまでの期間は、選局データを保
持してAFC 動作を停止させ、チャンネル選局時における
BSチューナの局部発振周波数のずれを防止すべく構成し
てあることを特徴とする。
The AFC circuit of a BS tuner according to the present invention is the AFC circuit of a BS tuner to which a keyed AFC pulse in high-definition broadcasting is input,
The AFT voltage obtained by detecting the intermediate frequency of the BS tuner is input, and the AFT voltage and the clock related to the tuning data that selects the channel are provided with a CPU that inputs the tuning data to the CPU. From the time of giving
During the period until the AFC pulse is input, the tuning data is retained and the AFC operation is stopped.
It is characterized in that it is configured to prevent deviation of the local oscillation frequency of the BS tuner.

【0005】[0005]

【作用】MUSE信号チャンネルを選局した直後は、CPU に
より選局データを保持して、BSチューナにキードAFC パ
ルスが入力されるまでAFC 動作を停止させる。保持した
選局データによりBSチューナの局部発振周波数を制御
し、局部発振周波数のズレが少なくなる。キードAFC パ
ルスが入力されると、BSチューナが出力するAFT 電圧を
モニタして、CPU によりキードAFC 動作をさせる。
[Function] Immediately after selecting the MUSE signal channel, the CPU holds the tuning data and stops the AFC operation until the keyed AFC pulse is input to the BS tuner. The local tuning frequency of the BS tuner is controlled by the held tuning data, and the deviation of the local tuning frequency is reduced. When a keyed AFC pulse is input, the AFT voltage output by the BS tuner is monitored and the CPU operates the keyed AFC.

【0006】これにより、MUSE信号チャンネル選局直後
に、BSチューナの局部発振周波数が大きくズレず、ハイ
ビジョン放送の受信性能が低下しない。
As a result, the local oscillation frequency of the BS tuner does not greatly shift immediately after the selection of the MUSE signal channel, and the reception performance of high-definition broadcasting does not deteriorate.

【0007】[0007]

【実施例】以下本発明をその実施例を示す図面により詳
述する。図2は本発明に係るBSチューナのAFC 回路の要
部構成を示すブロック図である。外部機器からのBS中間
周波数BS−IFが入力されるBSチューナ1には、外部機器
であるMUSEデコーダ又はMUSE/NTSCコンバータ等が出力
するキードAFC パルスAFCPが入力される。このBSチュー
ナ1には例えば品番CXA1401MのICが用いられる。BSチュ
ーナ1が出力する第2中間周波数を検波して得たAFT 電
圧AFTV (+) , AFTV (−) はBSCPU 2へ入力される。BS
CPU 2が出力するPLL データであるクロックCLK はBSチ
ューナ1の第2中間周波数を制御する図示しないPLL 回
路へ入力される。リモートコントロール送信器3が送信
するチャンネル選局信号は、チャンネル選局CPU 4へ送
信され、チャンネル選局CPU 4が出力する選局データSD
はBSCPU 2へ入力される。
The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 2 is a block diagram showing a main configuration of the AFC circuit of the BS tuner according to the present invention. To the BS tuner 1 to which the BS intermediate frequency BS-IF from an external device is input, a keyed AFC pulse AFCP output from a MUSE decoder or MUSE / NTSC converter which is an external device is input. For this BS tuner 1, for example, an IC with a product number CXA1401M is used. The AFT voltages AFTV (+) and AFTV (-) obtained by detecting the second intermediate frequency output from the BS tuner 1 are input to the BSCPU 2. BS
A clock CLK, which is PLL data output from the CPU 2, is input to a PLL circuit (not shown) that controls the second intermediate frequency of the BS tuner 1. The channel tuning signal transmitted by the remote control transmitter 3 is transmitted to the channel tuning CPU 4 and the channel tuning data SD output by the channel tuning CPU 4
Is input to BSCPU 2.

【0008】次にこのBSチューナのAFC 回路のチャンネ
ル選局時の動作を、BSチューナ1及びBSCPU 2の動作内
容を示す図3とともに説明する。リモートコントロール
送信器3を操作してMUSE信号チャンネルを選局すると、
チャンネル選局CPU 4から選局データSDをBSCPU 2へ入
力し、選局データSDに関連するクロックCLK をBSチュー
ナ1の図示しないPLL 回路へ入力する。それによりBSチ
ューナ1の局部発振周波数が制御される。BSチューナ1
は、その第2中間周波数をAFT 検波する。AFT検波したA
FT 電圧AFTV (+) , AFTV (−) は、第2中間周波数よ
り局部発振周波数が低いときはAFTV (+) が「0」、AF
TV (−) が「1」になり、高いときはAFTV (+) が
「1」、AFTV (−) が「0」になる。また第2中間周波
数と局部発振周波数が等しいときはAFTV (+) , AFTV
(−) がともに「1」になる。このAFT電圧AFTV (+) ,
AFTV (−) をBSCPU 2が取込む。このAFT 電圧AFTV
(+) , AFTV (−) に基づいてクロックCLK を制御し、
第2中間周波数のズレを選局データSDに基づいて補正す
べく、局部発振周波数を制御する。
Next, the operation of the AFC circuit of the BS tuner at the time of channel selection will be described with reference to FIG. 3 showing the operation contents of the BS tuner 1 and the BSCPU 2. When you operate the remote control transmitter 3 and select the MUSE signal channel,
Channel tuning CPU 4 inputs tuning data SD to BSCPU 2, and clock CLK related to tuning data SD is input to a PLL circuit (not shown) of BS tuner 1. Thereby, the local oscillation frequency of the BS tuner 1 is controlled. BS tuner 1
Performs AFT detection on the second intermediate frequency. AFT detected A
The FT voltages AFTV (+) and AFTV (-) have AFTV (+) of "0" and AF when the local oscillation frequency is lower than the second intermediate frequency.
When TV (−) becomes “1”, when it is high, AFTV (+) becomes “1” and AFTV (−) becomes “0”. When the second intermediate frequency is equal to the local oscillation frequency, AFTV (+), AFTV
Both (-) become "1". This AFT voltage AFTV (+),
BSCPU 2 takes in AFTV (-). This AFT voltage AFTV
Control the clock CLK based on (+), AFTV (-),
The local oscillation frequency is controlled so as to correct the deviation of the second intermediate frequency based on the tuning data SD.

【0009】前述したようにしてクロックCLK をBSチュ
ーナ1の図示しないPLL 回路へ入力する動作から、第2
中間周波数ズレを選局データSDに基づいて補正し、BSチ
ューナの局部発振周波数を制御するまでの一連の動作を
繰り返して局部発振周波数を収束させることになる。こ
の一連の動作は、MUSE信号チャンネル選局時も同様に行
われ、チャンネル選局直後、即ち図2に示すようにMUSE
信号チャンネル選局時点t0 から約1秒間はキードAFC
パルスAFCPが入力されないので、BSチューナ1内のAFT
回路は保持した選局データに基づいて平均値AFC 動作を
する。このときMUSE信号の内容によっては局部発振周波
数が数MHz ズレる可能性があるのでキードAFC パルスが
入力されるまではAFC 動作を停止させる。つまりBSCPU
2に取込んだAFT 電圧AFTV (+) , AFTV (−) を無視
し、選局プログラムによりMUSE信号チャンネル選局の選
局データを保持させる。
From the operation of inputting the clock CLK to the PLL circuit (not shown) of the BS tuner 1 as described above,
The intermediate frequency shift is corrected based on the tuning data SD, and a series of operations until controlling the local oscillation frequency of the BS tuner is repeated to converge the local oscillation frequency. This series of operations is similarly performed when the channel of the MUSE signal is selected, and immediately after the channel is selected, that is, as shown in FIG.
Keyed AFC for approximately 1 second from the time t 0 when the signal channel is selected
Since pulse AFCP is not input, AFT in BS tuner 1
The circuit operates the average value AFC based on the held tuning data. At this time, the local oscillation frequency may shift by several MHz depending on the contents of the MUSE signal. Therefore, the AFC operation is stopped until the keyed AFC pulse is input. That is BSCPU
The AFT voltages AFTV (+) and AFTV (-) fetched in 2 are ignored and the tuning data of the MUSE signal channel tuning is held by the tuning program.

【0010】次にキードAFC パルスが入力された時点t
1 では、キードAFC 動作をさせて、チャンネル選択直後
の局部発振周波数のズレを抑制する。それにより、チャ
ンネル選局時におけるハイビジョン放送の受信性能の低
下を防いで、ハイビジョン放送の受信状態を常に良好に
することができる。なお、本実施例ではチャンネル選局
のソフトウェアにより受信性能の低下を防止したが、ハ
ードウェアによりチャンネル選局時点t0 からキードAF
C パルスAFCPが入力される時点t1 までの期間、BSチュ
ーナ1におけるAFT 回路をミュートするようにしても同
様の効果が得られる。
Next time t when the keyed AFC pulse is input
In 1 , the keyed AFC operation is performed to suppress the deviation of the local oscillation frequency immediately after channel selection. As a result, it is possible to prevent the reception performance of high-definition broadcasting from being deteriorated when the channel is selected, and to always improve the reception state of high-definition broadcasting. In the present embodiment, the reception performance is prevented from being deteriorated by the channel selection software, but the keyed AF is performed from the channel selection time t 0 by the hardware.
The same effect can be obtained by muting the AFT circuit in the BS tuner 1 until the time t 1 when the C pulse AFCP is input.

【0011】[0011]

【発明の効果】以上詳述したように本発明によれば、MU
SE信号チャンネル選局時の局部発振周波数ズレを抑制し
て受信性能の低下を防止できる。そのためハイビジョン
放送を常に良好な状態で受信できるBSチューナのAFC 回
路を提供できる優れた効果を奏する。
As described above in detail, according to the present invention, the MU
It is possible to suppress the local oscillation frequency shift when the SE signal channel is selected and prevent the reception performance from deteriorating. Therefore, it has an excellent effect of being able to provide the AFC circuit of the BS tuner that can always receive the high-definition broadcast in a good condition.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来のBSチューナのAFC 回路における動作内容
の説明図である。
FIG. 1 is an explanatory diagram of operation contents in an AFC circuit of a conventional BS tuner.

【図2】本発明に係るBSチューナのAFC 回路の要部構成
を示すブロック図である。
FIG. 2 is a block diagram showing a main configuration of an AFC circuit of a BS tuner according to the present invention.

【図3】MUSE信号チャンネル選局時におけるAFC 動作内
容の説明図である。
FIG. 3 is an explanatory diagram of AFC operation contents when selecting a MUSE signal channel.

【符号の説明】[Explanation of symbols]

1 BSチューナ 2 BSCPU 3 リモートコントロール送信器 4 チャンネル選局CPU 1 BS tuner 2 BSCPU 3 Remote control transmitter 4 Channel tuning CPU

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ハイビジョン放送におけるキードAFC パ
ルスが入力されるBSチューナのAFC 回路において、 前記BSチューナの中間周波数を検波して得たAFT 電圧が
入力され、該AFT 電圧及びチャンネルを選局する選局デ
ータに関連するクロックを、BSチューナへ入力するCPU
を備え、前記CPU に選局データを与えた時点から前記キ
ードAFC パルスが入力されるまでの期間は、選局データ
を保持してAFC 動作を停止させ、チャンネル選局時にお
けるBSチューナの局部発振周波数のずれを防止すべく構
成してあることを特徴とするBSチューナのAFC 回路。
1. An AFC circuit of a BS tuner to which a keyed AFC pulse is input in high-definition broadcasting, an AFT voltage obtained by detecting the intermediate frequency of the BS tuner is input, and the AFT voltage and channel are selected. CPU that inputs the clock related to station data to the BS tuner
During the period from when the tuning data is given to the CPU until the keyed AFC pulse is input, the tuning data is retained and the AFC operation is stopped, and the local oscillation of the BS tuner at the time of channel tuning is performed. BS tuner AFC circuit characterized by being configured to prevent frequency shift.
JP4118261A 1992-04-10 1992-04-10 Afc circuit for bs tuner Pending JPH0630355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4118261A JPH0630355A (en) 1992-04-10 1992-04-10 Afc circuit for bs tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4118261A JPH0630355A (en) 1992-04-10 1992-04-10 Afc circuit for bs tuner

Publications (1)

Publication Number Publication Date
JPH0630355A true JPH0630355A (en) 1994-02-04

Family

ID=14732252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4118261A Pending JPH0630355A (en) 1992-04-10 1992-04-10 Afc circuit for bs tuner

Country Status (1)

Country Link
JP (1) JPH0630355A (en)

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