JPH0630355B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a semiconductor device, particularly an insulating layer for passivation thereof.

Background Art and its Problems For example, in a complementary MOS integrated circuit, there is a portion having a sectional structure as shown in FIG. That is, the figure shows a so-called field portion between one channel MOS element and another channel MOS element which is adjacent to the channel element, and an oxide is formed on the main surface of the semiconductor substrate corresponding to the field portion between both elements. A field insulating layer (4) is formed by sequentially stacking a silicon (SiO ₂ ) layer (1), an arsenic silicate glass layer (2) and a plasma CVD type silicon nitride layer (3).
Note that (5) is, for example, an N-type semiconductor substrate, (6) is a P-type island region that constitutes a so-called N-channel MOS transistor of one channel MOS element, and (7) is its source or drain. One of the N ^{+ type} diffusion regions. (8) is one P ^{+ type} diffusion region which serves as a source or a drain of a so-called P channel MOS transistor which forms another channel MOS element. Further, (9) and (10) are Al electrodes which are ohmic-connected to the diffusion regions (7) and (8), respectively. Therefore, in this case, the field insulating layer (4) is formed over the N type semiconductor substrate (5) and the P type island region (6). In this field insulating layer (4), the arsenic silicate glass layer (2) is used in lowering the flattening technology,
The plasma-enhanced silicon nitride layer (3) is used to prevent the Al electrode from being scratched and to prevent external impurities.

However, in such a structure of the field insulating layer (4), when an annealing treatment at a low temperature (for example, 400 ° C.) is performed, a positive charge is generated in the field insulating layer (4).
The phenomenon that the surface of the lower P-type island region (6) was inverted to the N-type and the leak current was increased occurred. The generation of this positive charge is
As a result of the experiment, it was found that hydrogen occurs in the interface between the arsenic silicate glass layer (2) and the silicon oxide layer (1) and hydrogen in the plasma CVD type silicon nitride layer (3) is involved. That is, As is annealed to fluidize the arsenic silicate glass layer (2), As diffuses into the silicon oxide layer (1), and the arsenic silicate glass layer (2) and the silicon oxide layer (1) are diffused.
A so-called As transition layer having a concentration distribution of As is formed at the interface. After this, a silicon nitride layer formed by plasma CVD
When (3) is deposited and annealed at 400 ° C., hydrogen H in the silicon nitride layer (3) diffuses in the arsenic silicate glass layer (2) and reaches the As transition layer. There, hydrogen H combines with oxygen O in the glass to form an OH group. As a result, As contained in the network in the glass cannot bond with oxygen O and becomes ionized. This results in the generation of positive charges.

According to this mechanism, the generation of positive charges can also occur at the so-called silicon gate portion where, for example, an As-doped polycrystalline silicon layer is formed on the gate insulating film made of SiO ₂ , and the threshold voltage at this time is generated. Fluctuations occur.

OBJECT OF THE INVENTION The present invention provides a semiconductor device that solves the above-mentioned problems caused by the generation of positive charges.

SUMMARY OF THE INVENTION According to the present invention, a plurality of electrical elements are formed on a main surface of a semiconductor substrate, and an element isolation region that isolates the electrical elements from each other is formed by P.
In a semiconductor device including a p-type semiconductor region, an oxide layer, an arsenic diffusion blocking layer on the oxide layer, and arsenic on the arsenic diffusion blocking layer are formed on at least a P-type semiconductor region of the element isolation region. It has a field insulating layer including an insulating layer containing hydrogen and a hydrogen containing layer on the insulating layer containing arsenic.

The present invention also provides an oxide layer, an arsenic diffusion blocking layer on the oxide layer, an arsenic containing layer on the arsenic diffusion blocking layer, and a hydrogen containing layer on the arsenic containing layer on the semiconductor region. And a gate portion composed of the arsenic-containing layer,
A semiconductor device in which the oxide layer serves as a gate insulating layer.

According to this structure, the diffusion of As from the arsenic-containing layer to the oxide layer is blocked, and the generation of positive charges is eliminated. Therefore, the surface state of the semiconductor substrate under the oxide layer is stabilized, and an increase in leak current or a change in threshold voltage is avoided.

Examples Examples of the present invention will be described below.

FIG. 2 shows an embodiment of the present invention, which is applied to the field portion between each MOS element in the complementary MOS integrated circuit as in FIG. In the figure, those parts corresponding to those in FIG. 1 are designated by the same reference numerals, and a duplicate description will be omitted.

In this example, as shown in FIG. 2, the N-type semiconductor substrate (5) and the P-type island region (6) are spread over the main surface of the semiconductor substrate corresponding to the field portion between the complementary MOS devices. As described above, a field insulating layer (12) is formed by sequentially laminating a silicon oxide layer (1), an arsenic diffusion blocking layer (11), an arsenic silicate glass layer (2) and a plasma CVD type silicon nitride layer (3). . As the arsenic diffusion blocking layer (11), plasma CVD type silicon nitride or CVD silicon nitride having a small diffusion coefficient of As is used.

With such a structure of the field insulating layer (12), when the arsenic silicate glass layer (2) is annealed, As is scattered by the arsenic diffusion blocking layer (11) and the silicon oxide layer (1 ) Side is not spread. For this reason, since the As transition layer is not formed, the generation of positive charges does not occur even if hydrogen in the silicon nitride layer (3) by plasma CVD comes thereafter.
Therefore, an inversion layer is not formed on the surface of the P-type island region (6), an increase in leak current is prevented, and a highly reliable complementary MOS integrated circuit is obtained.

In another embodiment of the present invention, As is formed on the silicon gate portion of the MOS transistor, especially on the gate insulating layer made of SiO _2.
It can be applied to a silicon gate portion having a contained polycrystalline silicon layer. That is, in this case, the arsenic diffusion blocking layer is interposed between the gate insulating layer and the As-containing polycrystalline silicon layer. In this structure, As of the polycrystalline silicon layer is not diffused into the SiO ₂ layer which is the gate insulating layer, and therefore, even if hydrogen enters later, no positive charge is generated. Therefore, the surface level of the channel portion is stable, and fluctuations in the threshold voltage are avoided.

As the arsenic diffusion blocking layer, the above-described plasma CVD type silicon nitride or CVD silicon nitride can be used.
AsSG (arsenic silicate glass) as arsenic-containing layer
Alternatively, it is As-doped polycrystalline silicon or the like. As hydrogen diffusion, hydrogen annealing or CV on the arsenic-containing layer is performed.
It is the presence of hydrogen during D film formation (Si ₃ N ₄ , amorphous Si, etc.).

EFFECTS OF THE INVENTION According to the present invention described above, the arsenic diffusion blocking layer is provided between the oxide layer on the main surface of the semiconductor substrate and the arsenic-containing layer in which hydrogen can be diffused. As of the arsenic-containing layer is not diffused into the oxide layer, and generation of positive charges is blocked. Therefore, a highly reliable semiconductor device can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a field portion of a conventional complementary MOS integrated circuit, and FIG. 2 is a complementary MO showing an embodiment of the present invention.
It is sectional drawing of the field part of S integrated circuit. (1) a silicon oxide layer, (2) an arsenic silicate glass layer, (3) a plasma CVD silicon nitride layer, (5) an N type semiconductor substrate, (6) a P type island region, (11) Is an arsenic diffusion blocking layer.

Claims (2)

[Claims] 1. A plurality of electrical elements are formed on a main surface of a semiconductor substrate, and an element isolation region for isolating the electrical elements from each other is formed by P.
In a semiconductor device including a p-type semiconductor region, an oxide layer, an arsenic diffusion blocking layer on the oxide layer, and an arsenic diffusion blocking layer are provided on at least a P-type semiconductor region of the element isolation region. A semiconductor device having a field insulating layer including an insulating layer containing arsenic and a hydrogen containing layer on the insulating layer containing arsenic. 2. An oxide layer, an arsenic diffusion blocking layer on the oxide layer, an arsenic containing layer on the arsenic diffusion blocking layer, and a hydrogen containing layer on the arsenic containing layer on the semiconductor region. A semiconductor device, comprising: a gate portion composed of a layer, the arsenic-containing layer serving as a gate electrode, and the oxide layer serving as a gate insulating layer.