JPH0630488B2 - Data transmission device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a start-stop synchronization data transmission device.

[Description of Prior Art] An example of a conventional start-stop synchronization data transmission device is shown in FIG.

This is an example of a data transmission device having a parity check function, in which a plurality of bits of data added with a parity bit are transmitted from a transmitter 1 to a receiver 3 via a data line 5.

The transmitter 1 starts a clock 9 based on the enable signal input from the enable signal input terminal 7, and the clock 9
A counter 11 for counting the number of oscillations of the clock and a clock signal from the clock 9 are input, and in synchronization with this clock signal, the n-bit parallel data D ₁ , D ₂ ... D _n input from the data input terminal 13 are started. A parallel-serial conversion shift register (hereinafter referred to as a P / S converter) 15 for adding a bit S and a parity bit P to serially output to the data line 5, a start bit adding circuit 17, and a parity adding circuit 19 are provided. Is configured.

On the other hand, the receiver 3 has the enable signal input terminal 21 as described above.
A clock 23 that prepares for activation based on an enable signal input from the clock signal, and a start bit that detects a start bit S at the beginning of data input through the data line 5 and outputs a clock signal for data reception from the clock 23. A detection circuit 25, a counter 27 that counts a clock signal output from the clock 23, and serial data D _n ... D ₂ and D ₁ following the start bit S from the data line 5 in synchronization with the clock signal. A serial / parallel shift register (hereinafter referred to as S / P) that inputs together with the parity bit P and outputs the input data D ₁ , D ₂ ... D _n in parallel to the data output terminal 31 according to the control signal from the parity check circuit 29.
(Abbreviated as converter) 33.

In the data transmission apparatus of the start-stop synchronization system having the transmitter 1 and the receiver 3 having the above configuration, the transmitter 1 inputs n-bit data from the data input terminal 13 and inputs the parity bit P
Then, the data is serially output to the data line 5, the data serially output from the receiver 3 is input in synchronization with the clock signal of the clock 23, a parity check is performed, and then the data is output to the data output terminal 31.

Here, if the period of the clock 9 of the transmitter 1 is T, the period of the clock 23 of the receiver 3 is adjusted to T in accordance with this, and the reception timing of the receiver 3 is the same as that of the transmission. The mode is such that reception is delayed by exactly 1/2 cycle T / 2 of the clock from the transmission timing of the machine. As a result, even if the clock 9 of the transmitter 1 and the clock 23 of the receiver 3 each have an error of ΔT, (n + 1) · (2 · ΔT) does not exceed the value of 1/2 of the cycle T. In the range, that is, the bit number n + 1 of the transmission data to which the parity bit is added is T / (4
-The data can be transmitted within the range not exceeding ΔT) without any synchronization deviation.

However, in such a conventional start-stop synchronization type data transmission apparatus, the number n + 1 of bits of transmission data to which the parity bit is added is T / T based on the error of the clocks respectively provided in the transmitter and the receiver as described above. The value must be smaller than (4 · ΔT), and the clock error ΔT must be reduced in order to increase the number of bits of transmission data. In this case, a highly accurate and expensive clock is required. There was a problem that it was necessary.

[Object of the Invention] The present invention solves the above problems and provides a data transmission apparatus capable of transmitting a plurality of bits of data without synchronization deviation without the need to further improve the clock accuracy of the transmitter / receiver. The purpose is to provide.

[Summary of the Invention] In order to achieve the above object, the present invention provides a parity adding means for adding two even and odd parity bits adjacently to a predetermined position in the middle of transmission data of a plurality of bits, and outputting a signal at a predetermined cycle. And a transmitter having serial data output means for sequentially outputting the data to which the parity bit is added to the NRZ signal bit by bit in synchronization with the signal from the first clock, and at a predetermined period. A second clock for outputting a signal, the serial data from the serial data output means,
Serial data input means for inputting bit by bit in synchronization with the signal from the second clock, and at least one of two parity bits at the predetermined position in the middle of the serial data input by the serial data input means. Parity check means for performing a parity check on the serial data excluding two parity bits, and a synchronization signal when the occurrence of a level change of the serial data from the serial data output means is detected. Edge detecting means for outputting to the timepiece and adjusting the signal output time of the second timepiece at the time when the level change occurs.

[Description of Embodiments] Hereinafter, the present invention will be described in detail with reference to an embodiment.

FIG. 1 is a circuit diagram showing a transmitter / receiver of a data transmission device.

The transmitter 35 outputs the second signal based on the enable signal A shown in FIG.
Clock 9 of synchronization T that outputs clock signal D shown in FIG.
And a counter 11 for counting the number of oscillations of the clock 9,
N-bit parallel data D input from the data input terminal 13 using the clock signal D from the clock 9 as a periodic signal.
_A start bit S and even and odd parity bits P ₂ and P ₁ are added to the beginning and the middle of ₁ , D ₂ ... D _n , and NRZ (Non Return to Zer) shown in FIG.
o) A P / S converter 37 that outputs a signal B, and a parity adding circuit 39 that adds the even-odd parity bit adjacently in the middle of data are configured.

On the other hand, the receiver 41 has the enable signal input terminal 2 as described above.
The clock 23 which oscillates under a predetermined condition in the cycle T on condition that the enable signal A is inputted from 1 and the start bit S at the head of the data inputted through the data line 5 are detected. 2 has a start bit detecting circuit 25 for outputting the clock signal E for data reception shown in FIG. 2E, and a counter 43 for counting the clock signal E output from the clock 23. Counter 4
3 counts the number of data bits, and has the function of stopping the oscillation of the clock 23 after counting the number of bits n + 2 of even-odd parity bits of n-bit data.

The receiver 41 has a data edge detection circuit 45.
The circuit 45 includes a one-shot multivibrator, detects the time when the NRZ signal B of the data changes from low level to high level or from high level to low level, and synchronizes with the detection time. Then, the synchronizing signal C is output.
This synchronizing signal C is output to the clock signal 23, and the clock 23
To reset. Therefore, the watch has an enable signal A
Is input and the data edge detection circuit 45 is reset when the data edge is detected, the oscillation occurs at the synchronous T from the input of the stop bit to the input of a predetermined amount of data. .

The receiver 41 has an S / P converter 47 and a parity check circuit 49. The S / P converter 47 sequentially inputs the n-bit data to which the even-odd parity bits P ₂ and P ₁ are added in the middle of the data, and outputs the input data to the parity check circuit 49. The parity check circuit 49 performs a parity check on the data using the parity bits P ₂ and P ₁ added in the middle of the data, and outputs the data to the data output terminal 31. That is, since the even parity bit and the odd parity bit are opposite to each other, a level change is always generated when these even and odd parity bits are adjacent to each other. Therefore, for example, even if all the data bits are high level or low level, the clock is reset at least once.

The operation of the transmitter 35 and the receiver 41 having the above configurations will be described below.

The transmitter 35 outputs n-bit data from the input terminal 13 to P /
The parity is added to the S converter 37, and the parity adding circuit adds even and odd parity P ₂ and P ₁ in the middle of the received data. The P / S converter 47 adds a start bit S to the head of these data, and sends the n-bit data to which the start bit S and the even / odd parity bits P ₂ and P ₁ have been added to the data line 5 as an NRZ signal. This transmission is performed in synchronization with the falling edge of the clock signal D shown in FIG. 2 (d).

On the other hand, the receiver 41 receives the NRZ signal input from the data line 5 in the start bit detection circuit 25, the data edge detection circuit 45, and the S / P converter 47. Therefore, the start bit detection circuit 25 detects the leading start bit S in the data signal shown in FIG. 2 (b), and causes the clock 23 to oscillate in synchronization with this. The clock 23 oscillates at a preset cycle T. The counter 27 counts this frequency.

The data edge detection circuit 45 detects the level change timing of the input NRZ signal, and outputs this timing as a synchronization signal C to the timepiece 23. The clock 23 is reset by this synchronizing signal C. Therefore, data transmission / reception is performed in synchronization with the synchronization signal C. As shown in FIG. 2 (e), the clock 23 of the transmitter is equal to the clock 9 of the receiver by Δ.
Even if it is delayed by t · n, it will be corrected by this synchronization signal C. In the present embodiment, since even-odd parity P ₂ and P ₁ are inserted at one place adjacent to each other in the middle of the data, the level change of the input data always appears once in the middle of the data. As shown in c), the level change appears at other times according to the level change of the input data, and the synchronizing signal C is output according to these level changes. Based on this, the clock 23 is reset each time. In other words, the second of the clock 23
The correction of Δt · n shown in FIG. 6C is the maximum value, and the timepiece 23 is actually corrected for each synchronization signal C with an error of a smaller value. The data received by the S / P converter 47 is parity-checked by the parity check circuit 49 and output from the data output terminal 31.

As described above, in the present embodiment, since the clock 23 is corrected in the receiver 41 at the intermediate position of the n-bit data D ₁ , D ₂ ... D _n and the change position of the sign level, the clock 23 becomes the clock 9. On the other hand, even if there is a predetermined amount of error, these errors can be removed by the correction, and a start-stop synchronization type data transmission device that does not cause synchronization deviation with a simple circuit configuration without increasing cost is formed. Will be able to.

In the above embodiment, an example in which two even and odd parity bits P ₂ and P ₁ are added to the intermediate position of n-bit data has been shown, but these even and odd parity may be provided adjacent to any position of the data. Of course, it can be added to a plurality of places.

Although the parity check circuit 49 has been described as checking both even and odd parity, it is actually sufficient to check either _one of the even and odd parity bits P ₂ and P _1. Of course.

EFFECTS OF THE INVENTION As described above, according to the present invention, on the transmitter side, two even and odd parity bits are adjacently added to a predetermined position in the middle of transmission data, and this data is received as serial data by an NRZ signal as a receiver. Output to. In addition, the receiver side uses at least one of the two parity bits to perform a parity check on the serial data excluding the two parity bits, and at the time when the level change of the serial data occurs, Second for inputting bit by bit
Since the output time of the clock signal is adjusted, for example, even if all the data bits of the transmission data are high level or low level, the clock is adjusted at least once, so it is accumulated according to the data bit length. It is possible to eliminate the clock error that occurs, and to reliably transmit the data of multiple bits without synchronizing deviation, and to correct the parity bit for the parity check of the signal output timing of the receiver clock. Since it is also used for the above, it also has an effect that the above effect can be realized with a simple configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a transmitter and a receiver showing an embodiment of the present invention, FIG. 2 is a time chart of each part of the transmitter and the receiver, and FIG. 3 is a circuit showing an example of a conventional data transmission device. It is a figure. 9 ... Transmitter clock 23 ... Receiver clock 37 ... P / S converter 39 ... Parity addition circuit 45 ... Data edge detection circuit 47 ... S / P converter 49 ... Parity check circuit

Front Page Continuation (72) Inventor Atsushi Sakagami 2 Takaracho, Kanagawa-ku, Yokohama, Kanagawa Nissan Motor Co., Ltd. (56) Reference JP 57-33850 (JP, A) JP 56-79540 (JP, A)

Claims (1)

[Claims] 1. A parity adding means for adding two even and odd parity bits adjacently to a predetermined position in the middle of transmission data of a plurality of bits, a first clock for outputting a signal at a predetermined cycle, and the parity bit. A transmitter having serial data output means for sequentially outputting the added data as an NRZ signal bit by bit in synchronization with the signal from the first clock; a second clock for outputting a signal at a predetermined cycle; Serial data from the data output means,
Serial data input means for inputting bit by bit in synchronization with the signal from the second clock, and at least one of two parity bits at the predetermined position in the middle of the serial data input by the serial data input means. Parity check means for performing a parity check on the serial data excluding two parity bits, and a synchronization signal when the occurrence of a level change of the serial data from the serial data output means is detected. A data transmission device, comprising: an edge detection unit that outputs the signal to a timepiece and adjusts the signal output time of the second timepiece when the level change occurs.