JPH06309082A - Key scan circuit - Google Patents

Abstract

PURPOSE:To obtain the key scan circuit which does not use a diode for reverse current prevention by adding a pull-down resistance to each input port of a key scan circuit which has output lines and input lines wired in matrix and also has keys connected to the intersections and using a P-ch open-drain output for each output port. CONSTITUTION:The output lines L1-L4 connected to output ports OUT 01-OUT 04 and the input lines R1-R4 connected to input ports IN 01-IN 04 are wired in matrix, and Line keys S1-S9, S*, SO, and S# which are closed by being pressed are connected to the intersections of the output lines L1-L4 and input lines R1-R4. Then buffers BFI-BF4 are provided between the output ports OUT 01-OUT 04 and output lines L1-L4, and pull-down resistances are added to the input ports IN 01-IN 04. A buffer circuit consists of a P-ch FET, etc., and the pull-down resistances are attached to the sides of the respective input ports IN 01-IN 04.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key scan circuit for detecting the depression of a key used in, for example, a button telephone, and more particularly to a key scan circuit for recognizing a depressed key using a matrix method.

[0002]

2. Description of the Related Art A conventional key scan circuit will be described with reference to FIG. 6 and its operation with reference to FIG. First, in FIG. 6, OUT01 to OUT04 are output ports for output data sequentially output by scanning, and L1 to L4
Is an output line connected to the output ports OUT01 to OUT04. IN01 to IN04 are input ports for inputting detection data for detecting a key press, and R1 to R4 are input lines connected to the input ports IN01 to IN04. These output lines L1 to L
4 and the input lines R1 to R4 are wired in a matrix. At the intersections of these output lines L1 to L4 and input lines R1 to R4, keys S1 to S9, which are closed by pressing the keys,
S *, S0 and S # are connected. Output ports OUT01 to OUT04 and input ports IN01 to IN0
Reference numeral 4 is built in the CPU unit 1. Reference numeral 2 is a backflow prevention diode.

FIG. 7 is a timing chart of the key scan circuit. In the figure, key S2 and key S
Due to the double pressing of 5, the output lines L1 and L2 are short-circuited to each other during the periods (1) and (2), which are simultaneously pressed. During the period (1), the output line L1 of the output port OUT01 is at high level V _DD , and the output line L2 of the output port OUT02 is at low level GND. Also, during the period of (2), the output line L2 of the output port OUT02 is at the high level V
A _DD, the output line L1 of the output port OUT01 is GND low. Therefore, a large current may flow into the output port OUT02 during the period (1), and a large current may flow into the output port OUT01 during the period (2). In this way, if you press the key twice, CP
The output ports of the U section 1 are short-circuited to each other and the outputs collide. At this time, if one of the shorted output ports is at a high level and the other is at a low level, a large current may flow into the low level output port. Also, the output port OU
Since T01 and OUT02 are also short-circuited with the input port IN03, the potential of IN03 becomes unstable when the output ports are short-circuited, which may cause the key to be erroneously recognized. Therefore, the normal output ports OUT01 to OUT
A backflow prevention diode 2 is inserted between 04 and the output lines L1 to L4.

[0004]

However, in the conventional key scan circuit, the backflow prevention diode 2 is connected to the output port O.
Since it is provided between the output lines L1 to L4 of the UT01 to OUT04 and the wiring of the key circuit is complicated, the workability is poor and the production efficiency is hindered.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a key scan circuit that does not use a backflow prevention diode. Further, by using the 3-state output buffer circuit, erroneous recognition of the key can be eliminated.

[0006]

In order to solve the above problems, a key scan circuit of the present invention detects an output line from an output port for sending output data sequentially sent by scanning, and a key press. In the key scan circuit in which the input lines to the input ports for inputting the detection data are wired in a matrix, and the keys are connected to the intersections, pull-down resistors are added to each of the input ports and Is characterized by using P-ch open drain output.

Further, the key scan circuit of the present invention connects the output line from the output port for sending the output data sequentially sent by the scan and the input port for inputting the detection data for detecting the pressing of the key. In a key scan circuit in which input lines are wired in a matrix and keys are connected to the intersections, each output buffer is in an ON state when high level output data is output, and the high level output data is output. Is output when it is not output, and is characterized in that it is sequentially switched according to the output data sequentially sent by scanning.

[0008]

The output data sequentially sent by scanning is sent from each output port to each corresponding buffer. When the high level output data is output, the corresponding buffer is in the ON state, and the high level output is output from the buffer to the output line. When high-level output data is not output, the corresponding buffer is in the OFF state, and the output line has the high impedance disconnected from the output circuit. Therefore, even if the key is pressed twice, the key scan can be performed without a large current flowing into the output port, and the configuration of the key circuit can be simplified by incorporating the buffer circuit in the CPU section.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The components denoted by the same reference numerals as those in FIG. 6 and FIG. FIG. 1 shows a key scan circuit according to the present invention. The difference from the conventional example shown in FIG.
Buffers BF1 to BF4 are provided instead of the above, and pull-down resistors (P.D.
R. ) Is added. Each buffer BF1 to BF
By turning ON / OFF of 4, the keys S1 to S9, S0, S *,
Even if any two keys of S # are pressed at the same time, a large current does not flow into the output ports OUT01 to OUT04.

FIG. 2 is a timing chart of the key scan circuit. In the figure, key S2 and key S
Due to the double pressing of 5, the output lines L1 and L2 are short-circuited to each other during the periods (1) and (2), which are simultaneously pressed. During this period (1), the output line L1 of the output port OUT01 is at high level V _DD , and the output line L2 of the output port OUT02 is cut off by the buffer BF2 and has high impedance. Also, during the period of (2), the output port OUT
The output line L2 of 02 is high level V _DD , and the output line L1 of the output port OUT01 is cut off by the buffer BF1 and has high impedance. Therefore, in each of the periods (1) and (2), each output port OUT01, OU
There is no fear that a large current will flow into T02. As described above, when any one of the output ports OUT01 to OUT04 is at the high level, the output buffer is turned on, the output buffers of the other three outputs are turned off, and scanning is sequentially performed for each output. A key input is detected by the logic of signals IN01 to IN04.

FIG. 3 shows an example of a buffer circuit used in the key scan circuit of the present invention. As shown in the figure, this buffer circuit includes inverters, NANDs, NORs, P-
It is composed of an FET of ch, an FET of N-ch and the like. A pull-down resistor (PDR) of several tens of KΩ is attached to each input port side. OUP01 disable is O
This is an output line output from the CPU separately from UT01. Therefore, when the buffer is turned on, the OUTPUT
The data is output to L1.

FIG. 4 shows an example of a buffer circuit used in the key scan circuit of the present invention. As shown in the figure, this buffer circuit includes an inverter, a NAND, and a P-ch F
Consists of ET etc. A pull-down resistor (PDR) of several tens of KΩ is attached to each input port side. O
UP01 disable is CPU separately from OUT01
It is an output line that is output from. Therefore, when the buffer is turned on, the data is output to the OUTPUT L1.

FIG. 5 shows an example of a buffer circuit used in the key scan circuit of the present invention. As shown in the figure, this buffer circuit is composed of a P-ch FET and the like.
A pull-down resistor (PDR) of several tens of KΩ is attached to each input port side. When the buffer is turned on, data is output to OUTPUT L1. Although the above description is for positive logic output, similarly for negative logic output, the P-ch open drain output of the buffer circuit is N
It can be applied by replacing the -ch open drain output with a pull-up resistor instead of a pull-up resistor. It is also possible to apply a buffer circuit capable of turning on / off the C-MOS output by using a 3-state output.

[0014]

As described above, in the key scan circuit according to the present invention, an output buffer is provided between each output port and an output line, and each of these output buffers is turned on when high level output data is output. In this state, when high-level output data is not output, it is in the OFF state, and it can be switched sequentially according to the output data sequentially sent by scanning, so do not use a backflow prevention diode at the output port, The output collision at the time of double pressing of the key input can be prevented, which can greatly contribute to the simplification of the key circuit and the improvement of productivity.

[Brief description of drawings]

FIG. 1 is a key scan circuit diagram according to the present invention.

FIG. 2 is a timing chart of a key scan circuit according to the present invention.

FIG. 3 is a circuit diagram of a buffer used in the key scan circuit of the present invention.

FIG. 4 is a circuit diagram of a buffer used in the key scan circuit of the present invention.

FIG. 5 is a circuit diagram of a buffer used in the key scan circuit of the present invention.

FIG. 6 is a key scan circuit diagram according to a conventional example.

FIG. 7 is a timing chart of a key scan circuit according to a conventional example.

[Explanation of symbols]

 1 CPU section 2 Backflow prevention diode

Claims (2)

[Claims] 1. An output line from an output port for transmitting output data sequentially sent by scanning and an input line to an input port for inputting detection data for detecting a key press are wired in a matrix. In the key scan circuit in which a key is connected to the intersection, a pull-down resistor is added to each of the input ports and a P-ch open drain output is used for each of the output ports. 2. Each of the output buffers is in an ON state when high-level output data is output, is in an OFF state when high-level output data is not output, and is sequentially sent by scanning. 2. The key scan circuit according to claim 1, wherein the key scan circuit is sequentially switched according to incoming output data.