JPH06309880A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] An object is to obtain a sense circuit that can perform a sensing operation even when the power supply voltage drops. [Structure] N-channel transistors N11 and N12 are connected in series to a contact 7, a gate electrode of the N-channel transistor N11 is connected to a signal terminal 31 for giving a control signal, and a gate electrode of the N-channel transistor N12 is an original input. It is connected to the same signal terminal 4 as the N-channel transistor N1 which is a transistor. Further, N-channel transistors N13 and N14 are connected in series to the contact 8, the gate electrode of the N-channel transistor N13 is connected to the signal terminal 31, and the N-channel transistor N14 is the same as the N-channel transistor N2 which is the original input transistor. It is connected to the signal terminal 5. [Effect] Even if the power supply voltage drops, the sense operation can be normally performed by operating the N-channel transistor N11 or N13 by the control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit suitable for a memory circuit, and more particularly to a semiconductor integrated circuit suitable for a sense circuit of SRAM.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional SRAM sense circuit. In FIG. 2, P-channel transistors P1 and P3 having drain electrodes connected to the power supply potential terminal 1 are provided, and N-channel transistors N1 and N2 having drain electrodes connected to respective source electrodes of P-channel transistors P1 and P3. Is provided. The gate electrodes of the N-channel transistors N1 and N2 are connected to the signal terminals 4 and 5 from the memory cell, respectively.

The gate electrodes of the P-channel transistors P1 and P3 are connected to the drain electrode and the source electrode of the P-channel transistor P2, respectively, and the gate electrode of the P-channel transistor P2 is connected to the signal terminal 3 for supplying a control signal. Has been done.

A contact 7 is formed between the source electrode of the P-channel transistor P1 and the drain electrode of the N-channel transistor N1.
To the gate electrode of the P-channel transistor P3, and the source electrode of the P-channel transistor P3 and the drain electrode of the N-channel transistor N1 are commonly connected to the gate electrode of the P-channel transistor P1 from the contact 8. There is.

An inverter G1 is connected to the contact 8 and its output is connected to the output terminal 6.

FIG. 3 shows a memory cell circuit per bit. P-channel transistors P4 and P5 connected in parallel between the power supply potential terminal 1 and the signal terminals 4 and 5
Is provided, N-channel transistors N3 and N4 are connected in series between the source electrodes of the P-channel transistors P4 and P5, and inverters G2 and G3 are provided between the source and drain electrodes of the N-channel transistors N3 and N4.
Are connected in anti-parallel.

Further, P-channel transistors P4 and P5
Has a gate electrode connected to the signal terminal 9, and N-channel transistors N3 and N4 gate electrodes connected to the signal terminal 10.

Next, the operation will be described with reference to the circuit diagrams of FIGS. 2 and 3 and the timing chart of FIG. Before the start of sensing, the signal terminals 9 and 1 shown in FIG.
A low potential signal (hereinafter abbreviated as “L”) is applied to 0.
As a result, a high potential signal (hereinafter “H”) is applied to the signal terminals 4 and 5.
Is abbreviated). Moreover, "L" is given to the signal terminal 3 shown in FIG.

Here, P-channel transistors P1 and P
3 and the respective current conductances CP1, CP3, CN1, and CN2 of the N-channel transistors N1 and N2 are 2 to 3 at the values of the current conductance ratios CN1 / CP1 and CN2 / CP3.
P-channel transistors P1 and P3
By selecting the N-channel transistors N1 and N2, the contacts 7 and 8 become "L". But in this case
Since both the P-channel transistors P1 and P3 and the N-channel transistors N1 and N2 are conductive,
Since it becomes equivalent to resistance and the contacts 7 and 8 can be treated in the same manner as in the case of resistance division, the potentials of the contacts 7 and 8 are determined by the ratio of their respective conduction resistances, and are slightly higher than the ground potential.

When the sense is started, the control signal transits to the signal terminals 9, 10 and 3 by the read signal issued from the CPU (not shown) and the signal synchronized with the system clock. Is supplied with "H", and the potentials latched by the inverters G2 and G3 appear on the signal terminals 4 and 5. The signal given to the signal terminal 4 is “H”,
When the signal applied to the signal terminal 5 is "L", the N-channel transistor N2 becomes non-conductive, the potential of the contact 8 rises, and the P-channel transistor P1 accordingly.
Current conductance is reduced. Since the signal applied to the signal terminal 4 does not change before and after the start of sensing and remains “H” and constant, the current conductance of the N-channel transistor N1 is constant and only the conductance of the P-channel transistor P1 decreases. Then, when the N-channel transistor N1 and the P-channel transistor P1 are treated as equivalent to resistors, the potential of the contact 7 is determined by the ratio of the respective conduction resistances, and the potential of the contact 7 decreases, as in the case of resistance division. .

By this mechanism, the potential of the contact 7 finally becomes "L", the potential of the contact 8 becomes "H", and "L" is output to the output terminal 6.

The operation up to this point is shown by a solid line in FIG. 4 as a timing chart. FIG. 4 shows the signal input order from the top.

[0013]

Since the conventional sense circuit is constructed as described above, in order to increase the sense speed, the potentials of the contacts 7 and 8 at the start of sensing are slightly higher than the ground potential. P-channel transistors P1 and P3 and N-channel transistor N so that the value becomes high.
1 and N2 have a current conductance ratio of CN1 / C
Since the ratings are selected so that the values of P1 and CN2 / CP3 are about 2 to 3, the power supply voltage may decrease due to aging when a battery is used as the power supply. At this time, if the signal terminals 4 and 5 are "H", the conductance of the N-channel transistors N1 and N2 is lowered,
The potentials of the contacts 7 and 8 do not decrease in proportion to the power source potential. Therefore, the P-channel transistors P1 and P3
However, since the potentials of the contacts 7 and 8 are not "L", the sense operation becomes impossible.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a sense circuit capable of performing a sensing operation even when the power supply voltage is lowered.

[0015]

According to a first aspect of a semiconductor integrated circuit of the present invention, a first conductivity type first transistor and a second conductivity type second transistor which is an input transistor are connected in series. Connected to the first circuit, a third transistor of the first conductivity type, and a second transistor that is an input transistor.
A second transistor in which a conductive fourth transistor is connected in series
Circuit, the first and second circuits are connected in parallel between a first potential and a second potential, and one of the third transistors is connected to a control electrode of the first transistor. Of the first transistor to the control electrode of the third transistor.
The semiconductor integrated circuit in which one electrode of the transistor is cross-connected, further includes another input transistor connected in parallel to each of the second and fourth transistors.

According to a second aspect of the semiconductor integrated circuit of the present invention, first, second and third signal terminals for supplying the first and second input signals and the control signal, respectively, and the first conductivity type are provided. A first circuit in which a first transistor and a second conductive type second transistor whose control electrode is connected to the first signal terminal are connected in series, and a first conductive type third transistor A second circuit in which a fourth transistor of the second conductivity type having the second signal terminal connected to the control electrode is connected in series; and an output terminal for providing an output signal,
Between the first potential and the second potential, the first and second circuits are connected in parallel, and one electrode of the third transistor is connected to the third transistor as a control electrode of the first transistor. In a semiconductor integrated circuit in which one electrode of the first transistor is cross-connected to the control electrode of the transistor, a fifth transistor of the second conductivity type having the third signal terminal connected to the control electrode, and a control electrode Further comprising a circuit in which a sixth transistor of the second conductivity type connected to the first signal terminal is connected in series to the second transistor, and the control electrode is provided with the first transistor. A circuit in which a second conductivity type seventh transistor connected to the third signal terminal and a second conductivity type eighth transistor connected to the control electrode to the second signal terminal are connected in series; The fourth
It is further provided in parallel with the transistor.

[0017]

According to the first aspect of the semiconductor integrated circuit of the present invention, when the first potential is sufficiently high, the circuit configuration similar to the conventional one enables high speed operation. When the first potential drops, another input transistor connected in parallel with each of the second transistor and the fourth transistor, which are input transistors, is operated to operate the second transistor or the second transistor. Since the effective current conductance of the 4th transistor can be increased,
It becomes possible to operate.

According to the second aspect of the semiconductor integrated circuit of the present invention, when the first potential is sufficiently high, the fifth transistor and the seventh transistor are non-conductive to the third signal terminal. By applying a signal for turning off the signal, the circuit including the fifth transistor and the sixth transistor and the circuit including the seventh transistor and the eighth transistor are brought into a non-conducting state and high speed is achieved. It becomes possible to operate.

When the first potential drops, a signal for turning on the fifth transistor and the seventh transistor is applied to the third signal terminal, so that the fifth signal is supplied.
Of the second transistor or the fourth transistor is turned on when the circuit of the second transistor and the sixth transistor or the circuit of the seventh transistor and the eighth transistor becomes conductive. Since the conductance can be increased, the operation can be performed even when the first potential drops.

[0020]

1 shows a sense circuit of an SRAM which is an embodiment of a semiconductor integrated circuit according to the present invention. In FIG. 1, an N-channel transistor N11 (fifth transistor) and an N-channel transistor N12 are provided at the contact 7.
(Sixth transistor) is connected in series, the gate electrode of the N-channel transistor N11 is connected to the signal terminal 31 for giving a control signal, and the N-channel transistor N1 is connected.
The gate electrode of 2 is connected to the signal terminal 4. Also,
The contact 8 has an N-channel transistor N13 (seventh transistor) and an N-channel transistor N14 (eighth transistor).
Are connected in series, the gate electrode of the N-channel transistor N13 is connected to the signal terminal 31 for giving a control signal, and the gate electrode of the N-channel transistor N14 is connected to the signal terminal 5. Other configurations are similar to those of the conventional example described in FIG.

Next, the operation will be described. If the power supply voltage is sufficient, the mode control circuit (not shown) supplies the mode control signal "L" to the signal terminal 31 in the high speed mode in which the sensing speed is high, and the N channel transistor N
Since 11 and N13 are non-conducting, the same operation as the conventional sense circuit is performed.

When the power supply voltage drops, the mode control signal "H" is applied to the signal terminal 31 in the low voltage mode for operating at a low voltage, and the N-channel transistors N11 and N13 become conductive. , A series connection circuit of N-channel transistors N11 and N12, and a series connection circuit of N-channel transistors N13 and N14 operate to effectively enable N-channel transistor N1 (second transistor) and N-channel transistor N2 (fourth transistor). ) Is equivalent to the case where the conductance is increased.

As a result, N-channel transistors N11 and N12, and N-channel transistor N13.
By treating N14 and N14 as resistors, contacts 7 and 8
The potential of is determined by the ratio of the respective conduction resistances as in the case of resistance division.

FIG. 4 shows the potential changes of the contacts 7 and 8 by broken lines. As shown in FIG. 4, at the start of sensing, the potential is almost the ground potential level, which means that the potentials of the contacts 7 and 8 decrease in proportion to the power source potential. Therefore, the potentials of the contacts 7 and 8 are relatively “L” for the P-channel transistor P1 (first transistor) and the P-channel transistor P3 (third transistor), so that the sensing operation becomes possible. Sense is started and signal terminals 4 and 5
Becomes "H" and "L" respectively, the potential of the contact 8 becomes "H". At this time, the sense circuit includes P-channel transistor P3, N-channel transistors N2, N.
13 and N14, the operation of which is that the signal input to the signal terminal 5 is inverted and output to the contact 8 and is similar to the operation of the inverter circuit. The output of the output terminal 6 at this time becomes "L". When the signal terminals 4 and 5 are "L" and "H", respectively, the potential of the contact 7 is "H". At this time, the sense circuit includes P-channel transistor P1, N-channel transistors N1 and N.
11 and N12, and the operation is such that the signal input to the signal terminal 4 is inverted and output to the contact 7. The output of the output terminal 6 at this time becomes "H".

Therefore, even if the power supply voltage drops, the sensing operation can be normally performed by switching the operation mode.

Further, as described above, since the present embodiment is configured by simply adding a new input transistor in parallel to the input transistor of the conventional sense circuit, the circuit design can be easily changed.

The above-described embodiment of the sense circuit according to the present invention can be modified as follows.

That is, N-channel transistor N12 and N-channel transistor N14 shown in FIG. 1 may be formed of transistors having a low threshold voltage (V _Th ). A transistor having a low threshold voltage (V _Th ) has a higher current conductance even if the transistors have the same size. Therefore, an effective N-channel transistor N1 is used.
And the conductance of N2 will increase,
Since the potential of the contact 7 or the contact 8 becomes closer to the ground potential, the operation of the sense circuit becomes more reliable.

[0029]

According to the semiconductor integrated circuit of the first aspect, when the first potential is sufficiently high, the semiconductor integrated circuit operates at high speed similarly to the conventional circuit, and when the first potential drops, A circuit which operates at a low voltage can be obtained.

According to the semiconductor integrated circuit of claim 2,
If the first potential is sufficiently high, it operates at high speed as in the conventional circuit, and even if the first potential drops, a circuit that operates at a low voltage is added to the conventional circuit with a few transistors. Since it is easily obtained by doing so, there is an effect that the economic burden due to designing, manufacturing process changes, etc. accompanying the improvement is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a sense circuit which is an embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing a conventional sense circuit.

FIG. 3 is a circuit diagram showing the concept of a 1-bit memory cell.

FIG. 4 is a timing chart showing an operation of a sense circuit according to an embodiment and a conventional sense circuit.

[Explanation of symbols]

P1 P-channel transistor (first transistor) N1 N-channel transistor (second transistor) P3 P-channel transistor (third transistor) N2 N-channel transistor (fourth transistor) N11 N-channel transistor (fifth transistor) N12 N-channel transistor (sixth transistor) N13 N-channel transistor (seventh transistor) N14 N-channel transistor (eighth transistor) 1 Power supply potential terminal 2 Ground potential terminal 3 Control signal terminal 4, 5 Input terminal 6 Output terminal 31 Mode control signal terminal

Claims (2)

[Claims] 1. A first circuit in which a first-conductivity-type first transistor and a second-conductivity-type second transistor that is an input transistor are connected in series, and a first-conductivity-type third transistor A second circuit in which a transistor and a fourth transistor of the second conductivity type, which is an input transistor, are connected in series, and the first and second potentials are provided between the first potential and the second potential. Two circuits are connected in parallel, and one electrode of the third transistor is connected to the control electrode of the first transistor and the third electrode is connected to the control electrode of the first transistor.
Integrated circuit in which one electrode of the first transistor is cross-connected to the control electrode of the second transistor, further comprising another input transistor connected in parallel to each of the second and fourth transistors. circuit. 2. A first, second and third signal terminals for supplying first and second input signals and a control signal respectively, a first transistor of a first conductivity type, and a first electrode for the control electrode. A first circuit in which a second conductive type second transistor connected to the signal terminal of is connected in series, a first conductive type third transistor, and the control signal to the second signal terminal. A second circuit in which a connected fourth transistor of the second conductivity type is connected in series; and an output terminal for providing an output signal, wherein the second circuit is connected between the first potential and the second potential. First and second circuits are connected in parallel, and one electrode of the third transistor is connected to the control electrode of the first transistor as the third electrode.
In a semiconductor integrated circuit in which one electrode of the first transistor is cross-connected to the control electrode of the transistor, and a fifth transistor of the second conductivity type in which the third signal terminal is connected to the control electrode, A circuit in which a sixth transistor of the second conductivity type having an electrode connected to the first signal terminal is connected in series is further connected in parallel to the second transistor, and the control electrode is provided with the circuit. A circuit in which a seventh transistor of the second conductivity type connected to the third signal terminal and an eighth transistor of the second conductivity type connected to the control electrode to the second signal terminal are connected in series A semiconductor integrated circuit further connected to the fourth transistor in parallel.