JPH06310509A - Wiring structure of semiconductor integrated circuit - Google Patents
Wiring structure of semiconductor integrated circuitInfo
- Publication number
- JPH06310509A JPH06310509A JP9566693A JP9566693A JPH06310509A JP H06310509 A JPH06310509 A JP H06310509A JP 9566693 A JP9566693 A JP 9566693A JP 9566693 A JP9566693 A JP 9566693A JP H06310509 A JPH06310509 A JP H06310509A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- barrier layer
- wiring structure
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路（ＬＳ
Ｉ）の配線構造に関するものである。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (LS).
The present invention relates to the wiring structure I).
【０００２】[0002]
【従来の技術】現在、半導体集積回路の配線材料として
はＡｌあるいはＡｌとＳｉもしくはＣｕなどとの合金に
よるものが使用されている。このような配線において
は、Ａｌを主材料として用いるため、許容電流密度は
（２〜３）×１０5 Ａ／ｃｍ2 以下に制限されていた。
その理由は、これを越える電流を流した場合にはエレク
トロマイグレーションによって配線が断線してしまうた
めである。より多くの電流を流すためには、配線の材料
としてＡｌ中に０．１〜５％のＣｕを含む合金を用いる
ことがある。しかし、許容電流密度は改善されるものの
配線の比抵抗は増加し、発熱に伴う信頼性低下の問題が
生じる。2. Description of the Related Art At present, a wiring material for semiconductor integrated circuits is made of Al or an alloy of Al and Si or Cu. In such wiring, since Al is used as a main material, the allowable current density is limited to (2 to 3) × 10 5 A / cm 2 or less.
The reason is that when a current exceeding this is applied, the wiring is broken due to electromigration. In order to flow a larger amount of current, an alloy containing 0.1 to 5% Cu in Al may be used as the material of the wiring. However, although the allowable current density is improved, the specific resistance of the wiring is increased, which causes a problem of reliability deterioration due to heat generation.
【０００３】一方、Ａｌ配線に代わって、エレクトロマ
イグレーション耐性の高い配線材料として実質的にＣｕ
を用いることが提案されている。ところが、Ｃｕ膜はＡ
ｌと比べてＳｉ又はＳｉＯ2 中に拡散しやすく、そのた
めトランジスタの正常な動作を妨げるという問題が生じ
る。これまで各種のバリア材料を用いたＣｕの拡散防止
層としての応用が提案（特開昭６３−１５６３４１号公
報、特開平１−２０２８４１号公報など）されてきた。
しかし、これらの技術によってＣｕの拡散を完全に抑制
することは困難である。On the other hand, in place of Al wiring, Cu is substantially used as a wiring material having high electromigration resistance.
Is proposed to be used. However, the Cu film is A
Compared with l, it is more likely to diffuse into Si or SiO 2 , which causes a problem that the normal operation of the transistor is hindered. Up to now, application of Cu as a diffusion preventing layer using various barrier materials has been proposed (Japanese Patent Laid-Open No. 63-156341, Japanese Patent Laid-Open No. 1-202841 and the like).
However, it is difficult to completely suppress the diffusion of Cu by these techniques.
【０００４】[0004]
【発明が解決しようとする課題】したがって、バリア層
を通過したＣｕを効果的に捕獲し、僅かに拡散したＣｕ
を捕獲する配線構造が必要となる。すなわち、周囲のＳ
ｉＯ2 又はＳｉ中へのＣｕの拡散を完全に防止すること
ができる配線構造の開発が急務である。Therefore, Cu that has passed through the barrier layer is effectively trapped and slightly diffused.
A wiring structure that captures That is, the surrounding S
There is an urgent need to develop a wiring structure capable of completely preventing diffusion of Cu into iO 2 or Si.
【０００５】[0005]
【課題を解決するための手段】本発明は前記問題点を解
決するために、Ｃｕ配線の下地又は周囲にＣｕと固溶し
ないバリア層を設け、このバリア層の下地又は周囲にＣ
ｕと完全に固溶するトラップ層を設けたことを特徴とす
るＣｕ配線構造体を提案するものである。In order to solve the above-mentioned problems, the present invention provides a barrier layer which does not form a solid solution with Cu under or around Cu wiring, and a C layer under or around this barrier layer.
The present invention proposes a Cu wiring structure characterized in that a trap layer that completely forms a solid solution with u is provided.
【０００６】[0006]
【作用】Ｃｕに接触するバリア層はＣｕの拡散防止効果
に優れ、かつＣｕの抵抗を上昇させないことが必要であ
る。Ｔａ、Ｗ又はＴａ−Ｗ合金は、Ｃｕと固溶しないた
め熱処理に対しても、Ｃｕの比抵抗を上昇させることは
なく、また、Ｎｂ，Ｍｏ，Ｃｒ，Ｔｉ等の他の遷移金属
に比べて自己拡散係数が小さいためにＣｕの拡散防止材
料として有効である。It is necessary that the barrier layer in contact with Cu has an excellent Cu diffusion preventing effect and does not increase the resistance of Cu. Since Ta, W, or Ta-W alloy does not form a solid solution with Cu, it does not increase the specific resistance of Cu even with heat treatment, and compared with other transition metals such as Nb, Mo, Cr, and Ti. Since it has a small self-diffusion coefficient, it is effective as a Cu diffusion preventing material.
【０００７】バリア層に接触するトラップ層はバリア層
を通過したＣｕを捕獲するものである。Ｂｉ，Ｇａ，Ｍ
ｇ，Ｍｎ等はＣｕと完全に固溶するのでこれらによって
トラップ層を設けると、バリア層を通過したＣｕと固溶
体を形成してトラップ層内にＣｕを捕獲する。バリア層
とトラップ層とを有する本発明の配線構造と、バリア層
とトラップ層とを合わせた膜厚と同じ膜厚を持つバリア
層のみを有する従来の配線構造とで、周囲に拡散するＣ
ｕ量を比較すると本発明による前者の構造では優れた拡
散防止効果が見られる。The trap layer in contact with the barrier layer captures Cu that has passed through the barrier layer. Bi, Ga, M
Since g, Mn, and the like are completely solid-dissolved with Cu, when a trap layer is provided by these, Cu and the Cu that have passed through the barrier layer form a solid solution and capture Cu in the trap layer. The wiring structure of the present invention having the barrier layer and the trap layer and the conventional wiring structure having only the barrier layer having the same thickness as the total thickness of the barrier layer and the trap layer are diffused to the surrounding C.
Comparing the amounts of u, the former structure according to the present invention exhibits an excellent diffusion preventing effect.
【０００８】[0008]
【実施例】以下に実施例をあげて詳細な説明を行う。表
１は、各種バリア材料のＣｕに対するバリア性評価を目
的としてＣｕ／Ｍ1／Ｍ2 ／Ｓｉ（Ｍ1 ＝バリア層、Ｍ2
＝トラップ層）の積層膜を拡散熱処理した後に、ＳＩ
ＭＳによりＳｉ表面のＣｕ濃度を示したものである。こ
れらの多層膜は、Ｓｉ基板上にバリア層膜をＲＦマグネ
トロンスパッタリングによって９００Å堆積させ、さら
にＣｕをＲＦマグネトロンスパッタリングによって１０
０００Å積層したものである。熱処理は多層膜をＨ2 中
で７００℃×３ｈ実施した。[Examples] A detailed description will be given below with reference to Examples. Table 1 shows Cu / M 1 / M 2 / Si (M 1 = barrier layer, M 2 for the purpose of evaluating barrier properties against Cu of various barrier materials).
(= Trap layer) is subjected to diffusion heat treatment, and then SI
It shows the Cu concentration on the Si surface by MS. For these multilayer films, a barrier layer film was deposited on the Si substrate by RF magnetron sputtering to 900 Å, and Cu was further deposited by RF magnetron sputtering to 10 Å.
It is a stack of 000Å. The heat treatment was performed on the multilayer film in H 2 at 700 ° C. for 3 hours.
【０００９】バリア材料をこれまで提案されているＴａ
又はＺｒ単相とした場合に比べて、Ｔａ又はＷとＭｇ又
はＭｎのトラップ材との積層構造とした場合には、バリ
ア層の周囲すなわちＳｉ基板表面に存在するＣｕ濃度が
減少していることが分かる。これは、後者ではバリア層
を通過したＣｕ元素がＭｇ又はＭｎに固溶してＳｉ基板
への拡散が効果的に抑制されているものと考えられる。
この時、バリア層であるＴａ又はＷはＣｕと固溶しない
ために、試料のシート抵抗の上昇は観察されなかった。Barium materials have been proposed so far for Ta.
Or, compared with the case where the Zr single phase is used, when the laminated structure of Ta or W and the trap material of Mg or Mn is used, the Cu concentration existing around the barrier layer, that is, on the surface of the Si substrate is decreased. I understand. This is considered to be because, in the latter case, the Cu element that has passed through the barrier layer forms a solid solution with Mg or Mn and the diffusion into the Si substrate is effectively suppressed.
At this time, since Ta or W, which is the barrier layer, did not form a solid solution with Cu, no increase in the sheet resistance of the sample was observed.
【００１０】図１は、本発明によるＣｕ配線構造の断面
図を示したものである。図１（ａ）のように、Ｓｉ基板
１の表面に５０００ÅのＢＳＰＧの絶縁膜２を設け、そ
の表面にＣｕ膜の下地として、ＢＰＳＧ上の全面にＭｎ
膜３を全圧２ｍＴｏｒｒのＡｒ雰囲気中でＲＦマグネト
ロンスパッタリングによって成膜速度５Å／ｓで２００
Å成長させる。さらにＷ膜４を全圧２ｍＴｏｒｒのＡｒ
雰囲気中でＲＦマグネトロンスパッタリングによって成
膜速度１０Å／ｓで４００Å成長させる。その表面にＣ
ｕを全圧２ｍＴｏｒｒの、Ａｒ雰囲気中でＲＦマグネト
ロンスパッタリングによって成膜速度６０Å／ｓで５０
００Å成長させて、図１（ｂ）のように、これをパター
ニングしてＣｕ配線５を形成する。さらに図１（ｃ）の
ように、ＷをＣＶＤ法によってＣｕ配線５及び下地膜の
周囲のみに選択的に４００Å成長させてＷ被覆膜６を形
成する。この時のＷ成膜条件は試料温度を２００〜４０
０℃としＷＦ6 とＨ2 を混合して成膜室へ供給し、この
時のガス圧を１Ｔｏｒｒ以下とすることによって界面反
応が律速となり、Ｃｕ及び下地のバリア材料合金膜側面
のみに選択成長させることが可能となる。さらに、この
配線構造を多層化する場合には、Ｗ被覆膜６上にＳｉＯ
2 等の絶縁膜を設けて、その上にＭｎ膜３、Ｗ膜４、Ｃ
ｕ配線５、Ｗ被覆膜６からなる配線構造を同様に作製す
ればよい。FIG. 1 is a sectional view of a Cu wiring structure according to the present invention. As shown in FIG. 1A, a 5000 Å insulating film 2 of BSPG is provided on the surface of a Si substrate 1, and a Mn film is formed on the entire surface of BPSG as a base of a Cu film on the surface.
The film 3 was formed by RF magnetron sputtering in an Ar atmosphere at a total pressure of 2 mTorr at a film forming rate of 5 Å / s to 200.
Å Grow. In addition, the W film 4 is Ar at a total pressure of 2 mTorr.
400 Å is grown at a film forming rate of 10 Å / s by RF magnetron sputtering in an atmosphere. C on the surface
u at a total pressure of 2 mTorr by RF magnetron sputtering in an Ar atmosphere at a deposition rate of 60 Å / s for 50
00Å is grown, and as shown in FIG. 1B, this is patterned to form Cu wiring 5. Further, as shown in FIG. 1C, W is selectively grown only around the Cu wiring 5 and the base film by the CVD method to form a W coating film 6 by 400 Å. At this time, the W film forming condition is that the sample temperature is 200 to 40.
The temperature is set to 0 ° C., WF 6 and H 2 are mixed and supplied to the film forming chamber, and the gas pressure at this time is set to 1 Torr or less, the interfacial reaction becomes rate-determining, and selective growth occurs only on the side surface of the Cu and underlying barrier material alloy film. It becomes possible. Further, when the wiring structure is to be multilayered, SiO is formed on the W coating film 6.
An insulating film such as 2 is provided, and the Mn film 3, W film 4, C
A wiring structure including the u wiring 5 and the W coating film 6 may be similarly produced.
【００１１】[0011]
【表１】 [Table 1]
【００１２】[0012]
【発明の効果】このように、微細な半導体集積回路の配
線構造におけるＣｕ配線に対して、Ｔａ又はＷ等のバリ
ア層及びＭｇ又はＭｎ等のトラップ層を設けることによ
り、Ｃｕの拡散を抑制可能な半導体のＣｕ配線構造を実
現することができた。したがって、比抵抗がＡｌ合金よ
り小さく、耐エレクトロマイグレーションに優れた本Ｃ
ｕ配線の工業的意義は非常に大きい。As described above, the diffusion of Cu can be suppressed by providing the barrier layer such as Ta or W and the trap layer such as Mg or Mn for the Cu wiring in the wiring structure of the fine semiconductor integrated circuit. It was possible to realize a Cu wiring structure of a different semiconductor. Therefore, this C which has a smaller specific resistance than the Al alloy and is excellent in electromigration resistance.
The industrial significance of u wiring is very great.
【図１】本発明のＣｕ配線構造の断面図である。FIG. 1 is a cross-sectional view of a Cu wiring structure of the present invention.
１ Ｓｉ基板 ２ 絶縁膜 ３ Ｍｎ膜 ４ Ｗ膜 ５ Ｃｕ配線 ６ Ｗ被覆層 1 Si substrate 2 Insulating film 3 Mn film 4 W film 5 Cu wiring 6 W coating layer
Claims (2)
てＣｕを用い、その配線の下地又は周囲にバリア層を設
け、バリア層の下地又は周囲にトラップ層を設けたこと
を特徴とする半導体集積回路の配線構造。1. A semiconductor integrated circuit characterized in that Cu is used as a wiring material in a wiring portion of a semiconductor integrated circuit, a barrier layer is provided under or around the wiring, and a trap layer is provided under or around the barrier layer. Circuit wiring structure.
し、トラップ層をＣｕと完全に固溶する金属としたこと
を特徴とする請求項１記載の半導体集積回路の配線構
造。2. The wiring structure of a semiconductor integrated circuit according to claim 1, wherein the barrier layer is made of Ta, W or a Ta—W alloy, and the trap layer is made of a metal which is completely solid-dissolved with Cu.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9566693A JPH06310509A (en) | 1993-04-22 | 1993-04-22 | Wiring structure of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9566693A JPH06310509A (en) | 1993-04-22 | 1993-04-22 | Wiring structure of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06310509A true JPH06310509A (en) | 1994-11-04 |
Family
ID=14143824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9566693A Withdrawn JPH06310509A (en) | 1993-04-22 | 1993-04-22 | Wiring structure of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06310509A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000011721A1 (en) * | 1998-08-20 | 2000-03-02 | The Government Of The United States Of America, Represented By The Secretary Of The Navy | Electronic devices with barrier film and process for making same |
| KR100290491B1 (en) * | 1997-03-18 | 2001-08-07 | 다니구찌 이찌로오, 기타오카 다카시 | CVD Apparatus for Cu Formation |
| US6339258B1 (en) | 1999-07-02 | 2002-01-15 | International Business Machines Corporation | Low resistivity tantalum |
| US6351036B1 (en) | 1998-08-20 | 2002-02-26 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with a barrier film and process for making same |
| US6465887B1 (en) | 2000-05-03 | 2002-10-15 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with diffusion barrier and process for making same |
| WO2007100125A1 (en) * | 2006-02-28 | 2007-09-07 | Advanced Interconnect Materials, Llc | Semiconductor device, its manufacturing method, and sputtering target material for use in the method |
| US7755192B2 (en) | 2008-03-25 | 2010-07-13 | Tohoku University | Copper interconnection structure, barrier layer including carbon and hydrogen |
| US8169079B2 (en) | 2008-12-19 | 2012-05-01 | Advanced Interconnect Materials, Llc | Copper interconnection structures and semiconductor devices |
| US8372745B2 (en) | 2006-02-28 | 2013-02-12 | Advanced Interconnect Materials, Llc | Semiconductor device, its manufacturing method, and sputtering target material for use in the method |
-
1993
- 1993-04-22 JP JP9566693A patent/JPH06310509A/en not_active Withdrawn
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100290491B1 (en) * | 1997-03-18 | 2001-08-07 | 다니구찌 이찌로오, 기타오카 다카시 | CVD Apparatus for Cu Formation |
| WO2000011721A1 (en) * | 1998-08-20 | 2000-03-02 | The Government Of The United States Of America, Represented By The Secretary Of The Navy | Electronic devices with barrier film and process for making same |
| US6351036B1 (en) | 1998-08-20 | 2002-02-26 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with a barrier film and process for making same |
| US6339258B1 (en) | 1999-07-02 | 2002-01-15 | International Business Machines Corporation | Low resistivity tantalum |
| US6465887B1 (en) | 2000-05-03 | 2002-10-15 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with diffusion barrier and process for making same |
| US6881669B2 (en) | 2000-05-03 | 2005-04-19 | The United States Of America As Represented By The Secretary Of The Navy | Process for making electronic devices having a monolayer diffusion barrier |
| WO2007100125A1 (en) * | 2006-02-28 | 2007-09-07 | Advanced Interconnect Materials, Llc | Semiconductor device, its manufacturing method, and sputtering target material for use in the method |
| US8188599B2 (en) | 2006-02-28 | 2012-05-29 | Advanced Interconnect Materials, Llc | Semiconductor device, its manufacturing method, and sputtering target material for use in the method |
| US8372745B2 (en) | 2006-02-28 | 2013-02-12 | Advanced Interconnect Materials, Llc | Semiconductor device, its manufacturing method, and sputtering target material for use in the method |
| US7755192B2 (en) | 2008-03-25 | 2010-07-13 | Tohoku University | Copper interconnection structure, barrier layer including carbon and hydrogen |
| US8163649B2 (en) | 2008-03-25 | 2012-04-24 | Advanced Interconnect Materials, Llc | Copper interconnection structure, semiconductor device, and method for forming copper interconnection structure |
| US8169079B2 (en) | 2008-12-19 | 2012-05-01 | Advanced Interconnect Materials, Llc | Copper interconnection structures and semiconductor devices |
| US9082821B2 (en) | 2008-12-19 | 2015-07-14 | Advanced Interconnect Materials, Llc | Method for forming copper interconnection structures |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000704 |