JPH06311111A - Input signal cut detection device - Google Patents

Abstract

(57) [Abstract] [Purpose] An input signal disconnection detection device for detecting that input of a pulsed periodic signal is interrupted is intended to prevent malfunction due to circuit noise. According to a difference between an input signal and an output signal from the delay unit 1, a detecting unit 2 detects that a periodic signal is not input. That is, focusing on the fact that there is a difference between two input signals whose phases are shifted depending on the presence or absence of the periodicity of the input signal, it is detected that no periodic signal is input. The clock pulse extracted from the received signal is supplied as the input signal here, and the fact that the clock pulse is not input corresponds to the fact that the received signal is not received. Since the circuit noise has no periodicity, the circuit noise is not mistaken for a clock pulse as in the conventional case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal disconnection detecting device for detecting interruption of input of a pulsed periodic signal, and more particularly to an input signal disconnection used in a repeater or receiver for optical digital communication. Regarding a detection device.

[0002] In an optical digital communication system, an alarm is generated when a transmission signal is not received due to some trouble, and based on this alarm, a measure such as switching to a protection line is taken. . Hereinafter, such a state in which the transmission signal is not received is referred to as “input signal disconnection”.

[0003]

2. Description of the Related Art FIG. 6 is a block diagram showing a part of a receiver for optical digital communication equipped with a conventional input signal loss detecting device. That is, the receiver for optical digital communication includes an equalization amplification unit 100 that converts an optical signal into an electric signal and amplifies it, an identification / reproduction unit 200 that shapes the waveform of a signal pulse, a retiming unit 300 that generates a clock pulse, The signal loss detection unit 400 and the like for detecting the loss of the input signal. The equalization amplification unit 100 includes a light receiving element 101 that converts an optical pulse signal into an electric signal, and a preamplification circuit 102 that amplifies the electric signal.
And an equalization amplifier circuit 103 including an AGC circuit for making the amplitude of the electric signal a constant value. The discriminating / reproducing unit 200 is a discriminating circuit 201 which is composed of a flip-flop and which shapes the signal pulse from the equalizing / amplifying circuit 103 based on a clock pulse supplied from a limiter / amplifying circuit 303 described later. The identification circuit 201 outputs a waveform-shaped signal, that is, data, and also outputs a clock pulse from the limiter amplifier circuit 303.

On the other hand, the retiming unit 300 uses the output signal from the equalization amplifier circuit 103 to extract a clock signal contained therein, and a non-linear extraction circuit 301, and the same frequency as the frequency of this clock signal. A SAW (surface acoustic wave) filter 302 that passes only a signal having a noise and a limiter amplifier circuit 303 that amplifies the output of the SAW filter 302 and keeps the amplitude constant. As a result, the limiter amplifier circuit 303 outputs a clock pulse in synchronization with the input optical pulse signal, which is supplied to the identification circuit 201 as described above and to the signal disconnection detection unit 400.

The signal loss detection section 400 includes a peak detection circuit 401 for detecting the peak value of an input clock pulse,
The operational amplifier 402 is configured to compare the peak value with a predetermined reference level and output an input signal disconnection detection signal when the peak value is smaller than the predetermined reference level. Therefore, when the optical pulse signal is not input, the input signal disconnection detection signal is output, which causes, for example, an alarm (not shown).

[0006]

However, in the above-mentioned device, even when the optical pulse signal is no longer input and the signal disconnection detection signal should be output, the input signal disconnection detection signal is naturally affected by noise. Sometimes it was not output.
That is, of the circuit noise generated from the light receiving element 101, the preamplification circuit 102, the equalization amplification circuit 103, and the nonlinear extraction circuit 301, the component that passes through the SAW filter 302 and the circuit noise of the limiter amplification circuit 303 are The signal disconnection detection unit 400 may have a level higher than a predetermined reference level. Therefore, there is a problem in that an input signal disconnection detection signal is not output although the optical pulse signal is not input. .

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an input signal disconnection detecting device which prevents malfunction due to circuit noise.

[0008]

FIG. 1 is a diagram for explaining the principle of the present invention which achieves the above object. The first invention is
As shown in (A), delay means 1 for delaying an input signal
And a detection means 2 for detecting that no periodic signal is input based on the difference between the input signal and the output signal from the delay means 1.

Further, the detecting means 2 has a difference detecting means 2a for detecting the difference, an averaging means 2b for averaging the outputs of the difference detecting means 2a, and an output level of the averaging means 2b for a predetermined reference level. Comparing means 2c for comparing

A second invention is, as shown in (B), a first delay means 3 for delaying an input signal by (n + 1/4) cycles, and an input signal and an output signal from the first delay means 3. To the D terminal and the clock terminal, respectively, a first averaging means 5 for averaging the outputs of the D-flip flop 4, and a first averaging means 5
From the first comparison means 6 for comparing the output level of the input signal with the first reference level, the second delay means 7 for delaying the input signal by (m + 1/2) cycles, and the input signal and the second delay means 7. An exclusive OR circuit 8 for inputting the output signal of the input signal, and a second averaging means 9 for averaging the output of the exclusive OR circuit 8.
Second comparing means 10 for comparing the output level of the second averaging means 9 with a second reference level, and a NAND circuit 11 for inputting each output of the first comparing means 6 and the second comparing means 10. Have.

[0011]

With the above configuration, in the first invention shown in FIG. 1 (A), the detection means 2 receives the periodic signal based on the difference between the input signal and the output signal from the delay means 1. Detect that there is no. That is, focusing on the fact that there is a difference between two input signals whose phases are shifted depending on the presence or absence of the periodicity of the input signal, it is detected that no periodic signal is input. The clock pulse extracted from the received signal is supplied as the input signal here, and the fact that the clock pulse is not input corresponds to the fact that the received signal is not received. Since circuit noise has no periodicity,
Circuit noise is no longer mistaken for a clock pulse as in the past.

A second aspect of the invention shown in FIG. 1B is a more specific form of the first aspect of the invention, and enables a more reliable signal disconnection detection operation than the first aspect of the invention.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the input signal loss detection device. This input signal loss detection device is arranged in the same position as the position where the signal loss detection unit 400 of FIG. 6 is arranged in the receiver for optical digital communication. Therefore, in FIG. 2, the same components as those shown in FIG. 6 are designated by the same reference numerals, and the description thereof will be omitted.

The delay circuit 21 is a limiter amplifier circuit 303.
The clock pulse of the period Ts output from (n + 1 /
4) A delay circuit that delays by a period. n is an integer. The output of the delay circuit 21 is a clock input terminal C of a D-flip-flop (hereinafter referred to as "D-FF") 22.
Is input to. The clock pulse output from the limiter amplifier circuit 303 is input to the D input terminal of the D-FF 22. Therefore, from the output terminal Q of the D-FF 22,
The output value of the limiter amplifier circuit 303 at the moment when the output of the delay circuit 21 rises is always output.

The output of the D-FF 22 is averaged by a low pass filter (hereinafter referred to as "LPF") 23 and then input to a non-inverting input terminal (+) of an operational amplifier 24 which operates as a comparator. The inverting input terminal (−) of the operational amplifier 24 is supplied with a first reference voltage of −1.1V, for example. The first reference voltage is set to a voltage slightly lower than the level of a predetermined high level signal that is normally input to the non-inverting input terminal of the operational amplifier 24.

On the other hand, the delay circuit 25 outputs the clock pulse of the cycle Ts output from the limiter amplifier circuit 303 to (m
This is a delay circuit that delays by +1/2) cycle. m is an integer. The output of the delay circuit 25 is input to one input terminal of an exclusive OR circuit (hereinafter referred to as “EX-OR”) 26. The clock pulse output from the limiter amplifier circuit 303 is input to the other input terminal of the EX-OR 26. Therefore, the output of the EX-OR 26 becomes high level when only one of the output of the delay circuit 25 and the output of the limiter amplifier circuit 303 is at high level.

The output of the EX-OR 26 is averaged by a low pass filter (hereinafter referred to as "LPF") 27, and then,
It is input to the non-inverting input terminal (+) of the operational amplifier 28 that operates as a comparator. The inverting input terminal (-) of the operational amplifier 28 is supplied with a second reference voltage having a value lower than the first reference voltage supplied to the inverting input terminal of the operational amplifier 24, for example, -1.5V. The second reference voltage is set to a voltage slightly higher than the level of a predetermined low level signal that is normally input to the non-inverting input terminal of the operational amplifier 28.

The outputs of the operational amplifier 24 and the operational amplifier 28 are input to the NAND circuit 29, and the NAND circuit 2
An input signal disconnection detection signal is output from 9. The operation of the input signal loss detection device configured as described above will be described below with reference to FIGS.
This will be described with reference to FIG.

First, FIG. 3 is a timing chart of signals of respective parts of the input signal disconnection detecting device in a state where the clock pulse is normally input to the input signal disconnection detecting device. As shown in (A), the limiter amplifier circuit 303 outputs a clock pulse having a cycle Ts. (B) is the output of the delay circuit 21 that delays this clock pulse by (n + 1/4) cycles, and (C) is the output of the delay circuit 25 that delays this clock pulse by (m + 1/2) cycles. is there.

From the signal shown in (A) and the signal shown in (B), the output of the D-FF 22 becomes as shown in (D). That is, the signal level of (A) at the time of rising of the signal shown in (B) is output from the D-FF 22, and in this case, as shown in (D), all are high level signals.

From the signal shown in (A) and the signal shown in (C), the output of the EX-OR 26 becomes as shown in (E). That is, in this case, since the signal shown in (A) and the signal shown in (C) have opposite phases, all the outputs of the EX-OR 26 are high level signals. However, if the bit rate of the clock pulse output from the limiter amplifier circuit 303 becomes high, the EX-O may be delayed due to rounding of the pulse waveform.
It is possible that a temporary low-level portion (hereinafter, referred to as “beard”) is generated in the output of R26. This beard occurs when the signal shown in (A) and the signal shown in (C) change their amplitudes, as indicated by the broken line in (E).

The signal shown in (D) reaches the operational amplifier 24 without changing even when passing through the LPF 23. This operational amplifier 2
Since the level of the signal reaching 4 is larger than the first reference voltage of the operational amplifier 24 −1.1V, the output of the operational amplifier 24 becomes a high level as shown in (F). On the other hand, the signal shown in (E) is passed through the LPF 27 to be averaged even if a whisker is generated, and the signal is slightly lower than a predetermined high level, but becomes a sufficiently high level. There is. Therefore, the output of this LPF 27 is the operational amplifier 2
8 is sufficiently higher than the second reference voltage of -1.5V, and the output of the operational amplifier 28 becomes a high level as shown in (G).

Output of operational amplifier 24 and operational amplifier 2
Since the outputs of 8 are all at the high level, the output of the NAND circuit 29 is at the low level as shown in (H). The low level output of the NAND circuit 29 means that the input signal disconnection is not detected. That is, since the received signal of the optical pulse is received, the periodic clock pulse extracted from the received signal is supplied to the input signal loss detection device of the present embodiment, so that the output of the NAND circuit 29 is low. It becomes a level. That is, the low level output of the NAND circuit 29 indicates that the received signal of the optical pulse is being received.

Next, FIG. 4 is a timing chart of the signals of the respective parts of the input signal loss detection device in the state where the clock pulse is not input to the input signal loss detection device and the pulse based on the circuit noise is input. Is.

In this case, the limiter amplifier circuit 303 outputs a pulse having no periodicity due to circuit noise as shown in FIG. (B) sends this pulse to (n + 1 /
4) The output of the delay circuit 21 delayed by the period,
(C) is the output of the delay circuit 25 which delays this clock pulse by (m + 1/2) cycles.

From the signal shown in (A) and the signal shown in (B), the output of the D-FF 22 becomes as shown in (D). That is, when the signal shown in (B) rises, the level of the signal shown in (A) may be high or low, and when the signal shown in (A) falls when the signal shown in (B) rises, The output of the D-FF 22 is unclear as to which level is high or low. Therefore, when a pulse having no periodicity is input, the output level of the D-FF 22 is mixed with high and low.

From the signal shown in (A) and the signal shown in (C), the output of the EX-OR 26 becomes as shown in (E). That is, in this case, the signal shown in (A) and the signal shown in (C) do not necessarily have opposite phases, so EX-O
The output level of R26 is high and low.

The signal shown in (D) passes through the LPF 23 and is averaged to obtain the first reference voltage -1.1 of the operational amplifier 24.
V, that is, the voltage set to a level slightly lower than the level of a predetermined high level signal that is normally input to the non-inverting input terminal of the operational amplifier 24, becomes lower, so that the output of the operational amplifier 24 becomes low as in (F). Become a level. On the other hand, the signal shown in (E) passes through the LPF 27 and is averaged to obtain a second reference voltage of -1.5 V of the operational amplifier 28, that is, a predetermined low-level signal that is normally input to the non-inverting input terminal of the operational amplifier 28. Since the voltage set to a level slightly higher than the level becomes higher, the output of the operational amplifier 28 becomes as shown in (G).
High level.

The output of the operational amplifier 24 is low level,
Since the output of the operational amplifier 28 is high level, NAND
The output of the circuit 29 becomes high level as shown in (H).
The high level output of the NAND circuit 29 means that the input signal disconnection is detected. That is, the NAND circuit 29
The high level output of is because the periodic clock pulse is not input to the input signal loss detection device.The reason why the clock pulse is not input is that the optical pulse reception signal is received by the optical digital communication receiver. Because not.

As described above, even when the clock pulse is not input and the pulse based on the circuit noise is input,
The input signal disconnection can be accurately detected. Note that FIG.
There is a clear difference between the signal shown in (D) and the signal shown in (D) of FIG. 4, and similarly the signal shown in (E) of FIG. 3 and the signal shown in (E) of FIG. 3F and the signal shown in FIG. 4F, the output signal level of the LPF 27 at the normal time and the LPF 27 at the time of the signal interruption.
There is also a clear difference with the output signal level of each. Therefore, the input signal disconnection may be detected based on such a difference. However, in this case, it is not possible to detect the signal loss as accurately as in the above embodiment.

FIG. 5 shows the output signal levels of the operational amplifier 24, the operational amplifier 28, and the NAND circuit 29, which change depending on the input state of the clock pulse or circuit noise to the input signal disconnection detecting device and the state of occurrence of the beard. It is a figure displayed for each such state. In the figure, H indicates a high level and L indicates a low level. The contents of columns 51 and 52 have already been explained with reference to FIG. 3, and the contents of column 54 have already been explained with reference to FIG.

The content of the column 53 shows the case where no clock pulse is input to the input signal disconnection detecting device and no pulse based on circuit noise is input. In this case, the outputs of the limiter amplifier circuit 303, the delay circuit 21, and the delay circuit 25 are all at a low level, so it is unclear whether the output of the D-FF 22 is at a high level or a low level. Yes, but keep one or the other. On the other hand, the output of the EX-OR 26 becomes low level. Therefore,
Although it is unclear whether the output of the operational amplifier 24 is high or low, the output of the operational amplifier 28 is low. As a result, the output of the NAND circuit 29 becomes high level, and the disconnection of the input signal is detected.

In the above embodiment, the case where the input signal loss detecting device is applied to the receiver for optical digital communication has been described.
The input signal disconnection detection device of the present invention can also be applied to other devices that need to perform periodic pulse input disconnection detection.

In the above embodiment, the delay circuit 21 delays by (n + 1/4) cycles and the delay circuit 25 delays by (m
It was explained that the delay is +1/2) cycle,
The delay amount is not limited to this.

[0035]

As described above, in the present invention, the input signal disconnection of the periodic signal is detected based on the difference between the input signal and the delayed input signal. This allows
It is possible to prevent malfunction of the input signal loss detection device due to circuit noise. Further, even if a whisker is generated due to the input of the signal of the high bit rate, the malfunction can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a configuration of an input signal loss detection device.

FIG. 3 is a timing chart of signals of respective parts of the input signal loss detection device in a state where a clock pulse is normally input to the input signal loss detection device.

FIG. 4 is a timing chart of signals of respective parts of the input signal loss detection device in a state where a clock pulse is not input to the input signal loss detection device and a pulse based on circuit noise is input.

FIG. 5 is a diagram showing a change in level of output signals of an operational amplifier and a NAND circuit that are output according to an input state of a clock pulse or circuit noise to the input signal loss detection device, and a beard generation state.

FIG. 6 is a block diagram showing a part of a receiver for optical digital communication provided with a conventional input signal loss detection device.

[Explanation of symbols]

 1 delay means 2 detection means 2a difference detection means 2b averaging means 2c comparing means 3 first delaying means 4 D-flip-flop 5 first averaging means 6 first comparing means 7 second delaying means 8 exclusive OR circuit 9 Second averaging means 10 Second comparing means 11 NAND circuit

Claims (8)

[Claims] 1. An input signal loss detection device for detecting the interruption of the input of a pulsed periodic signal, comprising: delay means (1) for delaying the input signal; and the input signal and the delay means (1). An input signal disconnection detection device comprising: a detection unit (2) that detects that a periodic signal is not input based on a difference between the output signal and the output signal. 2. The detecting means (2) includes a difference detecting means (2a) for detecting the difference, an averaging means (2b) for averaging the outputs of the difference detecting means (2a), and the averaging means. 2. The input signal loss detection device according to claim 1, further comprising a comparison means (2c) for comparing the output level of the means (2b) with a predetermined reference level. 3. The delay means (1) receives an input signal (n
2. The input signal loss detection device according to claim 1, wherein the input signal loss detection device is configured to delay by +1/4) period. 4. The detection means (2) has a D-flip-flop for inputting the input signal and the output signal from the delay means (1) to a D terminal and a clock terminal. 3. The input signal loss detection device according to item 3. 5. The delay means (1) receives an input signal (m).
The input signal loss detection device according to claim 1, wherein the input signal loss detection device is configured to be delayed by +1/2) cycles. 6. The input signal disconnection according to claim 5, wherein the detection means (2) has an exclusive OR circuit for inputting the input signal and the output signal from the delay means (1). Detection device. 7. An input signal disconnection detecting device for detecting the interruption of the input of a pulsed periodic signal, and a first delay means (3) for delaying the input signal by (n + 1/4) cycles, D for inputting the input signal and the output signal from the first delay means (3) to the D terminal and the clock terminal, respectively.
A flip-flop (4), a first averaging means (5) for averaging the output of the D-flip-flop (4), and an output level of the first averaging means (5) being a first First comparing means (6) for comparing with a reference level, and second for delaying the input signal by (m + 1/2) cycles
Delay means (7), an exclusive OR circuit (8) for inputting the input signal and an output signal from the second delay means (7), and an average of outputs of the exclusive OR circuit (8). Second averaging means (9) for averaging, second comparing means (10) for comparing the output level of the second averaging means (9) with a second reference level, and the first comparing Means (6) and second comparing means (1
0) inputting each output of the NAND circuit (11); 8. The input signal loss detection device according to claim 7, wherein the second reference level is smaller than the first reference level.