JPH06314148A - Key scan circuit - Google Patents

Abstract

PURPOSE:To prevent the misoperation of an equipment by detecting the depression state of a key of a keyboard which becomes faulty at the time of power-ON operation and to reduce the harmonic disturbance which is generated during scanning operation. CONSTITUTION:The key scan circuit is provided with a key scan control circuit 40 which inputs a POR signal at the same time with the power-ON operation. This key scan control circuit 40 receives the POR signal and outputs a control signal S2 for starting key-scanning operation to a key scan pulse generating circuit 50. Further, this key scan control circuit 40 outputs a control signal S3 for stopping the scanning operation to the key scan pulse generating circuit 50 a set time later. The key scan circuit forcibly performs the scanning operation with those signals S2 and S2 right after the power source is turned ON to detect a fault of a key switch in a key matrix 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key scan circuit in a keyboard device or the like.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference: Japanese Patent Application Laid-Open No. 1-260520 The key matrix has a plurality of key switches corresponding to a plurality of keys. The key scan circuit is a circuit that performs a scan operation to detect which key in the key matrix is pressed by the scan pulse SSC generated in the circuit. The conventional key scan circuit includes a key scan circuit that always performs a scan operation and a key scan circuit that starts a scan operation after detecting depression of any key in the key matrix.

First Conventional Example FIG. 2 is a configuration block diagram showing an example of a conventional key scan circuit. The key scan circuit is a circuit that always performs a scan operation. The key scan circuit of FIG. 2 has n first scan lines and m second scan lines intersecting the scan lines, and is arranged in a matrix at each n × m intersections. The key switch 10 and the first and second scanning lines form a key matrix 10. The key scan circuit inputs a pulse and sequentially outputs the pulse as a scan pulse SSC to the n first scan lines, and a scan pulse SSC from the shift register 11 via each key switch. The input latch circuit 12 that inputs by the second scanning line, the counter 13, the shift register 11 that generates a pulse, and the input latch circuit 1
2 and a counter 13, and a pulse generation circuit 14 for supplying a pulse to each of the input latch circuit 12 and the counter 1.
3 to output the output data Dout of the scan operation result and to output the signal S10 indicating that the key has been pressed. The operation of the key scan circuit of FIG. 2 configured as above will be described.

When the state level of the active signal during the scanning operation in the key matrix 10 is "L" and the non-active state is "H", one of the n first scanning lines is generated by the scan pulse SSC. Only "L" and the other n-1 lines are "H". This "L" scanning line is shifted by the shift register 11 in response to the input of a pulse from the pulse generating circuit 14, and is sequentially moved in each of the first scanning lines. The state of the m key switches connected to the first scanning line in the "L" state is
The input latch circuit 12 latches via the m second scanning lines. At the same time, the counter 13 also has a pulse generation circuit 14
The number of the first scanning line in the key matrix 10 being "L" is counted in accordance with the input pulse from.
The output signal of the input latch circuit 12 and the output signal of the counter 13 are input to the determination circuit 15, and the determination circuit 15 detects the pressed key in the key matrix 10 by these output signals and outputs it as the data Dout. , Key press signal S10 is output.

Second Conventional Example FIG. 3 shows a key scan circuit of an improved example of FIG. The key scan circuit is configured to start the scan operation after detecting the depression of any key in the key matrix. Therefore, the scan pulse SSC is generated only during the time when the key is pressed, and harmonic interference due to the harmonic of the scan pulse SSC is reduced.
The key scan circuit of FIG. 3 has n first scan lines and m second scan lines intersecting the scan lines, and each of the n × m intersections is the same as in FIG. A key matrix 10 is composed of the key switches arranged in a matrix and the first and second scanning lines. The key scan circuit inputs a pulse and sequentially outputs a pulse as a scan pulse SSC from the n output terminals of the shift register 21, and the output of the shift register 21 is controlled to control the first n of the key matrix 10. 22-1 and 22-2 for outputting the scan pulse SSC to the scan line of
2-n, the input latch circuit 23 for inputting the scan pulse SSC from the gates 22-1 to 22-n through the respective key switches on the second scan line, the counter 24, and generating the pulse. It has a shift register 21, an input latch circuit 23, and a pulse generation circuit 25 for supplying pulses to a counter 24, respectively. The key scan circuit is connected to the m second scan lines to control the opening / closing of the gates 22-1 to 22-n and also to control the drive of the pulse generating circuit 25. Is equipped with. Further, the key scan circuit inputs the output signals of the input latch circuit 23, the counter 24, and the press-down determination circuit 26, detects the pressed key, outputs the output data Dout, and outputs a signal indicating that the key is pressed. The determination circuit 27 outputs S10.

The operation of the key scan circuit configured as above will be described below. When all the key switches are not pressed, that is, when all the key switches are off, the output signal of the depression determination circuit 26 of FIG. 3 controls the gates 22-1 to 22-n to shift register 21. Signal level of n first scanning lines regardless of the output of
To After that, the push-down determination circuit 26 determines whether or not the signal level of at least one of the m second scanning lines is "L", and if not "L", the current state is maintained as it is. That is,
The output signal of the push-down determination circuit 26 is the pulse generation circuit 25.
All pulses of the gates 22-1 to 22-n are set to "L" without generating a pulse. At the same time, the depression determination circuit 26 informs the determination circuit 27 that the key is not pressed. Here, if one or more of the m second scanning lines is at the signal level “L”, the output signal of the push-down determination circuit 26 causes the pulse generation circuit 25 to generate a pulse. At the same time, the output signal of the push-down determination circuit 26 controls the gates 22-1 to 22-n to output the scan pulse SSC from the shift register 21 to the key matrix 10 as it is to start the scan operation. Further, the depression determination circuit 26 informs the determination circuit 27 that the key switch has been depressed. Then, determine which key switch is turned on by the first
The same operation as that of the conventional example is performed.

[0007]

However, the conventional key scan circuit has the following problems.
For example, in the case of a normally-off key switch, if the key is broken and the key is always in the on state, in the first conventional example, the judgment circuit 15 always judges that the switch of the broken key is in the depressed state, which causes the malfunction of the device. Becomes The first in the second conventional example
In addition to the disadvantage of the prior art example, since the key switch of the defective key is always in the ON state, the push-down determination circuit 26 always outputs the first control signal to the pulse generation circuit 25, and the scan operation is continuously performed. Done. As a result, the advantages of the second conventional example are not exerted, and the scan pulse SS
Harmonic interference due to the harmonics of C cannot be reduced. Also,
In the second conventional example, if the key switch is continuously pressed for a long time even if the key switch for the defective key is not held, the key scan operation is continuously performed as described above.
The advantage of the prior art example is not exerted, and the harmonic interference due to the harmonic of the scan pulse cannot be reduced. SUMMARY OF THE INVENTION The present invention solves, as problems that the above-mentioned conventional art has, a key scan circuit that solves the problem of erroneous detection when a key fails and that harmonic interference cannot be reduced when the key is pressed and the key switch is pressed for a long time. Is provided.

[0008]

According to a first aspect of the present invention, in order to solve the above-mentioned problems, a key scan circuit is provided at each intersection of a plurality of intersecting first scanning lines and a plurality of second scanning lines. A key matrix in which a plurality of key switches are arranged in a matrix, a key scan pulse generation circuit that sequentially outputs a scan pulse to the first scan line, and a scan pulse for the second scan via the key switch. An input latch circuit for inputting from a line and a first control signal for controlling the output of the key scan pulse generation circuit based on the ON / OFF state of each key switch in the key switch is output to the key scan pulse generation circuit. And a key input determination circuit for Then, a signal generated when the power is turned on is input, and a second control signal for starting the scan operation and a third control signal for stopping the scan operation after a lapse of a predetermined time are sent to the key scan pulse generating circuit. The supplied key scan control circuit is provided in the key scan circuit.

According to a second aspect of the invention, the key scan circuit includes a key matrix in which a plurality of key switches are arranged in a matrix at each intersection of a plurality of intersecting first scanning lines and a plurality of second scanning lines. A key scan pulse generation circuit for sequentially outputting scan pulses to the first scan line,
A first input latch circuit for inputting the scan pulse from the second scan line via the key switch, and control of the key scan pulse generation circuit based on an on / off state of each key switch in the key switch. First to do
And a key input determination circuit for applying the control signal of 1 to the key scan pulse generation circuit. The key input determination circuit includes a first latch circuit that latches each signal level of the second scanning line at a predetermined timing, and the first latch circuit.
The second latch circuit that latches the output signal of the first latch circuit at a timing different from that of the second latch circuit and the output signals of the first and second latch circuits are detected, and when they do not match, And a mismatch circuit that outputs the first control signal.

[0010]

According to the first aspect of the invention, since the key scan circuit is constructed as described above, the key scan control circuit supplies the second control signal to the key scan pulse generating circuit when the power is turned on, and the key scan pulse is generated. The pulse generated by the generating circuit is output to the key matrix. The input latch circuit inputs the scan pulse via the second scan line to forcibly perform the scan operation for detecting the on / off state of each key switch. Then, after a lapse of a predetermined time, the key scan control circuit supplies the third control signal to the key scan pulse generating circuit, and the key scan pulse generating circuit stops the pulse generation. Therefore, the scan operation is stopped. After that, the key input determination circuit detects the on / off state via the second scan line, supplies the first control signal to the key scan pulse generation circuit, and is generated by the key scan pulse generation circuit. Pulse is output to the key matrix. The input latch circuit inputs the scan pulse through the second scan line to perform the scan operation of detecting the on / off state of each key switch.

According to the second invention, when the outputs of the first latch circuit and the second latch circuit do not match, that is, after being latched by the first latch circuit, the state of each key switch changes. Is latched by the second latch circuit,
The first control signal is supplied to the key scan pulse generation circuit. The scan pulse generated by the key scan pulse generation circuit is output to the key matrix, and the scan operation is performed. Therefore, the above problem can be solved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing the configuration of a key scan circuit according to the first embodiment of the present invention. This key scan circuit forcibly performs a scan operation to detect which key switch is in a pressed state for a predetermined time when the power is turned on, and then any key switch in the key matrix is A key scan circuit that detects which key switch is in the pressed state when the key is pressed. The key scan circuit of FIG. 1 has n first scan lines and m second scan lines intersecting the scan lines, and n × m key switches arranged in a matrix at each intersection. The key matrix 10 configured as described above and the second scan line thereof detect that one of the key switches in the key matrix 10 is in the depressed state, and detect the first scan start.
A key input determination circuit 30 for generating a control signal S1 of, and a power-on reset when the power is turned on (hereinafter referred to as POR)
A key scan control circuit 40 which inputs a signal and outputs a second control signal S2 for starting scanning when the power is turned on and outputs a third control signal S3 for stopping scanning after a predetermined time has elapsed. is doing.

The key scan circuit also includes signals S1 to S.
A key scan pulse generation circuit 50 for generating a scan pulse SSC based on 3 and sequentially outputting the scan pulse SSC to the n first scan lines of the key matrix 10. The key scan pulse generation circuit 50 includes, for example, a shift register, a counter, and a pulse generation circuit that receives the signals S1 and S2 and generates a pulse.
The latch signal S4 and the load signal S5 are respectively output. . In addition to the key scan circuit,
An input latch circuit 60 having an m-bit input for latching the state of the second scanning line connected to the first scanning line via a key switch in synchronization with the signal S4, and an input latch circuit 60.
An output register 70 of a shift register for accumulating the information from (1) by n × m bits by the signal S5. FIG. 4 shows each signal POR, S2, S when the power is turned on.
3 is a time chart of generation and output data of a scan pulse SSC from the key scan pulse generation circuit 50.

The operation of the key scan circuit will be described with reference to FIGS. 1 and 4. When the POR signal is, for example, a signal that is at “H” level when the power is turned on and becomes “L” after a certain time has elapsed, the key scan control circuit 40 is turned on when the power is turned on.
Outputs a signal S2 of “H” level to the key scan pulse generation circuit 50, for example. The key scan pulse generation circuit 50 sequentially outputs an active scan pulse SSC of, for example, "L" to the first scan line when the level of the POR signal becomes "L" in response to the signal S2, and scans the first scan line. The operation is started. When the scan operation is started, the output signal S2 of the key scan control circuit 40 is
It becomes "L". When the scan is started, the key scan pulse generation circuit 50 outputs the signal S4 to the input latch circuit 60 and the signal S5 to the output register 70, respectively. With these signals, the data of the n × m key switches detected by the scan operation is accumulated in the output register 70 via the input latch circuit 60 and output as the scan result data Dout. When a predetermined time elapses after the scan operation is started, the level of the signal S3 from the key scan control circuit 40 becomes "H". Receiving signal S3, key scan pulse generating circuit 50
Stops the generation of the scan pulse SSC and stops the scan operation.

Thereafter, as in the second conventional example, the key input determination circuit 30 outputs the signal S1 as a key only when one or more of the m second scanning lines are "L". Output to the scan pulse generation circuit 50. The key scan pulse generation circuit 50 sequentially outputs the scan pulse SSC of "L" to the first scan line, and the key scan circuit starts the scan operation. When the scan operation is started, the key scan pulse generation circuit 50 outputs the signal S4 to the input latch circuit 60 and the signal S5 to the output register 70, respectively. With these signals, the data of the n × m key switches detected by the scan operation is accumulated in the output register 70 via the input latch circuit 60 and output as the output data Dout. Here, in the case of the key matrix 10 configured by only normal normally-off key switches, all the key switches are in a non-depressed state when the power is turned on. Therefore, for example, the signal level “L” is output from the output register. Is output. If a part of the key fails and the key switch is still pressed, the result of the scan operation at power-on is that the key data “H” corresponding to the failed part is output through the output register. It is output as Dout. 5 is a circuit diagram showing a configuration example of the key scan control circuit 40 in FIG. 1, and FIG. 6 is a time chart of FIG.

The key scan control circuit 40 will be described with reference to FIGS. The key scan control circuit 40 is
RS (reset set) flip-flop (hereinafter referred to as RS) that inputs the POR signal and outputs the signal S2 when the power is turned on.
-FF) 41, a key scan stop circuit 42 that generates the signal S3 in FIG. 1, and an inverter 43 that inverts the output signal level of the RS-FF 41. The RS-FF 41 is connected to, for example, a counter of the key scan pulse generation circuit 50, and receives the reset signal S6 from the counter. The key scan stop circuit 42 is a delay flip-flop (hereinafter referred to as D-FF) that inputs the power supply potential Vdd to the data terminal and the signal S7 from the counter of the key scan pulse generation circuit 50 to the clock terminal, and a NOR circuit. It is configured. When the POR signal becomes “H” when the power is turned on, R
The output of the S-FF 41 is “H” via the inverter 43.
Is output to the pulse generation circuit in the key scan pulse generation circuit 50. At this time, the signal S3 of the key scan stop circuit 42 is set to "L" by the signal S7 whose level in the normal state is set to "H", for example.
Becomes When a "L" pulse is input from the counter of the key scan pulse generation circuit 50 to the key scan stop circuit 42 as the signal S7 at the time when the scan of the key scan circuit is completed, for example, one cycle, the signal S3 becomes
It becomes "H". The scanning operation is stopped by the "H" signal S3. Further, when the key scan is started, the signal S
For example, 6 is set to "H" by a counter in the key scan pulse generation circuit 50, and the signal S6 of "H" resets the RS-FF 41 to set the output signal S2 to "L".

As described above, in the present embodiment, since the scan operation is forcibly performed after the power is turned on, it is possible to detect the key failure by checking the output data. Therefore, for example, by storing the output data in a memory or the like and processing the input data of the failure key as invalid thereafter, it is possible to prevent the malfunction of the device due to the key failure. In addition, even when the scan operation is started due to a key failure, a key scan stop signal can be generated to prevent continuous scan operation by comparing with the key failure data at power-on, and harmonic interference can be reduced. Become.

Second Embodiment FIG. 7 is a block diagram showing the configuration of a key scan circuit according to the second embodiment of the present invention. This key scan circuit is a circuit that detects a change when any of the key switches in the key matrix changes from on to off or from off to on and starts a scan operation. The key scan circuit of FIG. 7 has n first scan lines, m second scan lines intersecting the scan lines, and n at each intersection.
A key matrix 10 formed by arranging xm key switches in a matrix and a second scanning line thereof detects that any one of the key switches in the key matrix 10 has changed, Key input determination circuit 8 for generating a first control signal S1 for starting scanning
0 and. The key scan circuit further includes a key scan pulse generation circuit 50 that sequentially outputs the scan pulse SSC to the n first scan lines of the key matrix 10 based on the signal S1. , And also outputs the latching signal S4 and the load signal S5. The key scan circuit includes an m-bit input latch circuit 60 for latching the state of the second scan line connected to the first scan line via a key switch in synchronization with the signal S4, and an input latch circuit. An output register 70 of a shift register for accumulating the information from 60 by n × m bits by the signal S5.

FIG. 8 is a block diagram showing a configuration example of the key input determination circuit 80. This key input determination circuit 80
A first latch circuit 81 connected to the second scanning line for latching the signal level of each scanning line; a second latch circuit 82 for receiving the output signal of the first latch circuit 81; A non-coincidence circuit 83 is provided which detects the coincidence or non-coincidence of the output signals of the second latch circuit and supplies the signal S1 to the key scan pulse generation circuit 50 if the two signals do not coincide.

The operation of the key scan circuit will be described with reference to FIGS. 7 and 8. Immediately after turning on the power, the latch circuit 8
The same data is latched in Nos. 1 and 82, and the output signal of the mismatch circuit 83 is, for example, "L". When the on / off state of any of the key switches in the key matrix 10 is changed by the key operation, the data of the second scanning line is latched in the latch circuit 81 by the latch signal L1 having a certain fixed cycle. At this time, the latch circuit 82
Since the data before the key operation is latched, the output signal of the mismatch circuit 83 becomes "H" and is output to the key scan pulse generation circuit 50 as the signal S1. Upon receiving the signal S1 of "H", the key scan pulse generation circuit 50 generates the scan pulse SSC, and the scan operation is started. After that, for example, when one cycle of the scan operation is completed, the latch signal L2 is set to the latch circuit 82.
Then, the latch circuit 82 latches the data of the latch circuit 81. Therefore, the output signals of the latch circuits 81 and 82 match and the output signal S1 of the mismatch circuit 83 becomes
It becomes "L". Then, upon receiving the signal S1 of "L", the key scan pulse generation circuit 50 causes the scan pulse SSC
, And the key scan circuit stops the scan operation. The latch circuits 81 and 82 prepare for the next change of key input when the output signals match.

As described above, in the present embodiment, when one of the key switches in the key matrix changes its state from on to off or from off to on, the scan operation is started for a certain set time. Since the scanning operation is stopped, the scanning operation is not continuously performed even when the key is continuously pressed for a long time, and harmonic interference due to harmonics can be reduced. Also, when the state of the key switch changes, it scans, so
Compared to the conventional key scan circuit that detects only the pressed state of the key switch, continuous scanning is not performed even for a system that imposes significance on the time the key switch is pressed, for example. It is possible to reduce harmonic interference due to harmonics.

The key scan circuit of the third embodiment the third embodiment, in the first embodiment, in the configuration obtained by replacing the key input determination circuit 30 to the key input determination circuit 80 in the second embodiment .

FIG. 9 shows a key scan control circuit 40, a key input determination circuit 80, and a key scan pulse generation circuit 50.
It is a block diagram of. Key scan pulse generation circuit 50
Signals S1 and S2 for outputting scan pulse SSC to
In the key scan pulse generation circuit 50, for example, AN
The scan operation is performed when the signal is input via the D circuit and at least one of the signals S1 and S2 is at an active signal level. Therefore, this key scan circuit, like the first embodiment, for a predetermined time when the power is turned on,
A forced scanning operation is performed to determine which key switch is in the pressed state, and thereafter, as in the second embodiment, any of the key switches in the key matrix 10 is switched from on to off or off. The key scan circuit starts a scan operation and stops the scan at a set time when the state changes from ON to ON.

As described above, in the present embodiment, since the key scan is forcibly performed after the power is turned on, it becomes possible to detect the key failure, and thereafter, the input data of the failure key is treated as invalid. This can prevent malfunction due to key failure. Further, after that, when one of the key switches in the key matrix changes its state from on to off or from off to on, scanning is started, and for example, scanning is stopped after one cycle of scanning operation. Even when the key is pressed for a long time, the scanning operation is not continuously performed, and the harmonic interference due to the harmonic can be reduced. Since the scanning operation is performed when the state of the key switch changes, compared to a conventional key scan circuit that detects only the pressing of the key switch, for example, a system that imposes a significance on the time when the key switch is pressed. Also, since continuous scanning is not performed, it is possible to reduce harmonic interference due to harmonics.

The first to third embodiments are not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the first to third embodiments, the key matrix 10
Although the normally-off key switch is used therein, the same effect can be obtained by using the normally-on key switch or the normally-on / off mixed key switch. (2) In the first to third embodiments, the key matrix 10
Regarding the signal level during the scanning operation of, the active state is set to "L", but the operation and the effect are the same even if "H" is set only by changing each logic circuit. (3) Second and third embodiments In the example, the scanning operation started by the signal S1 is performed only for one cycle, but it may be changed depending on the purpose.

[0026]

As described in detail above, according to the first aspect of the invention, immediately after the power is turned on, the scan of the key switches in the key matrix is forcibly performed by the second control signal. By this scan, the defective key switch is detected immediately after the power is turned on. For example, the detection result can be stored in a memory or the like to invalidate the data of the subsequent defective key. In addition, for example, when displaying the switch function on a display, etc., it is possible to operate the system normally by invalidating the faulty part and reassigning to the key and changing the function display of each switch. Become. Therefore, malfunctions of the device due to the failure of the key switch can be reduced. According to the second invention,
When any key switch in the key matrix changes state from on to off or from off to on,
Since the scan operation is started and stopped at a certain set time, even if the key is held down for a long time, the scan operation does not continue and the harmonic Interference can be reduced. Furthermore, since scanning is started when the state of the key switch changes, compared to the conventional key scan circuit that detects only the pressing of the key switch, for example, the time during which the key switch is pressed imposes significance. Even when used in such a system, since continuous scanning is not performed while the switch is being pressed, it is possible to reduce harmonic interference due to harmonics.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a key scan circuit of a first embodiment.

FIG. 2 is a block diagram showing a key scan circuit of a first conventional example.

FIG. 3 is a block diagram showing a key scan circuit of a second conventional example.

FIG. 4 is a time chart of the control signal of FIG.

5 is a circuit diagram showing a configuration example of a key scan control circuit in FIG.

FIG. 6 is a time chart of control signals in FIG.

FIG. 7 is a block diagram showing a configuration example of a key scan circuit of a second embodiment.

FIG. 8 is a block diagram showing a key input determination circuit in FIG.

FIG. 9 is a block diagram showing a configuration example of a key scan circuit of a third embodiment.

[Explanation of symbols]

SSC scan pulse S1 to S3 first to third control signals 10 key matrix 30,80 key input determination circuit 40 key scan control circuit 50 key scan pulse generation circuit delay circuit 60 input latch circuit Dout output data

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G06F 11/22 370 A 7737-5B

Claims (2)

[Claims] 1. A key matrix in which a plurality of key switches are arranged in a matrix at each intersection of a plurality of intersecting first scanning lines and a plurality of second scanning lines, and the first scanning lines are sequentially arranged. A key scan pulse generation circuit that outputs a scan pulse; an input latch circuit that inputs the scan pulse from the second scan line via the key switch; and an on / off state of each key switch in the plurality of key switches. A key input determination circuit for giving a first control signal for controlling the output of the key scan pulse generation circuit based on the state to the key scan pulse generation circuit, and for detecting an on / off state of the key switch. In a key scan circuit that performs a scan operation, a second control signal for starting a scan operation and a predetermined control signal are generated based on a signal generated when power is turned on. The third control signal and a key scan circuit, characterized in that a key scan control circuit for supplying to said key scan pulse generation circuit for the scanning operation is stopped after a time lapse. 2. A key matrix in which a plurality of key switches are arranged in a matrix at each intersection of a plurality of intersecting first scanning lines and a plurality of second scanning lines, and the first scanning lines are sequentially arranged. A key scan pulse generation circuit that outputs a scan pulse; a first input latch circuit that inputs the scan pulse from the second scan line via the key switch; and a key switch of each of the plurality of key switches. A key input determination circuit for giving a first control signal for controlling the output of the key scan pulse generation circuit to the key scan pulse generation circuit based on the on / off state, and detecting the on / off state of the key switch. In the key scan circuit for performing the scanning operation for performing the scanning operation, the key input determination circuit is configured to set each signal level of the second scanning line at a predetermined timing. A first latch circuit that latches the first latch circuit and the first latch circuit at a timing different from that of the first latch circuit.
Second latch circuit for latching the output signal of the latch circuit, and a non-coincidence circuit for detecting the coincidence or non-coincidence of the output signals of the first and second latch circuits and outputting the first control signal when they do not coincide. A key scan circuit characterized by being configured with.