JPH06314252A - Data transfer system - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the data transfer performance from the CPU to the I / O and to improve the utilization efficiency of the I / O bus. [Structure] The present invention comprises a CPU 1 and an I / O bus control mechanism 2.
And an information processing device including I / O-3,
The bus control mechanism 2 has a data buffer 6 and a data transfer start flag 7, and temporarily transfers data to the data buffer 6 when transferring data from the CPU 1 to the I / O-3. Data is stored, and when the data transfer start flag 7 is accessed, the data is transferred.
Data is transferred from the data buffer 6 to the I / O-3 by using the burst transfer function of the I / O bus 5. According to the present invention, the burst transfer function of the I / O bus can be effectively utilized to perform data transfer from the CPU to the I / O, thus improving the data transfer speed. Can be achieved. In addition, by using burst transfer, the bus occupation time per unit data transfer can be reduced,
The utilization efficiency of the I / O bus can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system in an information processing system, and more particularly, it uses burst transfer from CPU to I / O to enable high speed data transfer. Data transfer method.

[0002]

2. Description of the Related Art Generally, a CP in an information processing system
Data access from the U to the I / O is performed in a basic data length unit handled by a CPU called a word or a partial length unit thereof. For example, in the case of a 32-bit microprocessor, the basic processing data length of 32 bits (4
In general, data access to I / O is performed in units of 16 bytes (2 bytes) or 8 bits (1 byte).

On the other hand, in the I / O bus to which the I / O is connected, the data width of the I / O bus is used for the purpose of improving the data transfer processing speed and improving the I / O bus utilization efficiency. It is possible to have a burst transfer function for transferring the above data in one bus cycle.

This burst transfer is a method in which data having a size larger than the bus width is divided into bus width units and continuously transferred in a bus cycle.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the data transfer from the CPU to the I / O, the unit for transferring the data of the CPU bus is determined, so CP
There is a problem that data transfer with a data length exceeding the basic processing data length of U cannot be performed, and the burst transfer function of the I / O bus cannot be effectively utilized.

The present invention has been made in view of the above, and an object thereof is to effectively use the burst transfer function of the I / O bus even in the data transfer from the CPU to the I / O. The purpose is to improve the data transfer speed from the CPU to the I / O and to improve the utilization efficiency of the I / O bus.

[0007]

In order to achieve the above object, in the present invention, an I / O bus control mechanism for controlling the bus between the CPU and the I / O is provided with maximum data from the CPU to the I / O. When a data buffer larger than the transfer size and a data transfer activation flag for instructing the data transfer activation to the I / O are provided and data is transferred from the CPU to the I / O first, The data is transferred to the data buffer in the I / O bus control mechanism in units of data transfer size from the CPU to the I / O, and then the data transfer start flag is accessed to access the data. This can be achieved by transferring data from the data buffer to I / O.

[0008]

By setting the size of the data buffer to the burst transfer size of the I / O bus, the data transfer start flag is accessed to transfer the data in the data buffer to the I / O bus.
It becomes possible to transfer to the I / O using the burst transfer function of the I / O bus, which improves the data transfer speed from the CPU to the I / O and improves the utilization efficiency of the I / O bus. be able to.

In addition to having a plurality of the data buffers, and having a data buffer instruction flag indicating which buffer is to perform the next data transfer, the CPU can access the data buffers. When it occurs, it writes to the data buffer indicated by the data buffer instruction flag, and when the access to the data transfer start flag occurs, the contents of the data buffer indicated by the data buffer instruction flag are transferred to the I / O and If the value of the data buffer instruction flag is updated and the next data buffer is updated as indicated, the I / O from the data buffer is changed.
Data can be stored in another data buffer from the CPU even during data transfer to the CPU, and the efficiency of CPU data processing can be improved.

Further, regarding the data transfer cycle from the data buffer to the I / O which is started by accessing the data transfer start flag, the data is received from the I / O within a specified time after the start of the cycle. When the notification of the available status is received, the data transfer is continued, and when the notification of the ready status of the data is not received from the I / O within the specified time, the data transfer cycle is stopped. In addition to the control, the access to the data transfer start flag is set as a read access, and the presence or absence of the data receivable state notification is read for the read access to the data transfer start flag.
By responding as data, it is not necessary to check whether or not the I / O is ready to receive the data before starting the data transfer, and the data from the CPU to the I / O is not required. The data transfer rate can be improved.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a first schematic block diagram showing an embodiment of a data transfer system according to the present invention, and FIG. 2 is a timing showing an operation from the CPU 1 to the I / O-3 in FIG. It is a figure.

In FIG. 1, 1 is a CPU, 2 is an I / O bus control mechanism, 3 is I / O, 4 is a CPU bus connecting the CPU 1 and the I / O bus control mechanism 2, and 5 is an I / O bus. An I / O bus connecting the control mechanism 2 and the I / O-3 is shown.
In the / O bus control mechanism 2, 6 is a data buffer, 7 is a data transfer start flag, 8 is an I / O bus output data buffer, 9 is an address buffer, 10 is a CPU bus control circuit, and 11 is I. The / O bus control circuit is shown.

In this embodiment, the CPU bus 4 is a CPU that represents the 32-bit CPU bus data line 12, the 32-bit CPU bus address line 13, and the type and timing of the data transfer cycle of the CPU bus. Bus control line 14
Have and. The I / O bus is a 32-bit I / O.
It has a bus data line 26, a 32-bit I / O bus address line 27, and an I / O bus control line 28 showing the type and timing of the data transfer cycle of the I / O bus. The data buffer has a length of 32 bytes, and access to the data buffer is possible in units of 4 bytes.

The CPU in FIG. 1 will be described below with reference to FIG.
The data transfer from 1 to I / O-3 will be described in detail.

The CPU 1 writes transfer data in the data buffer 6 in units of 4 bytes (32 bits). This is performed by activating the 4-byte write cycle -29a, 29b, 29c shown in FIG. 2 eight times to the CPU bus. At this time, the CPU bus control circuit 10
From the information of the CPU bus address line 13 and the CPU bus control line 14 of the U bus 4, the data write pulse signal 15 is output to the 4 bytes currently in the write cycle in the data buffer 6. The data of the CPU bus data line 12 is written in the data buffer 6.

Next, the CPU 1 sends the data transfer start flag 7
The flag access 30 shown in FIG. The CPU bus control circuit 10 outputs the write pulse signal 16 to the data transfer start flag 7 from the information of the CPU bus 4 as in the case of writing to the data buffer 6. In this embodiment, the data transfer start flag 7 is 1 bit, and the CPU
The value of the least significant bit of the bus data line 12 is written, and when this value is 1, the data transfer is started. When the value of the data transfer start flag 7 becomes 1,
The output data 18 is transmitted to the I / O bus control circuit 11. The I / O bus control circuit 11 outputs a write pulse signal 19 to the I / O bus data buffer 8, and the 32 bytes of data stored in the data buffer 6 are transferred to the I / O bus data buffer 8. Transferred.

Next, the I / O bus control circuit 11 operates the I / O bus.
A 32-byte burst transfer 31 shown in FIG.
To start. At this time, a signal indicating 32-byte burst transfer is output to the I / O bus control line 28, and the data of the I / O bus data buffer 8 is output to the I / O bus data line 26 in units of 4 bytes. Is output continuously. This is I / O
Bus data buffer output signal selector 20 and I
This is performed by controlling the selector 21 for the / O bus data output signal using the select signals 23 and 24. The address information stored in the address buffer 9 is output to the I / O bus address line 27. This is done by controlling the address selector 22 using the select signal 25. The content of the address buffer 9 may be set by the CPU 1 or a fixed value may be stored in advance.

In this embodiment, the data transfer start flag 7 is realized by a data holding means such as a flip-flop, but only the address of the data transfer start flag 7 is specified and When access to the address occurs, CP
The U bus control circuit 10 is
The data transfer start signal 17 may be output.

As described above, according to this embodiment,
When data is transferred from the CPU 1 to the I / O-3, the transfer data is temporarily stored in the data buffer 6 and then the data transfer start flag 7 is accessed to access the I / O bus. Since the data transfer can be performed by using the burst transfer function of No. 5, the high speed data transfer can be performed and the I
The utilization efficiency of the / O bus can be improved.

FIG. 3 is a second schematic block diagram showing an embodiment of the data transfer system according to the present invention.

In FIG. 3, reference numeral 32 is a data buffer instruction flag for instructing the two data buffers 6a and 6b which data buffer is to be used. The data buffer instruction flag 32 outputs data. An AND gate 33 for switching which data buffer the data write pulse 15 is output to, and data for selectively outputting the data of the two data buffers according to the value of the data buffer instruction flag 32. This is a configuration including a buffer selector 34.

When writing data from the CPU 1 to the data buffers 6a and 6b, the output of any AND gate 33 becomes valid depending on the value of the data buffer instruction flag 32, and any data is output. -Only the data buffer is written. I / O from the data buffers 6a and 6b
-3, the data buffer selector 3 is used for data transfer.
One of the data buffers 6a and 6b is selected by 4 and the data is transferred to the I / O bus data buffer 8. The value of the data buffer instruction flag 32 is switched by the data buffer switching signal 35 from the I / O bus control circuit 11 when the data transfer is activated.

According to the present embodiment, the data buffer I
While data is being transferred to the I / O, the data is transferred to another data buffer.
Since the data can be written, the processing efficiency of the CPU can be improved.

FIG. 4 is a third schematic block diagram showing an embodiment of the data transfer system according to the present invention. When the data transfer trajectory flag 7 is accessed, a data transfer start instruction is issued. In this embodiment, the I / O-3 responds whether or not the data can be received while the I / O-3 is performing.

In FIG. 4, access to the data transfer activation flag 7 is defined as read access, and the read access is defined.
The read access read data has a value indicating whether or not this I / O is in a data receivable state for data transfer to the I / O-3. Data transfer start flag 7
When a read access to the CPU occurs, the CPU bus control circuit 10 issues a data transfer start instruction to the I / O bus control circuit 11. After this, the I / O bus control circuit 11
I / O from the data buffer 6 according to the procedure described in the above embodiment.
Data transfer to -3. At this time, during the data transfer cycle, the value of the data receivable state signal output from the I / O-3 of the I / O bus control signal line 28 is receivable within a specified time. When the status is indicated, the data transfer is continued and the read data for the data transfer start flag 7 is set to a value indicating the data receivable status. However, if the I / O-3 is not ready to receive the data within the specified time, this data transfer cycle is stopped and the data transfer start flag 7 is read.
The data is set to a value indicating that the data cannot be received. According to the present embodiment, I / O status check and I / O
The data transfer start instruction to O-3 can be realized by one access, and the processing performance can be improved.

[0027]

As described above, according to the present invention,
Utilizing the burst transfer function of the I / O bus effectively, CP
When data is transferred from U to I / O, the data transfer speed can be improved. Further, by using the burst transfer, the bus occupation time per unit data transfer can be reduced and the utilization efficiency of the I / O bus can be improved.

[Brief description of drawings]

FIG. 1 is a first schematic configuration diagram showing an embodiment of a data transfer system according to the present invention.

FIG. 2 is a timing chart showing an operation from CPU 1 to I / O 3 in FIG.

FIG. 3 is a second schematic configuration diagram showing an embodiment of a data transfer system according to the present invention.

FIG. 4 is a third schematic configuration diagram showing an embodiment of a data transfer system according to the present invention.

[Explanation of symbols]

1-CPU, 2-I / O bus control mechanism, 3-I / O, 4
-CPU bus, 5-I / O bus, 6-data buffer,
7-data transfer start flag, 8-I / O bus data buffer, 9-address buffer, 10-CPU bus control circuit, 11-I / O bus control circuit, 32-data buffer instruction flag

Claims (4)

[Claims] 1. An information processing system including an I / O bus control mechanism that enables a connection between a CPU and an I / O bus, wherein the I / O bus control mechanism is operated from the CPU to the I / O bus.
To a data buffer having a size larger than the maximum size of the data transfer output to the I / O, and a data buffer for instructing the data buffer to send the data transfer to the I / O.
A data transfer start flag, and when the data transfer from the CPU to the I / O is performed, temporary storage is performed in the data buffer in units of the data transfer output from the CPU. A data transfer system characterized in that data is transferred from the data buffer to the I / O by accessing the data transfer start flag from the CPU. 2. In the information processing system, the data
There is a plurality of data buffers, and a data buffer instruction flag for selecting the data buffers at the time of data transfer to the plurality of data buffers, and access from the CPU to the data buffers. Is generated, the contents are written in the data buffer indicated by the data buffer instruction flag, and when the access to the data transfer start flag occurs, the contents of the data buffer designated by the data buffer instruction flag are written in the I buffer. 2. The data transfer system according to claim 1, wherein the value of the data buffer instruction flag is updated while the data is transferred to / O. 3. In the information processing system, the data
Regarding the data transfer cycle from the data buffer to the I / O which is started by accessing the data transfer start flag, the data transfer start flag is set within the specified time after the start of the data transfer cycle. When the notification of the data receivable state is received from the I / O, the data transfer is continued, and when the notification is not received from the I / O within the specified time, the data transfer cycle is stopped. 2. The data transfer system according to claim 1, wherein said data transfer start flag responds to said CPU whether or not there is said notification. 4. In the information processing system, the data
Regarding the data transfer cycle from the data buffer to the I / O which is started by accessing the data transfer start flag, the data transfer start flag is set within the specified time after the start of the data transfer cycle. When the notification of the data receivable state is received from the I / O, the data transfer is continued, and when the notification is not received from the I / O within the specified time, the data transfer cycle is stopped. Together with the control to suppress the update of the value of the data buffer instruction flag,
The data transfer start flag responds to the CPU as to whether or not there is the notification.
Data transfer method.