JPH06314498A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to prevent a reverse repair from occurring in the relationship between an inverted bit and a non-reversed bit between a redundant rescue LSI and a non-relief LSI, and to make the rescue LSI a non-relief LSI. This makes it possible to accurately evaluate the influence of interference between adjacent memory cells when performing a disturb test under the same conditions. [Structure] Redundant regions 5 and 6 having the same relationship between the inverted bit and the non-inverted bit with respect to the word line in each of the memory cell regions 1 and 2 are individually allocated to prevent defects. A word line having an arrangement equal to the arrangement of inverted bits and non-inverted bits in which selection terminals are coupled to the word line to be repaired is used as the word line assigned to the relief of the word line to be repaired. select.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic intersection random access random access memory (hereinafter referred to as DRAM).
And a semiconductor integrated circuit having memory cells that are non-inverted bits such as (1) and (2).

[0002]

2. Description of the Related Art In a semiconductor memory, a large number of complementary data line pairs coupled to input / output terminals of matrix-arranged memory cells are regularly arranged with a minimum interval, and an insulating film is provided between the data lines. Intervened. Therefore,
Capacitive coupling occurs between adjacent data lines, and a negative desired capacitance component is parasitic. As an example of a document describing a technique for preventing an undesired change in a read signal of a data line by such a coupling capacitance,
1989 I / E / E International Solid State Circuits Conference, FAM 16.4A 60ns 3.3V 1
6 Megabit Drum (1989 IEEE IN
TERNATIONAL SOLID-STATE C
IRCUITS CONFERENCE; FAM1
6.4 A60 ns 3.3 V DRAM), and the description of Japanese Patent Application No. 1-65841. The technique described in the former document is intended for a DRAM, and employs a twisted structure of complementary data lines in which the mutual arrangement of paired complementary data lines is alternately switched on the way, and each data line is read by a word line selection operation. An attempt is made to prevent signals from interfering with each other between adjacent data lines and changing undesirably.

In the DRAM adopting the data line twist structure as described above, a plurality of complementary data line pairs having a twist structure in which the mutual arrangement of the inverted data lines and the non-inverted data lines are alternately switched on the way are arranged, A memory cell as an inverted bit in which a data input / output terminal is coupled to the inverted data line of the complementary data line pair and a memory as a non-inverted bit in which a data input / output terminal is coupled to the non-inverted data line of the complementary data line pair. A single cell or a plurality of cells are regularly provided along the complementary data line pairs, and in the direction orthogonal to the complementary data line pairs, a selection terminal of a memory cell as a corresponding inversion bit and a non-inversion bit. A plurality of word lines coupled to each other are arranged, for receiving the initial potential in the complementary data line pair and the read potential from the memory cell and performing differential amplification. Nsuanpu is provided in the complementary data line pairs each, also, the main amplifier for writing data to a memory cell is provided by driving the complementary data line pair to a complementary level.

For example, in FIG. 7 showing a part of a memory cell array in a 16-megabit DRAM, a complementary data line pair formed by a non-inverted data line DL and an inverted data line DL * has a non-inverted bit indicated by a circle. A memory cell and a data input / output terminal of a memory cell as an inversion bit indicated by ● are regularly connected, and a word line to which a selection terminal of a corresponding memory cell is connected is arranged in the vertical direction. In the figure, selection of A mat and B mat is switched by a specific address bit. At this time,
As is apparent from FIG. 7, the arrangements of the inverted bit and the non-inverted bit connected to the respective word lines are different between the A mat and the B mat. At this time, the redundant mat for relieving the defective memory cell of the A mat or the B mat is configured with the same arrangement as the arrangement of the inversion bit and the non-inversion bit in one B mat. That is, the redundant mat in which the arrangement of the inverted bit and the non-inverted bit is one type is
This is also used for mats in which the arrangement of inverted bits and non-inverted bits is different.

In the device test in such a DRAM, the influence of the adjacent memory cell on the target memory cell,
Alternatively, a disturb test for examining the influence from the adjacent word line or data line is also performed. In the disturb test, the positional relationship between the memory cell of interest, the adjacent memory cell, the adjacent word line and the data front line is an important factor. In the semiconductor memory device, the physical arrangement of internal memory cells does not necessarily match the position indicated by the X and Y values even if externally applied X and Y addresses due to the relationship with the internal decoder configuration. There is. Therefore, a scrambler for converting an address generated by the test pattern generator into an address corresponding to a physical position of the memory under test is used.

[0006]

However, in the configuration as shown in FIG. 7, when the defective portion of the A mat is repaired by the redundant mat, the logic of the scrambler is violated in the relationship between the inverted bit and the non-inverted bit. It was revealed by the present inventor that various reverse reliefs are caused. That is, when the defective portion E2 of the B mat is repaired by the redundant mat, the arrangement relationship between the inverted bit and the non-inverted bit in each of the defective portion E2 and the redundant mat is the same. Therefore, the interference between adjacent memory cells can be accurately evaluated in the disturb test, even in the portion repaired by the redundant mat in substantially the same manner as in the DRAM in which the redundant mat is not repaired. On the other hand, when the defective portion E1 of the A mat is repaired by the redundant mat, the arrangement relationship between the inverted bit and the non-inverted bit in each of the defective portion E1 and the redundant mat is different. Therefore, if the disturb test is performed on the portion repaired by the redundant mat with the same test pattern and scrambler as the DRAM that is not redundant repaired, the interference between adjacent memory cells can be accurately evaluated. Can not. For example, if the memory cell of interest in the disturb test is MC1
Then, one memory cell MC2 adjacent to this is a non-inverted bit, but in the case where the defective portion E1 is repaired by a redundant mat, the memory cell MCR2 adjacent to the memory cell MCR1 corresponding to the memory cell MC1 is inverted. The data charge of the memory cell MCR2 is different from that of the memory cell MC2. Therefore, the charge holding state of the adjacent memory cell in the memory cell MCR1 is
The redundancy-repaired DRAM, which is different from the charge holding state of the adjacent memory cell in the memory cell MC1, is non-relieved DRA.
The disturb test cannot be reliably performed under the same conditions as M, in other words, using the same test pattern and scrambler as each other.

An object of the present invention is to provide a semiconductor integrated device capable of preventing reverse repair from occurring in a relationship between an inverted bit and a non-inverted bit between a defect repaired by a redundant configuration and a defect not repaired. To provide a circuit. Another object of the present invention is to make it possible to reliably perform a disturb test on a redundant repaired semiconductor integrated circuit by using the same test pattern and scrambler as the non-repaired semiconductor integrated circuit, and An object of the present invention is to provide a semiconductor integrated circuit capable of accurately evaluating the influence of interference between cells.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of complementary data line pairs having a twist structure in which the mutual arrangement of the inverted data lines and the non-inverted data lines are alternately switched on the way are arranged, and data is input to the inverted data lines of these complementary data line pairs. A memory cell as an inversion bit to which an output terminal is connected and a memory cell as a non-inversion bit to which a data input / output terminal is connected to the non-inversion data line of the complementary data line pair are regularly arranged every one or more. A plurality of word lines, which are provided along the complementary data line pair and to which the selection terminals of the memory cells as the corresponding inversion bit and the corresponding non-inversion bit are coupled, are arranged in a direction orthogonal to the complementary data line pair, An amplifier circuit for receiving the initial potential of the complementary data line pair and the read potential from the memory cell for differential amplification, and driving the complementary data line pair to complementary levels. In a semiconductor integrated circuit including an amplifier circuit for writing data to a memory cell, the arrangement is the same as that of an inverted bit and a non-inverted bit in which a select terminal is coupled to a word line to be repaired for a defect. A redundant word line selecting means is used to select the word line having the arrangement as the word line assigned to the repair of the word line to be repaired. As the memory cell array configuration at this time, whether the memory cell to be selected by the address signal is the above-mentioned inverted bit or non-inverted bit depends on whether a predetermined address bit included in the address signal for selecting the memory cell A plurality of memory cell regions, which are mutually changed according to a logical value, are provided in a region in which a large number of the inverted bits and non-inverted bits are arranged, and each memory cell region has an inverted bit for a word line in it. And a non-inverted bit and a redundant area having the same relation as the non-inverted bit are individually assigned.

[0011]

According to the above-mentioned means, redundant regions having the same relation between the inverted bit and the non-inverted bit with respect to the word line in each memory cell region are individually assigned to each memory cell region to prevent defects. A word line having an arrangement equal to the arrangement of inverted bits and non-inverted bits in which selection terminals are coupled to the word line to be repaired is assigned to the above-mentioned word line to be repaired. Is selected, the reverse repair is prevented from occurring in the relationship between the inverted bit and the non-inverted bit between the defect repaired with the redundant configuration and the defect not repaired, and the redundant repair is performed. When a disturb test is performed on a semiconductor integrated circuit using the same test pattern and scrambler as the non-relief semiconductor integrated circuit, the influence of interference between adjacent memory cells Accurately assess possible to be.

[0012]

FIG. 2 shows a DRAM according to an embodiment of the present invention. Although not particularly limited, the DRAM shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 2, MCA is a memory cell array in which dynamic memory cells are arranged in a matrix. If there is a defective bit in the memory cell array MCA, the repaired normal array RGA to be repaired
And a redundant array RDA as a spare element for repairing a defective bit included in the regular array RGA.

The memory cells included in the normal array RGA have select terminals for each row of the normal word lines WRG0 to WRG.
The memory cells included in the redundant array RDA are commonly connected to the redundant word lines WRD0 to WRDm.

The normal word lines WRG0 to WRGn and the redundant word lines WRD0 to WRDm are not particularly limited, but any one of them is driven to the selection level via the word driver WDRV. Although not particularly limited, the selection of the regular word lines WRG0 to WRGn is
The redundant word lines WRD0 to WRDm are selected by the output selection signal of the row address decoder RADEC.
This is performed by the output signal of the redundant program circuit RDP, the details of which will be described later. Row address decoder RAD
A row address buffer RAB for inputting an external address signal RADDR is input to the EC and the redundant program circuit RDP.
Complementary level internal row address signals BXi, BXi * output from the UF (in the present specification, the symbol * means that the signal is not inverted and the symbol is an inverted signal. It means that the attached signal is a low active signal), or a refresh address output from a refresh counter (not shown) is selectively supplied.

The memory cells included in the memory cell array MCA have their data input / output terminals coupled to the data line pairs DL0, DL0 * to DLn, DLn * for each column. In this specification, a data line with a symbol * such as DL0 * is an inverted data line, and a data line without a symbol * is a non-inverted data line. Data line pair DL
0, DL0 * to DLn, DLn * are respectively coupled to the input / output terminals of the sense amplifier and the precharge circuit (the sense amplifier and the precharge circuit are included in the sense amplifier row and the precharge circuit row SPA) on the one hand, and the other on the other hand. , The column address decoder CADEC is coupled to the common data line pair CDL, CDL * via the column switch circuit CSW which is switch-controlled. The column address decoder CADEC has a column address buffer CAB for inputting an external column address signal CADDDR.
Internal address signals of complementary levels are supplied from UF.

The common data line pair CDL, CDL * is
Data output buffer DOBU via main amplifier MA
F and the data input buffer DIBUF. The output terminal of the data output buffer DOBUF and the input terminal of the data input buffer DIBUF are connected to one representative external data input / output terminal 20.

In FIG. 2, CONT is a row address strobe signal RAS *, which is supplied as an external signal.
Column address strobe signal CAS *, write
It is a control circuit that determines an internal operation mode based on an enable signal WE * and the like and forms various internal control signals according to the internal operation mode.

The basic internal control operation by the control circuit CONT is not particularly limited, but is as follows.
That is, when the chip is selected, first, the normal word lines WRG0 to WRGn and the redundant word lines WRD0 to WR are formed.
Dm is once controlled to the non-selection level, and the sense amplifier is correspondingly deactivated. The precharge circuit is operated in synchronization with this timing, whereby each data line pair DL0, DL0 * to DLn, DLn.
* Is precharged to a predetermined level. After that, the normal word lines WRG0 to WRGn and the redundant word lines WRD0 to WRD are formed.
A predetermined one of RDm is driven to the selection level according to the internal row address signal, and then the sense amplifier is made operable. After the operation of the sense amplifier, the column switch circuit CSW is selectively operated according to the internal column address signal, and in response to the operation, a predetermined data line pair is conducted to the common data line pair and connected to the data input buffer DIBUF or the data output buffer DOBUF. To be done. As a result, in the memory read operation, the selected memory cell data is read out, and in the memory write operation, the data is written in the selected memory cell.

The redundancy program circuit RDP is not particularly limited, but the address of the memory cell to be relieved is programmed, and the redundancy address judgment circuit section for comparing the programmed address with the address for memory access, and the redundancy. It is composed of a decoding circuit section for decoding the output of the address judging circuit section. Control of whether or not the redundant program circuit RDP is operable is performed by a control signal (redundancy enable signal) φren output from the redundancy enable circuit RDE. The redundancy enable circuit RDE includes, for example, a laser blow fuse (not shown) and is in a non-blown state in the initial state. In this state, control signal φren is set to the low level for inactivating or disabling redundant program circuit RDP. When repairing defects by redundancy,
The fuse is blown after the wafer probe test. As a result, the control signal φren is set to the high level,
The redundant program circuit RDP is activated or enabled.

The redundant address determination circuit section is not particularly limited, but stores an address programmed by a laser-fusible fuse for programming a predetermined address to be repaired corresponding to an internal row address signal and an input address. Compare. The comparison result is given to the decoding circuit section, and the decoding circuit section decodes it to set a predetermined one of the selection signals XR0 to XRm for selecting the redundant word lines WRD0 to WRDm. . At this time, if the comparison result in the redundant address determination circuit section is in agreement, the operation of the row address decoder RADEC is prohibited by the control signal φinh.

In FIG. 2, reference numeral 30 is a redundancy repair determination circuit. This redundancy repair determination circuit 30 is a circuit for externally determining that it is a repaired product when the redundancy enable circuit RDE and the redundancy program circuit RDP repair the circuit defect by an individual fuse blowing program. Therefore, according to the present embodiment, when a predetermined high voltage is applied to the external data input / output terminal 20, a current change corresponding to the presence or absence of redundancy relief is caused in the terminal 20 and the redundancy relief is performed. It is possible to externally determine whether or not there is.

FIG. 3 is a circuit diagram showing an example of the memory cell array MCA and its peripheral circuit block. In FIG. 3, the MOSFET having an arrow on the channel (back gate) portion is a P-channel MOSFET and is displayed separately from the N-channel MOSFET without the arrow.

Although not particularly limited, the memory cell array MCA is of a two-intersection (folded-back data line) system, and typically two sets of complementary data line pairs DLi, DLi * and DLj, DLj * are shown in the horizontal direction in the figure. And word lines WRG0 to WRDm are provided in a direction intersecting with each other, and a plurality of memory cells are arranged at the intersections of the complementary data line pairs and the word lines.

Each memory cell of the memory cell array MCA is a so-called 1-element type dynamic memory cell, and is composed of an information storage capacitor (hereinafter also simply referred to as storage capacitor) Cs and an address selection MOSFET Qm. Address-selecting MOSFETQ of memory cells arranged in the same column of the memory cell array MCA
The drain of m has a predetermined regularity, for example, 2 with respect to the non-inverted data line or the inverted data line of the corresponding complementary data line pair.
Every other pieces are joined alternately. In addition, the memory cell array M
The gates of the address selecting MOSFETs Qm of the memory cells arranged in the same row of CA are the corresponding word lines WR.
Commonly coupled to G0 to WRDm, respectively. A predetermined cell plate voltage VPL is commonly supplied to the other electrode of the information storage capacitor Cs of each memory cell, that is, the cell plate.

A large number of the complementary data line pairs are regularly arranged with a minimum distance, an insulating film is interposed between the data lines, and a capacitive coupling is generated between adjacent data lines, which is negatively desired. Parasitic components. In order to prevent the read signal of the data line from undesirably changing due to such coupling capacitance, a twisted structure of complementary data lines in which the mutual arrangement of the complementary data lines forming a pair is alternately replaced on the way is adopted. ing. As a result, it is possible to prevent the signals read on the respective data lines from being influenced by the data lines adjacent to each other by the word line selection operation and undesirably changing. In other words, the noise margin of the sense amplifier is improved. Although not shown in detail, the twist positions of the complementary data line pairs adjacent to each other are
They are offset from each other by a distance that is approximately half the unit distance from twisted portion to twisted portion.

The complementary data lines Di, Di *, Dj, Dj * constituting the memory cell array MCA are each provided with an N-channel type equalizing MOSFET Q1 and a power supply voltage V
N-channel type precharge MOSFETs Q2 and Q3 for supplying a level HVC that is half the level of cc are coupled to each other, thereby forming a precharge circuit. The operation of the precharge circuit is controlled by the timing signal φpcg, and the timing signal φpcg is set to the high level during the chip non-selection period, so that Di, D
All complementary data lines represented by i *, Dj, and Dj * are precharged to a level of about half the high-level side power supply voltage such as 5V.

Each complementary data line Di, Di *, Dj, Dj * forming the memory cell array MCA is
A CMOS static latch type sense amplifier composed of MOSFETs Q6 to Q9 is provided, and amplifies a minute potential difference of the data line to which the charges are redistributed according to the amount of accumulated charges of the selected memory cell. The P-channel type MOSFETs Q6 and Q7 forming the sense amplifier are arranged on the left side of the memory cell array MCA, and the N-channel type MO
The SFETs Q8 and Q9 are arranged on the right side of the memory cell array MCA, and the element isolation regions required when arranging MOSFETs having different conductivity types adjacent to each other are not necessary and the chip area is reduced. The MOSFET Q
Source electrodes of 6 and Q7 are commonly connected to a common source line CSLp, and P-channel type power switch MOSFET
Connected to the power supply terminal Vdd via Q10, and
The source electrodes of the SFETs Q8 and Q9 are the common source line CS
N-channel power switch M commonly connected to Ln
It is connected to the power supply terminal Vss through the OSFET Q11. The power supply terminal Vdd is supplied with a high-level power supply voltage such as 5V, and the power supply terminal Vss is supplied with a low-level power supply voltage such as a ground potential. Switch control signal φs of the power switch MOSFETs Q10 and Q11
a and φsa * are set to high level and low level at the time when the minute read signal output from the memory cell coupled to the selected word line in the DRAM chip selection state is established in the corresponding complementary data line. Then, they are activated all at once and are in an operating state. In the operating state, the sense amplifier amplifies a minute potential difference read from the memory cell coupled to the selected word line to the complementary data line to generate a high level or low level binary read signal. These binary read signals are rewritten to the corresponding memory cells to refresh the stored data when the DRAM is in the read mode or refresh cycle.

In FIG. 3, Q20 is the common source lines CSLp and CSL in the standby state of the DRAM.
It is an N-channel short MOSFET for selectively conducting n and n. Further, Q21 and Q22 are turned on in response to the on operation of the short MOSFET Q20, so that the common source lines CSLp and CSLn are
It is an N-channel type precharge MOSFET for giving a level HVC which is half the power supply voltage. These MOS
The FETs Q20, Q21, Q22 are also switch-controlled by the precharge signal φpcg. In the standby state of the DRAM, the power switch MOSFET Q1
0 and Q11 are cut off, and the complementary data lines are precharged to the level HVC which is about half the high level side power supply voltage.
TQ20 and precharge MOSFETs Q21 and Q22
Of the common source lines CSLp, CSL of both
Similarly to the complementary data line, n is also set to the level HVC which is about half the power supply voltage on the high level side, whereby the operation of the sense amplifier is completely stopped in the standby state.

Each complementary data line pair is commonly connected to a complementary common data line pair CDL, CDL * via column switch MOSFETs Qi, Qj.

FIG. 1 shows an example of an arrangement state of non-inverted bits (memory cells indicated by ◯) and inverted bits (memory cells indicated by ●) in the memory cell array MCA. The normal array RGA in the memory cell array MCA is divided into two memory cell areas, A mat 1 and B mat 2, although not particularly limited. Similarly, the redundant array RDA is not particularly limited, but a redundant mat on the A mat 1 side. 5 and the redundant mat 6 on the B mat 2 side are divided into two memory cell regions. The A-mat 1 and the B-mat 2 differ from each other in the arrangement configuration of the inverted bit and the non-inverted bit in which the select terminal is coupled to the word line, due to the data line twist structure in the middle thereof. In other words, the above A
Mat 1 and B mat 2 indicate whether a memory cell to be selected by an address signal is the above-mentioned inverted bit or non-inverted bit, which is included in the address signal for selecting the memory cell. It is positioned as a memory cell area which is changed depending on the logical value of the address bit Axi. That is, if the predetermined 1 bit Axi of the address signal is "0", the memory cell of A mat 1 is selected, and if it is "1", B is selected.
That is, the memory cell of the mat 2 is selected.
The redundant mat 5 on the A mat 1 side is a redundant area having the same relationship between the inverted bit and the non-inverted bit with respect to the word line in the A mat 1, and the redundant mat 6 on the B mat 2 side is , B-mat 2 is a redundant area having a relationship equal to the relationship between the inverted bit and the non-inverted bit with respect to the word line. The relationship between the redundant mats 5 and 6 is realized by applying a data line twist at a position indicated by DT in the middle thereof.

With respect to the structure of the memory cell array MCA, the redundant mat 5 is assigned to the defect relief of the A mat 1 and the redundant mat 6 is assigned to the defect relief of the B mat 2. Such allocation control is realized by the redundant program circuit RDP described with reference to FIG. In other words, the redundant program circuit RDP uses the word line having the same arrangement as the arrangement of the inverted bit and the non-inverted bit in which the selection terminals are coupled to the word line to be repaired for the defect. This is a redundant word line selection means for selecting a word line assigned to the repair of the word line to be repaired. For example, specifically, the redundant program circuit RD
In a program circuit using a fuse or the like for programming an address to be relieved to select a word line included in the redundant mat 5 in P, the address bit (Axi) is fixed to the "0" state. It is in a non-programmable state. That is, the program link like the other address bits is not provided for the address bit (Axi). Similarly, in the program circuit using a fuse or the like for programming an address to be relieved to select the word line included in the redundant mat 6 in the redundant program circuit RDP, the address bit (Axi) is used.
Is fixed to the "1" state, and the program link like the other address bits is not provided for the address bit (Axi).

In the configuration shown in FIG. 1, the A mat 1
The defective portion of B mat 2 is repaired by the redundant mat 5, and the defective portion of B mat 2 is repaired by the redundant mat 6.
There is no reverse relief that goes against the scrambler logic in the relationship between the inverted and non-inverted bits. For example, the defective portion E2 of the B mat 2 is replaced by the redundant mat 6
In the case of repairing by (1), the arrangement relationship between the inverted bit and the non-inverted bit in each of the defective portion E2 and the redundant mat 6 is the same. Similarly, the defective portion E1 of the A mat 1
When the redundant mat 5 is repaired, the arrangement relationship between the inverted bit and the non-inverted bit in each of the defective portion E1 and the redundant mat 5 is the same. Therefore, DRA
The interference between adjacent memory cells can be accurately evaluated in the disturb test performed as a part of the device test of M even in the part repaired by the redundant mat in substantially the same manner as in the DRAM without redundant repair. You can For example, if the memory cell of interest in the disturb test is MC1
In this case, one memory cell MC2 adjacent to this is a non-inverted bit, and the memory cell MCR2 adjacent to the memory cell MCR1 corresponding to the memory cell MC1 in the defective portion E1 repaired by the redundant mat 5 is also the same. It is a non-inverted bit, and the accumulated charge of the memory cell MCR2 is the same as that of the memory cell MC2.
The accumulated charge state of the adjacent memory cell in R1 is not different from the accumulated charge state of the adjacent memory cell in memory cell MC1. The same applies to the defective portion E2 and the redundant mat 6 for repairing the defective portion E2. Therefore, the redundant repaired DRAM can be reliably subjected to the disturb test under the same condition as the non-repaired DRAM, in other words, by using the same test pattern and scrambler. This makes it possible to accurately and efficiently evaluate the influence of the interference between the adjacent memory cells in the DRAM regardless of the presence or absence of the redundancy repair.

FIG. 4 shows an example in which the redundant mat 5 on the A mat 1 side is adjacent to the A mat 1 and the redundant mat 6 on the B mat 2 side is adjacent to the B mat 2 with respect to FIG. In this case, the layout is such that the redundant mats 5 and 4 are separated left and right, but it is not necessary to apply the data line twist at the position indicated by DT in FIG. Even in such a memory cell array structure, the same effect as that of FIG. 1 can be obtained.

FIG. 5 shows an example of a memory cell array structure when the number of mats is four. In the figure, the regular array RGA has an A mat 1, a B mat 2, a C mat 3 and a D mat 4, and redundant mats 5 to 8 assigned to the respective mats are arranged in the redundant array RDA. .
The configuration of FIG. 5 is such that the number of mat divisions is expanded from that of FIG. 1, and the redundant mat 4 is assigned to the defect relief of the A mat 1 and the redundant mat 6 is assigned to the defect relief of the B mat 2. The redundant mat 7 is assigned to the defect relief of the C mat 3 and the redundant mat 8 is assigned to the defect relief of the D mat 4.
Is assigned, and the reverse repair can be prevented in the same manner as above.

In FIG. 6, redundant mats 5 to 8 corresponding to the mats 1 to 4 are arranged adjacent to the individual mats as compared with FIG. In this case, the layout is such that the redundant mats 5 to 8 are scattered, but it is not necessary to perform the data line twist at the position indicated by DT in FIG. Even in such a memory cell array structure, the same effect as the above can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes. For example,
The number of divisions of the mat and the redundant mat is not limited to the above-mentioned embodiment, and is appropriately determined depending on the location and the number of the data line twist.

In the above description, the invention made by the present inventor is the field of application behind the invention.
However, the present invention is not limited to this, and a memory LSI such as a pseudo static RAM is described.
The present invention can be widely applied to semiconductor integrated circuits such as a logic LSI such as a microcomputer in which a DRAM, a DRAM and the like are mounted on a chip. The present invention can be widely applied to the condition that the twist structure is adopted for at least the complementary data line pair to which the non-inverted bit and the inverted bit are coupled.

[0039]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, each memory cell area is individually assigned with a redundancy area having a relationship equal to the relationship between the inverted bit and the non-inverted bit with respect to the word line in the memory cell area, and the defect is repaired. By selecting a word line having the same arrangement as the arrangement of the inverted bit and the non-inverted bit in which the selection terminals are coupled to the word line to be repaired, as the word line assigned to the repair of the word line to be repaired. It is possible to prevent the reverse repair from occurring in the relationship between the inverted bit and the non-inverted bit between the defect repaired and the defect not repaired with a redundant configuration. This makes it possible to accurately evaluate the effect of interference between adjacent memory cells even when performing a disturb test on a redundantly repaired semiconductor integrated circuit using the same test pattern and scrambler as the non-repaired semiconductor integrated circuit. it can. Further, by this, it is possible to facilitate the efficiency of the disturb test and guarantee the quality of the semiconductor integrated circuit repaired by the redundant configuration to be equal to that of the non-repair product.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of an array state of non-inverted bits and inverted bits in a memory cell array of a DRAM according to an embodiment of the present invention.

FIG. 2 is a block diagram generally showing a DRAM according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of the memory cell array of FIG. 2 and its peripheral circuit block.

FIG. 4 is a configuration explanatory view of a memory cell array in which a redundant mat is arranged adjacent to each mat as compared with FIG.

FIG. 5 is an explanatory diagram of a memory cell array configuration when the number of mats is four.

FIG. 6 is a diagram illustrating the configuration of a memory cell array in which a redundant mat is arranged adjacent to each mat in FIG.

FIG. 7 is a diagram for explaining the inconvenience in the disturb test due to the reverse repair of the inverted bit and the non-inverted bit.

[Explanation of symbols]

 1 A mat 2 B mat 3 C mat 4 D mat 5 A mat side redundant mat 6 B mat side redundant mat 7 C mat side redundant mat 8 D mat side redundant mat MCA memory cell array RGA regular array RDA redundant array WRG0 ~ WRGn Normal word line WRD0 ~ WRDm Redundant word line RDP Redundant program circuit DL0, DL0 * ~ DLn, DLn * Complementary data line pair ● Inverted bit ○ Non-inverted bit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeo Kizaki 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Hiritsu Cho El SII Engineering Co., Ltd. (72) Inventor Mitsuo Kawamoto Mobara, Chiba Prefecture 3681, Hayano Ichi, Hitachi Device Engineering Co., Ltd. (72) Inventor Masahiro Oyamada 5-20-1, Kamisuihonmachi, Kodaira-shi, Tokyo Hiratsuru ELS Engineering Co., Ltd. (72) Inventor Hiroshi Suzuki 3681 Hayano, Mobara-shi, Chiba Prefecture Hitachi Device Engineering Co., Ltd.

Claims (3)

[Claims] 1. A plurality of complementary data line pairs having a twist structure in which the mutual arrangement of the inverted data lines and the non-inverted data lines are alternately switched on the way, and data is input to the inverted data lines of the complementary data line pairs. A memory cell as an inversion bit to which an output terminal is connected and a memory cell as a non-inversion bit to which a data input / output terminal is connected to the non-inversion data line of the complementary data line pair are regularly arranged every one or more. A plurality of word lines, which are provided along the complementary data line pair and to which the selection terminals of the memory cells as the corresponding inversion bit and the corresponding non-inversion bit are coupled, are arranged in a direction orthogonal to the complementary data line pair, An amplifier circuit for receiving the initial potential of the complementary data line pair and the read potential from the memory cell for differential amplification, and driving the complementary data line pair to a complementary level for memory. In a semiconductor integrated circuit having an amplifier circuit for writing data in a cell, an arrangement equal to that of inverted bits and non-inverted bits in which a select terminal is coupled to a word line to be repaired for a defect is arranged. A semiconductor integrated circuit, comprising: a redundant word line selecting means for selecting the held word line as a word line assigned to the repair of the word line to be repaired. 2. Whether the memory cell to be selected by the address signal is the inverted bit or the non-inverted bit depends on the logical value of a predetermined address bit included in the address signal for selecting the memory cell. Has a plurality of memory cell areas that are mutually changed in the area where a large number of the above-mentioned inverted bits and non-inverted bits are arranged, and each memory cell area has an inverted bit and a non-inverted bit for the word line in it. 2. The semiconductor integrated circuit according to claim 1, wherein redundant regions having the same relationship with the above are individually allocated. 3. The semiconductor integrated circuit according to claim 1, wherein the memory cell is a dynamic memory cell.