JPH06314929A - Direct digital system synthesizer - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a wide band, high precision, and miniaturization of the output frequency of a direct digital synthesizer. [Structure] Output clock f _CLK of reference oscillation circuit 1 is 1 /
Provided with a counter 2 which divides the frequency into 2 and 1/4 and outputs it, the phase step information Δθ is multiplied by 4 and a numerically controlled oscillator (NCO) is provided.
Input to 6 and integrate according to the timing of f _CLK / 4,
The remainder Σ4 · Δθ divided by 2π is output. The 4-phase parallel arithmetic circuit 8 adds -Δθ, Δθ, 2 · Δθ in parallel to Σ4 · Δθ, extracts phase information at the timing of f _CLK / 4, causes the switching circuit 9 to output ΣΔθ, and causes the register 10 to output the phase information θ. Configured to obtain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a direct digital synthesizer used in communication equipment.

[0002]

2. Description of the Related Art A phase locked loop (PLL) structure is widely used as a basic structure for a frequency synthesizer for obtaining a highly accurate output frequency. The PLL configuration has a great advantage in terms of circuit scale and frequency accuracy that an output frequency phase-locked with a high-accuracy reference oscillation source using a crystal oscillator can be obtained with a relatively small-scale circuit. However, since the PLL configuration is a negative feedback control loop, there is a reciprocal relationship between the signal-to-noise ratio (C / N) of the frequency synthesizer output and the response speed of the loop. Therefore, TDM (Time Division Multi)
plex) communication, frequency hopping communication, etc., it is necessary to perform high-speed frequency switching for each short burst section, and if the response speed of the frequency switching operation is increased, the system band becomes wider and the output C There is a problem that / N decreases.

One of the methods for solving this problem is a direct digital synthesizer (Direct Digital).
There is a DDS type high speed synthesizer using Synthesizer (DDS). The DDS high-speed synthesizer is a DDS
Since the circuit does not have a feedback loop unlike the PLL configuration, the frequency switching time can be shortened. Figure 7
FIG. 3 is a block diagram of a conventionally used DDS circuit. In the figure, 101 is a reference oscillation circuit that outputs a reference clock f _CLK , 102 is a register that outputs phase step information Δθ according to the timing of f _CLK , and 103 is Δθ that is fθ.
Numerically controlled oscillator (Numer) that outputs phase information θ by integrating modulo 2 ^N (N is a natural number) according to the _CLK timing.
ical Controlled Oscillator (NCO), 104 and 105 are 1 cycle (0) of the cosine waveform and the sine waveform which are stored in advance using the output value θ of the NCO as an address.
ROM, 106 and 107, each of which can sequentially read amplitude data of (° to 360 °) are ROM 104.
And a D / A converter for converting the output value of the ROM 105 into an analog voltage signal, and 108 and 109 respectively D / A
It is a low pass filter (LPF) that removes harmonic components contained in the outputs of the converter 106 and the D / A converter 107 and outputs a desired signal.

In the above structure, the oscillation frequency f _DDS by the DDS circuit is represented by a mathematical expression. First, f _DDS and its period T _DDS have the following relationship.

[0005]

[Equation 1] Further, the cycle T _NCO of the _NCO 103 can be expressed by the following equation.

[0006]

[Equation 2] Here, since the ROM 104 and the ROM 105 output the amplitude data for one cycle of f _DDS at the cycle T _NCO of the _NCO , the following equation is established. T _NCO = T _DDS [sec] (3) From equations (1), (2), and (3), the relationship between f _DDS and f _CLK is as follows.

[0007]

[Equation 3] From the equation (4), it is understood that the reference clock f _CLK can be speeded up in order to increase the oscillation frequency f _DDS of the DDS circuit and widen the band.

[0008]

However, the NCO
Reference numeral 103 denotes a negative feedback configuration, and the reference clock f _CLK
Since the calculation processing is performed in, there is a limit in increasing the speed of f _CLK . Further, if the value of N in the equation (4) is increased, the minimum step frequency can be set smaller, and a highly accurate signal can be obtained, but the circuit scale of the NCO 103 increases and f
Similar to the case of increasing the speed of _CLK , the calculation processing time of the NCO 103 is limited. Therefore, in the conventional configuration, it is difficult to make the output frequency f _DDS wider and more accurate.

The present invention provides a direct digital synthesizer suitable for miniaturization and IC implementation by eliminating the problem of NCO operation processing speed due to the widening of the output frequency and the improvement of accuracy in the conventional configuration. The purpose is to

[0010]

A direct digital synthesizer according to the present invention comprises a reference oscillator circuit for outputting a reference clock f _CLK and a frequency divider for dividing the reference clock f _CLK to output f _CLK / 2 and f _CLK / 4. Counter, a first register that outputs externally set phase step information Δθ at the timing of the reference clock f _CLK , and the phase step information Δθ is multiplied by (−1) to output −Δθ {× (-1)} circuit, a circuit for multiplying the phase step information Δθ by 4 and outputting 4 · Δθ, and (× 4)
4) Output value 4 · Δθ of the circuit is output value f of the counter
A numerically controlled oscillator that integrates according to the timing of _CLK / 4 and outputs a remainder Σ4 · Δθ when divided by 2π (radian), and outputs 2 · Δθ by doubling the output value Δθ of the first register. (× 2) circuit and the above {× (−
1)} circuit output −Δθ, the numerically controlled oscillator output value Σ4 · Δθ, and the first register output value Δθ,
The output value 2 · Δθ of the (× 2) circuit is used as an input to perform parallel calculations Σ4 · Δθ−Δθ, Σ4 · Δθ, Σ4 ·
Four-phase parallel arithmetic circuit that outputs phase information of Δθ + Δθ, Σ4 · Δθ + 2 · Δθ, and phase information Σ4 · Δθ−Δθ, Σ4 · Δθ, Σ4 · Δθ that is the output of the four-phase parallel arithmetic circuit.
A first switching circuit that outputs + Δθ, Σ4 · Δθ + 2 · Δθ as ΣΔθ according to the timings of the outputs f _CLK / 2 and f _CLK / 4 of the counter, and the output value ΣΔθ of the first switching circuit is the reference clock. A second register that outputs phase information θ according to the timing of f _CLK , and the amplitude data of one cycle (0 ° to 360 °) of the cosine waveform stored in advance using the output value θ of the second register as an address. A first ROM that can be read and a second ROM that can read amplitude data of one cycle (0 ° to 360 °) of a sine waveform stored in advance using the output value θ of the second register as an address. And a first for converting the output from the first ROM into an analog voltage signal
The D / A converter, the second D / A converter for converting the output from the second ROM into an analog voltage signal, and the harmonic components of the output of the first D / A converter. First to remove
And a second low-pass filter that removes a harmonic component of the output of the second D / A converter.

Further, in the above direct digital synthesizer, the first ROM and the second R
A complement switching circuit for outputting OM according to the most significant bit of the output value θ of the second register as a value excluding the most significant bit of the output value θ or its complement as θ ′ (0 ≦ θ ′ ≦ π). And an output value θ ′ of the complement switching circuit as one input and a subtraction process with π / 2 (radian) as the other input, and an adder that outputs θ′−π / 2, and the complement switching A third ROM capable of sequentially reading amplitude data of a half cycle (0 ° to 180 °) of a cosine waveform stored in advance using the output value θ ′ of the circuit as an address, and the output value θ′−π of the adder. The second ROM is replaced with a fourth ROM capable of storing the same data as the third ROM and sequentially reading the same with // 2 as an address.

Further, in the above direct digital system synthesizer, the third ROM and the fourth R
A second switching circuit that inputs the output value θ ′ of the complement switching circuit and the output value θ′−π / 2 of the adder, and alternately outputs the OM according to the polarity of the reference clock f _CLK ; A fifth ROM capable of sequentially reading amplitude data of a half cycle (0 ° to 180 °) of a cosine waveform stored in advance using the output value of the second switching circuit as an address,
An output of the fifth ROM is replaced with a third switching circuit that switches an output destination at the same timing as the second switching circuit.

[0013]

【Example】

[Structure] FIG. 1 is a structural diagram showing a first embodiment of the present invention. In the figure, reference numeral 1 denotes a reference oscillation circuit, which outputs a reference clock f _CLK . Reference numeral 2 is a counter, which _{divides the} reference clock f _CLK and outputs f _CLK / 2 and f _CLK / 4. Reference numeral 3 denotes a register, which outputs an externally set phase increase amount step value (digital value) Δθ at the timing of the f _CLK . 4 is a {× (−1)} circuit, which multiplies the output value Δθ of the register 3 by (−1) to obtain −Δθ.
Is output. Since −Δθ can be represented by the two's complement of Δθ, the circuit can be easily configured by an inverting circuit and an adder. 5
Is a (× 4) circuit, which multiplies the output value Δθ of the register 3 by 4 and outputs 4 · Δθ. The circuit can be easily constructed by shift wiring to the upper side of 2 bits.

Reference numeral 6 denotes an NCO, which multiplies the output value 4 · Δθ of the (× 4) circuit 5 by modulo 2 ^M (M is a natural number) in accordance with the timing of f _CLK / 4 which is the output of the counter 2.
Outputs Σ4 · Δθ. The circuit can be easily configured with an adder and a register. Reference numeral 7 is a (× 2) circuit, which doubles the output Δθ of the register 3 and outputs 2 · Δθ. The circuit can be easily constructed by a shift wiring to the upper side of 1 bit. 8
Is a four-phase parallel arithmetic circuit, the output value of the {× (−1)} circuit −Δθ, the output value of the NCO 6 Σ4 · Δθ, the register 3
Output value Δθ of (x2) and the output value 2 × Δθ of the circuit 7 are input to perform parallel arithmetic processing, and the output of the counter 2 f _CLK /
Σ4 · Δθ−Δθ, Σ4 · Δ
θ, Σ4 · Δθ + Δθ, Σ4 · Δθ + 2 · Δθ are output. The circuit can be easily configured with an adder and a register.

A switching circuit 9 is a four-phase parallel arithmetic circuit 8
Output Σ4 · Δθ−Δθ, Σ4 · Δθ, Σ4 · Δθ + Δ
θ, Σ4 · Δθ + 2 · Δθ is the output of counter 2 f _CLK
ΣΔθ is sequentially switched and output according to the timing of / 2, f _CLK / 4. Reference numeral 10 is a register, which outputs the output value ΣΔθ of the switching circuit 9 as the phase information θ according to the timing of the reference clock f _CLK . 11 and 12 are RO
M (Read Only Memory), which is one cycle (0 ° to 360 °) of a cosine waveform and a sine waveform stored in advance.
The amplitude data of (°) is sequentially read using the output value θ of the register 10 as an address. Reference numerals 13 and 14 denote D / A converters, which convert the output values of the ROM 11 and ROM 12 into analog voltage signals and output them. 15 and 16 are LPF
And D / A converter 13 and D / A converter 14 respectively
Of harmonic components contained in the output of the LPF 15 and the cosine wave from the LPF 15; I = cos (Δθ · f _CLK · t), LPF 16
To sine wave; Q = sin (Δθ · f _CLK · t).

FIG. 4 is a block diagram showing the details of the four-phase parallel arithmetic circuit 8 shown in FIG. In the figure, 81, 82, and 83 are adders, and the output Σ4 · Δθ of the NCO 6 is used as one input, and the other input is -Δθ, Δθ, 2 respectively.
・ Addition operation is performed as Δθ, and Σ4 · Δθ−Δθ, Σ4 · Δ
Outputs θ + Δθ, Σ4 · Δθ + 2 · Δθ, respectively.
Reference numeral 84 denotes a register, which is the output of the adder 81 Σ4 · Δθ−
Δθ, NCO 6 output Σ4 · Δθ, adder 82 output Σ
4 · Δθ + Δθ, output of adder 83 Σ4 · Δθ + 2 · Δ
θ is output according to the timing of the clock f _CLK / 4 from the counter 2.

Next, FIG. 2 is a structural example view showing a second embodiment of the present invention. 1 to 10, 1 of the components of FIG.
3 to 16 are the same as in FIG. Reference numeral 17 is a complement switching circuit, and the most significant bit of the output value θ of the register 10 is input as a polarity bit C and controlled by the polarity bit C. C
It has a function of outputting the data excluding the most significant bit of θ when = "0" and the 1's complement value of the data when C = "1" as switching θ '. The same function can be easily configured by using an exclusive OR circuit. Reference numeral 18 denotes an adder, which uses the output value θ ′ (addition value) of the complement switching circuit 17 as one input and the π / 2 radian (subtraction value) as the other input to perform an addition operation (θ′−π / 2) is output. Reference numeral 11 'denotes a ROM, which sequentially reads amplitude data of a half cycle (0 to 180 °) of a cosine waveform stored in advance using the output value θ'of the complement switching circuit 17 as an address. 1
Reference numeral 2'denotes a ROM, and the same data as the ROM 11 'stored in advance is sequentially read using the output value (θ'-π / 2) of the adder 18 as an address.

Next, FIG. 3 is a structural example view showing a third embodiment of the present invention. 1 to 10, 1 of the components of FIG.
3-18 and 11 'are the same as in FIG. Reference numeral 19 denotes a switching circuit, which outputs the output value θ ′ of the complement switching circuit 17 and the adder 18
The output value (θ′−π / 2) of the input clock is used as an input value, and θ ′ when f _CLK = “1” depending on the polarity of the reference clock f _CLK.
When f _CLK = “0”, (θ′−π / 2) is alternately switched and output. Since θ ′ and (θ′−π / 2) are alternately input to the ROM 11 ′ by f _CLK , the ROM1
1 ′ alternately outputs waveform data for θ ′ and (θ′−π / 2). 20 is a switching circuit, which is the ROM 11 '
The output value of is distributed to cosine waveform data and sine waveform data and output at the same switching timing as the switching circuit 19.

(Operation) The operation of the configuration example shown in FIGS. 1 and 4 will be described with reference to FIG. FIG. 5 shows the NCO in FIG.
6 is a waveform diagram showing an example of temporal changes in the output value Σ4 · Δθ (dashed line) of 6 and the output value ΣΔθ (solid line) of the switching circuit 9. FIG.
Now, at time T ₀ , the output value of NCO 6 Σ4 · Δθ =
Set to 0. Thereafter, the NCO 6 continues to accumulate 4 · Δθ for each cycle (4 / f _CLK ) of the clock signal f _CLK / 4, and
As shown by the broken line, the number of steps increases stepwise in steps of 4.Δθ. Next, at time T ₁ , the value of Σ4 · Δθ is 2 ^M
When the above value is reached, the value of Σ4 · Δθ drops to the value obtained by subtracting 2 ^M due to the integration operation of modulo2 ^M , and again 4 · Δ
It rises in the step of θ, and the same operation as after time T ₀ is repeated. From the above operation, it can be seen that the output value of the NCO 6 exhibits a sawtooth waveform value.

[0020]

[Equation 4]

In FIG. 1, the switching circuit 9 has output values θ-Δθ, θ, θ + Δθ, θ + 2 of the preceding 4-phase parallel arithmetic circuit.
Δθ is sequentially switched and output according to the timing of f _CLK / 2 and f _CLK / 4. Therefore, as shown by the solid line in FIG. 5, ΣΔθ is equal to each cycle of the reference clock f _CLK (1 / f
_CLK ), and continues to accumulate Δθ, and outputs a sawtooth waveform value that rises stepwise in steps of Δθ, which is equivalent to the output waveform value of the conventional NCO 103 shown in FIG. Therefore, the direct digital synthesizer according to the present invention can operate the NCO at a speed of the integrated clock signal of the NCO which is ¼ of that of the integrated clock signal of the conventional NCO. That is, it can be said that this is equivalent to quadrupling the speed of the NCO. The output of the switching circuit 9 is output as θ from the register 10 at the timing of the reference clock f _CLK , and the phase information θ is used as an address to access the ROM 11 and the ROM 12 that store the cosine waveform data and the sine waveform data, respectively. Outputs digital values of cosine waveform and sine waveform, respectively. Further, the waveform shown in the following equation is obtained through the D / A converter 13, the D / A converter 14, the LPF 15, and the LPF 16, respectively. Cosine wave; I = cos (Δθ · f _CLK · t) …… (6) Sine wave; Q = sin (Δθ · f _CLK · t) …… (7)

Next, the second embodiment shown in FIG. 2 will be described with reference to FIG. To simplify the explanation,
Consider the case where M = 4, that is, the maximum value of the phase information θ output from the register 10 is 2 ^M −1 = 15. 6A shows the output waveform of the complement switching circuit 17, and FIG. 6B shows the adder 18
Output waveform of FIG. 6 (C) shows ROM11 ', ROM12'
Address-to-data relationship. Now, at time 0, the phase information θ = 0 which is the output value of the register 10 is set. The register 10 rises stepwise up to 2 ^M −1 = 15 as the time progresses in the order of 0 → 1 → 2 → 3 ..., and the value of θ becomes 2 ^M or more. Once reached, θ =
It descends to 0 and rises stepwise again. Here, focusing on the most significant bit (MSB) of θ, 0 ≦ θ ≦ 2 ^M−1 −1
It is clear that in the period is MSB = 1 in ^{MSB = 0,2 M-1 ≦ θ} ≦ 2 M -1 intervals. Therefore, the complement switching circuit 17 outputs the output value of the register 10 when MSB = 0 and the 1's complement value of θ when MSB = 1. Therefore, the output value θ ′ of the complement switching circuit 17 is shown in FIG.
As shown by the solid line in (A), a triangular staircase waveform that rises stepwise from time 0 to 7 and descends stepwise from time 8 to 15. From time 16 onward, the same operation as from time 0 to 15 is repeated.

Next, the adder 18 outputs (θ'-π / 2) radians. Since π / 2 radians can be represented by 2 ^M-2 -1, the output value of the adder 18 is (θ ' -2 ^M-2 -1)
Becomes Therefore, with respect to the output waveform of the complement switching circuit 17 shown by the broken line in FIG.
The triangular staircase waveform shown by the solid line in FIG. Figure 6
(C) is a diagram showing the relationship between the addresses of the ROM 11 'and the ROM 12' and the ROM 11 'and the ROM.
In 12 ', data corresponding to the amplitude of the cosine waveform is stored with the output value 0 to the maximum value 7 of the complement switching circuit 17 when M = 4 as an address. Therefore, FIG.
When the triangular staircase waveform value of the complement switching circuit 17 shown by the broken line in (B) is input to the ROM 11 'and accessed, the address is 0 → 1 → 2 → ... → 6 → 7 → 7 → 6 ... → 1 → 0 → 0
The data changes in the order of → 1 → ..., and the data forming the cosine waveform stored in advance in the ROM 11 'is read and output.

The adder 1 shown by the solid line in FIG.
When the triangular staircase waveform value of 8 is input to the ROM 12 ′ and accessed, the address is 3 → 2 → 1 → 0 → 0 → 1 → ...
→ 6 → 7 → 7 → 6 → ..., and the data forming the cosine waveform previously stored in the ROM 12 ′ is read and output. Here, the waveform output from the ROM 12 'is
The waveform has a phase delay of π / 2 from the waveform output from the ROM 11 ′. Therefore, it is clear that the output waveform of the ROM 12 'is a sine waveform. As shown in the above operation, the triangular staircase waveform is generated, and the ROM 11 ′ and the ROM are generated.
In the method of inputting and accessing the address 12 ', the data in the ROM 11' and the ROM 12 'can be amplitude data of a half cycle (0 ° to 180 °) of the waveform to be read. The outputs of the ROM 11 ′ and the ROM 12 ′ are converted into analog signals by the D / A converter 13 and the D / A converter 14, respectively, and the LPF 15 and the LPF, respectively.
The harmonics are removed at 16 and output as a complete cosine waveform or sine waveform.

Next, the operation of the configuration example diagram of the third embodiment of the present invention shown in FIG. 3 will be described. Complement switching circuit 17
Output value θ'and the output value of the adder 18 (θ'-π / 2)
Is input to the switching circuit 19 according to the timing of the reference clock f _CLK . The switching circuit 19 alternately outputs θ ′ when f _CLK = “1” and (θ′−π / 2) when f _CLK = “0”. The ROM 11 'has θ'and (θ'-π /
2) is alternately accessed with the address as an address, and the amplitude data corresponding to θ ′ and (θ′−π / 2) is alternately output. The output value of the ROM 11 ′ is input to the switching circuit 20 that performs switching operation at the same timing as the switching circuit 19, and f _CLK
= “1”, the amplitude data corresponding to θ ′ is f _CLK =
When the value is “0”, the amplitude data corresponding to (θ′−π / 2) is distributed and output. As shown in the above operation, it can be understood that the ROM can be shared by arranging the switching circuit that performs the switching operation at the same timing in the front stage and the rear stage of the ROM. The amplitude data corresponding to θ ′ is converted into an analog cosine waveform through the D / A converter 13 and the LPF 15, and the amplitude data corresponding to (θ′−π / 2) is D.
The sine waveform of the analog value is converted through the A / A converter 14 and the LPF 16 to obtain the waveforms shown in the equations (6) and (7) as in the first embodiment.

[0026]

As described in detail above, in the structure of the direct digital system synthesizer of the present invention, the integrating circuit of the negative feedback structure operates with a quarter of the clock signal of the conventional system, so that the output frequency Higher frequency, that is,
It is possible to widen the band and improve the accuracy of the set frequency. In addition, by devising the access method of ROM, R
The OM capacity can be reduced, contributing to miniaturization. Furthermore, since most of the circuits are logical operations, there is an advantage that they can be integrated into an IC, and that miniaturization, low power consumption, and cost reduction are easy.

[Brief description of drawings]

FIG. 1 is a configuration example diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration example diagram showing a second embodiment of the present invention.

FIG. 3 is a structural example diagram showing a third embodiment of the present invention.

FIG. 4 is a configuration example diagram of a four-phase parallel arithmetic circuit of FIG.

5 is a time chart of output values of an integrating circuit and a switching circuit of FIG.

FIG. 6 is an explanatory diagram of a time chart of output values of the complement switching circuit and the adder of FIG. 2 and address pair data of the ROM 11 ′ and ROM 12 ′.

FIG. 7 is a diagram showing a configuration example of a conventional direct digital synthesizer.

[Explanation of symbols]

 1 Reference Oscillation Circuit 2 Counter 3 Register 4 {× (-1)} Circuit 5 (× 4) Circuit 6 Accumulation Circuit 7 (× 2) Circuit 8 4-Phase Parallel Operation Circuit 9 Switching Circuit 10 Registers 11, 11 ′, 12, 12 'ROM 13, 14 D / A converter 15, 16 LPF 17 complement switching circuit 18 adder 19, 20 switching circuit 81, 82, 83 adder 84 register 101 reference oscillation circuit 102 register 103 integrating circuit 104, 105 ROM 106 , 107 D / A converter 108, 109 LPF

Claims (3)

[Claims] A reference oscillator for outputting a 1. A reference clock f _CLK, divides the reference clock _{f CLK f CLK / 2, f} CLK /
4, a first register that outputs externally set phase step information Δθ at the timing of the reference clock f _CLK , and the phase step information Δθ is multiplied by (−1) to output −Δθ. {× (−1)} circuit, a (× 4) circuit that multiplies the phase step information Δθ by 4 and outputs 4 · Δθ, and an output value 4 · Δθ of the (× 4) circuit Of the output value f _CLK / 4 of the numerical value controlled oscillator that outputs the remainder Σ4 · Δθ when divided by 2π (radian), and doubles the output value Δθ of the first register to 2 · A (× 2) circuit for outputting Δθ, an output of the {× (−1)} circuit −Δθ, an output value Σ4 · Δθ of the numerically controlled oscillator, an output value Δθ of the first register, and (× 2) Input the output value 2 · Δθ of the circuit and perform parallel operation Σ · Δθ-Δθ, Σ4 ·
A four-phase parallel arithmetic circuit that outputs phase information of Δθ, Σ4 · Δθ + Δθ, Σ4 · Δθ + 2 · Δθ, and phase information Σ4 · Δθ− that is the output of the four-phase parallel arithmetic circuit.
Δθ, Σ4 · Δθ, Σ4 · Δθ + Δθ, Σ4 · Δθ + 2
.DELTA..theta. Is the output of the counter _f.sub.CLK / 2, _f.sub.CLK / 4
A first switching circuit for outputting as ΣΔθ according to the timing of, and an output value ΣΔθ of the first switching circuit for the reference clock f.
_A second register that outputs phase information θ according to the timing of _CLK , and the amplitude value of one cycle (0 ° to 360 °) of the cosine waveform stored in advance is sequentially read using the output value θ of the second register as an address. And a second ROM capable of reading amplitude data of one cycle (0 ° to 360 °) of a sine waveform stored in advance using the output value θ of the second register as an address. A first D / A converter for converting the output from the first ROM into an analog voltage signal, and a second D / A conversion for converting the output from the second ROM into an analog voltage signal A first low-pass filter for removing harmonic components of the output of the first D / A converter, and a first low-pass filter for removing harmonic components of the output of the second D / A converter. Equipped with two low-pass filters, Direct digitally synthesizer characterized. 2. The direct digital synthesizer according to claim 1, wherein the first ROM and the second ROM are arranged according to a most significant bit of an output value θ of the second register,
A complement switching circuit that outputs the value excluding the most significant bit of the output value θ or its complement as θ ′ (0 ≦ θ ′ ≦ π), and the output value θ ′ of the complement switching circuit as one input, and π / 2
Perform subtraction processing using (radian) as the other input,
Using the adder that outputs θ′−π / 2 and the output value θ ′ of the complement switching circuit as an address, the amplitude data of the half cycle (0 ° to 180 °) of the cosine waveform stored in advance can be sequentially read. The third ROM is replaced with a fourth ROM capable of storing the same data as the third ROM and sequentially reading the output value θ′−π / 2 of the adder as an address. The direct digital synthesizer according to claim 1, characterized in that. 3. The direct digital synthesizer according to claim 2, wherein the third ROM and the fourth ROM are provided with an output value θ ′ of the complement switching circuit and an output value θ′−π / of the adder. 2 as an input, and a second switching circuit that alternately switches and outputs according to the polarity of the reference clock f _CLK ; and an output value of the second switching circuit as an address, a half cycle (0 ° to A fifth ROM capable of sequentially reading amplitude data of 180 °) and a third switching circuit for switching the output destination of the fifth ROM at the same timing as the second switching circuit. 3. The direct digital synthesizer according to claim 2, which is replaced.