JPH0632463B2 - Clamp circuit for color difference line sequential signal - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for clamping two types of color difference signals in a color difference line sequential signal at different levels, and more particularly to RY
A circuit useful for setting a difference of 100 KHz between the center carrier frequency of the RY signal and the center carrier frequency of the BY signal in the line-sequential frequency modulation recording method of the signal and the BY signal. is there.

<Prior Art> An electronic still video system is known as a system for recording a still image video signal on a magnetic disk. The standard of this system is unified worldwide. As the recording method, the luminance signal is recorded by directly frequency-modulating (FM) the carrier. In addition, two color difference signals R-Y and B
With respect to -Y, as shown in FIG. 2A, the RY signal and the BY signal are alternately selected every horizontal scanning period (1H) to form a color difference line sequential signal. Then, in order to distinguish between the two color difference signals, an offset voltage DC is added and frequency modulation is performed as shown in FIG. 2 (b), and frequency multiplexing with the FM signal of luminance is recorded. In FIG. 2, (c) represents the luminance signal Y. Further, in FIG. 2, the numbers attached to R-Y, B-Y, and Y indicate the order of horizontal scanning.

FIG. 3 shows the spectrum arrangement of the frequency modulation described above.
In FIG. 3, 1 indicates the band of the FM luminance signal, the sync tip level is 6 MHz, the white peak is 7.5 MHz,
It is defined in the standard. On the other hand, 2 indicates the band of the FM color difference line sequential signal, and the center carrier frequency _{1 of the} RY signal is
1.2MHz, center carrier frequency _{2 of} BY signal is 1.3MH
z and the standard.

Frequency difference Δ in the center carrier of the RY and BY signals
= ₂ - ₁ = 100KHz from providing, for the simultaneous reduction of the time of reproduction, it is necessary to distinguish between the R-Y signal and B-Y signal. That is, when demodulating the FM color difference line sequential signal,
Since the level in the horizontal blanking period differs between the RY signal and the BY signal by a value corresponding to the frequency difference of the center carrier, by detecting this level, the current signal is RY. Or BY.

In order to realize the frequency difference Δ between the center carriers described above, a color signal processing circuit as shown in FIG. 4 has been conventionally used. In FIG. 4, 3 is a clamp circuit dedicated to the RY signal, 4 is a clamp circuit dedicated to the BY signal, and 5
Is a clamp pulse generation circuit, 6 is a line sequential switch,
Reference numeral 7 is a frequency modulator. Each of the clamp circuits 3 and 4 includes an emitter follower circuit 9 and 10 having a coupling capacitor 8 in the input stage, a resistance voltage dividing circuit as the clamp voltage sources 11 and 12, and clamp switches 13 and 14. The clamp switches 13 and 14 are turned on every 1H by the clamp pulse 15 from the circuit 5 for a certain period (for example, pedestal level period and sync tip period) of the horizontal blanking period, and the clamp voltage source 11 and
Twelve DC voltages V ₁ and V ₂ are applied to the coupling capacitors of the clamp circuits 3 and 4. As a result, the level of the RY signal is clamped to the voltage V _{1 and} the level of the BY signal is clamped to the voltage V ₂ . Each clamped R
The −Y signal 16 and the BY signal 17 are alternately selected by the switch 6 for each 1H, and the color difference line sequential signal 18 is input to the frequency modulator 7. In frequency modulation, the clamp level V ₁ of the RY signal corresponds to the frequency ₁ of the center carrier, and the clamp level V _{2 of the} BY signal.
Corresponds to frequency ₂ of the central carrier. Therefore,
The two clamp voltage sources 11 and 12 have a voltage difference ΔV = V between them.
Frequency difference of ₂ -V ₁ are two central carrier delta = ₂ - ₁
It is designed to correspond to = 100 KHz. The signal 19 is a control signal for the switch 6, and alternately becomes high level and low level every 1H.

<Problems to be Solved by the Invention> In the clamp circuits 3 and 4 shown in FIG. 4, the clamp switches 13 and 14 are directly connected to the RY and BY signal lines, respectively. , Switches 13, 14
There is a problem that spike-like noise is generated in the color difference line sequential signal 18 every time the signal is turned on / off.

There is also a problem that two clamp circuits 3 and 4 are required to make the clamp level V ₁ of the RY signal different from the clamp level V ₂ of the BY signal.

In view of the above-mentioned problems of the prior art, the present invention does not generate spike noise in the color difference line sequential signal.
It is an object of the present invention to provide a circuit capable of clamping the RY signal and the BY signal at different levels in one circuit.

<Means for Solving the Problems> The clamp circuit according to the present invention that achieves the above-mentioned object is
A positive-phase DC amplifier that inputs and amplifies RY and BY color-difference line sequential signals, a circuit that generates a clamp pulse for each horizontal scanning period, and a clamp pulse that is controlled by this clamp pulse. During this period, there is a switch for passing the output signal of the positive-phase DC amplifier, and there is a level difference corresponding to the frequency difference between the two center carriers in the color difference line sequential frequency modulation recording. A circuit that generates a reference level signal whose level alternates every period, a circuit that compares the reference signal with the output signal of the switch, a capacitor that integrates the compared output, and an output signal of this comparison circuit. To the input signal of the positive-phase DC amplifier.

<Operation> In the above-described configuration, the switch changes the level of the color difference line sequential signal amplified by the positive phase DC amplifier for one horizontal scanning period (1
H) every time. The output signal of the switch is compared with the reference level signal by the comparison circuit, and the difference between the two is integrated and fed back to the input of the positive phase DC amplifier. As a result, feedback control is performed so that the level of the color difference line sequential signal matches the level of the reference level signal, and clamping is performed. Further, the reference level signal changes every 1H between a first level and a second level having a level difference corresponding to the frequency difference between the two center carriers in the color difference line sequential frequency modulation recording. Therefore, RY in the color difference line sequential signal
A level difference corresponding to the frequency difference of the center carrier occurs between the signal and the clamp level of the BY signal. In this case, since the output impedance of the positive phase DC amplifier is sufficiently small and the integrating circuit is used, spike noise hardly occurs. In addition, the level of the reference level signal is
Since it changes to the level, only one clamp circuit is required.

<Embodiment> An embodiment of the clamp circuit according to the present invention will be described with reference to FIG. FIG. 1 shows a recording color signal processing unit in an electronic still video device, in which a line sequentializing switch 6, a clamp circuit 20, and a frequency modulator 7 are connected in this order.

The switch 6 operates in response to the control signal 19 to select the RY signal and the BY signal alternately every 1H as in the conventional case. However, the color difference line sequential signal 2 output from the switch 6
1 is input to the clamp circuit 20 unlike the conventional one.

The clamp circuit 20 is a positive-phase DC amplifier 30, a clamp pulse generation circuit 5 having the same configuration as the conventional one, and a signal extraction switch 4
0, a reference level signal generation circuit 50, a differential input type integration circuit 60, and a feedback addition circuit 70.

The DC amplifier 30 outputs the color difference line sequential signal 21 from the switch 6.
Is amplified without inverting the phase, and the amplified signal 31 is applied to the frequency modulator 7 and the switch 40, respectively. The switch 40 is connected between the output terminal of the DC amplifier 30 and one (inverting) input terminal of the integrating circuit 60.

ON / OFF of the switch 40 is controlled by the clamp pulse 15 from the circuit 5, and in this example, the clamp pulse 1
Turns on while 5 is high. The clamp pulse 15 is a pulse that goes high every 1H for a certain period during the horizontal blanking period, for example, a pedestal level period or a sync tip period. Therefore, the signal 31 amplified by the DC amplifier 30 is input to the inverting input terminal of the integrating circuit 60 for a certain period of the horizontal blanking period. The circuit 50 is a circuit that generates a DC signal 51 whose voltage alternates between V ₁ and V ₂ every 1H.
Is applied to the other (non-inverting) input terminal of the integrating circuit 60 as a reference level signal. However, the voltage value V ₁ is the clamp level of the RY signal, and V ₂ is the clamp level of the BY signal. The difference [Delta] V = V ₂ -V ₁ is the frequency difference delta = ₂ the two central carrier in the frequency modulation - is set to correspond to _1. In other words, the voltage value V ₁ corresponds to the center carrier frequency of the RY signal ₁ = 1.2 MHz, and V ₂ is the center carrier frequency of the BY signal ₂ = 1.3 MHz.
Equivalent to. However, the level change of the reference level signal 51 and the signal selection of the switch 6 are synchronized, and the switch control signal 19 is generated by the reference level signal generation circuit 50.

The integrating circuit 60 uses an operational amplifier 61. The operational amplifier 61 has an inverting input terminal and a non-inverting input terminal, and a resistor 62 is connected to the inverting input terminal so as to form a series circuit with the switch 40. A capacitor 63 is connected between the inverting input terminal and the non-inverting input terminal. Therefore, the difference between the reference level signal 51 and the output signal 41 of the switch 40 is amplified and integrated.

The adding circuit 70 includes a resistor 71 connected between the output terminal of the integrating circuit 60 and the input terminal of the positive phase DC amplifier 30, and a resistor 72 connected between the input terminal of the DC amplifier 30 and the ground.
Have and. As a result, the integrated output signal 64 from the integrating circuit 60 is added to the color difference line sequential signal 21 from the switch 6 and feedback is performed.

The operation of the clamp circuit 20 having the above configuration will be described.
It is now assumed that when the switch 40 is turned on, the output level V _S of the switch 40 is lower than the level of the reference level signal 51 at that time, for example, V ₁ . Then, the difference V ₁ −V _S is amplified and integrated, and the integrated output signal is added to the input of the DC amplifier 30. As a result, feedback control is performed and V _S = V ₁ . Then, when the switch 40 is turned off, the reference level signal 51 continues to be added to the input of the DC amplifier 30, and continues until the switch 40 is turned on next. When the switch 40 is turned on again, feedback control is performed so that V _S = V ₂ . By repeating the above, the color difference line sequential signal 3 output from the DC amplifier 30.
1 is clamped to V ₁ for the RY signal and V ₂ for the BY signal. Reference numeral 22 is an output terminal for the clamped color difference line sequential signal 31.

At this time, in the clamp circuit 20, the output impedance of the DC amplifier 30 is small, and the output signal 4 of the switch 40 is
Since 1 is fed back to the input of the DC amplifier 30 through the integrating circuit 60, spike-like noise hardly occurs in the color difference line sequential signal 31 due to ON / OFF of the switch 40. Further, the RY signal and the BY signal are clamped to predetermined different levels V ₁ and V ₂ by one clamp circuit 20 according to the reference level signal 51.

The color-difference line-sequential signal 31 from the DC amplifier 30 is given to the frequency modulator 7, and frequency-modulates the carrier as in the conventional case.

<Effects of the Invention> According to the clamp circuit of the present invention, the level difference required for color difference line sequential frequency modulation recording is RY without generating spike noise in the color difference line sequential signal and with one clamp circuit. Signal and BY signal can be set.

[Brief description of drawings]

FIG. 1 is a block diagram of a color signal processing unit having an embodiment of a clamp circuit according to the present invention, FIG. 2 is an explanatory diagram for producing a color difference line sequential signal from a component video signal, and FIG. 3 is an electronic still video system. FIG. 4 is a configuration diagram of a color signal processing unit equipped with a conventional clamp circuit. In the drawings, 5 is a clamp pulse generation circuit, 6 is a line sequential switch, 7 is a frequency modulator, 20 is a clamp circuit, 21 is a color difference line sequential signal before clamping, 30 is a positive phase DC amplifier, 3
1 is a color difference line sequential signal after clamping, 40 is a signal extraction switch, 50 is a reference level signal generating circuit, 51 is a reference level signal, V ₁ and V ₂ are each level, 60 is an integrating circuit, 61
Is an operational amplifier thereof, 63 is a capacitor, and 70 is a feedback addition circuit.

Claims (1)

[Claims] 1. A positive-phase DC amplifier for inputting and amplifying RY and BY color difference line sequential signals, a circuit for generating a clamp pulse for each horizontal scanning period, and control by the clamp pulse. While the clamp pulse is being input, there is a switch for passing the output signal of the positive-phase DC amplifier, and a level difference corresponding to the frequency difference between the two center carriers in the color difference line sequential frequency modulation recording. A circuit for generating a reference level signal whose level alternates every horizontal scanning period, a circuit for comparing the reference level signal with the output signal of the switch, a capacitor for integrating the compared output, A circuit for feeding back the output signal of the comparison circuit to the input signal of the positive phase DC amplifier, and a clamp circuit for the color difference line sequential signal.