JPH06324910A - Access detector for computer system - Google Patents

Abstract

(57) [Summary] [Structure] ADT 7 for determining whether or not the access by the operation unit 1 is within the access detection area, and an access prohibition designation unit for setting access prohibition and permission from the operation unit 1 when access is detected. 17, the interrupt signal output from the ADT 7 to the IRQ, and the setting contents of the access prohibition designating unit 17, the read prohibition gate 10 that prohibits the slave read strobe of the SRD for the slave target 18, and the slave write of the SWD for the slave target 18. It comprises a write inhibit gate 11 which inhibits strobe. [Effect] Writing to the slave target when access is detected,
Since the configuration is such that read prohibition and permission can be specified, the efficiency of finding bugs during program debugging is improved, and it is also effective in preventing unauthorized access during system operation and system down.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access detecting apparatus suitable for investigating the cause of a program failure in a computer system used in various fields.

[0002]

2. Description of the Related Art Conventionally, in computer systems,
Most of the technologies for preventing access or detecting access are intended to protect the memory contents and prevent unauthorized writing.

Regarding the reading of memory contents, Japanese Patent Laid-Open No. 62-62
As described in Japanese Patent Laid-Open No. 160554, there is also invented an unauthorized access prevention device which is not limited to writing and which can prevent reading of data that should not be referred to during program execution. This is a means to set and store the access prohibited area of the memory, a means to judge whether the access address is in the prohibited area at the time of access of the arithmetic unit, and an access strobe output from the arithmetic unit as the judgment result can be accessed. If the determination result is inaccessible, it is provided with a gate means for giving to the memory, and a means for notifying the operation unit of inaccessibility.

In this technique, when the read address from the memory of the arithmetic unit is in the read prohibited area, the read from the memory is prohibited, and when the write address to the memory is in the write prohibited area, the write to the memory is prohibited. , Report to the operation unit.

[0005]

According to the above-mentioned prior art, there is an effect that it is possible to prevent the writing of data into an erroneous area by a program and the reference of data in an erroneous area, and it is also an illegal access to the arithmetic unit. Since it is reported, it becomes easier to find bugs in the program,
When detecting whether or not to correctly access the expected value address in the operation check of the program in which the access address changes depending on the execution condition of the program using indirect address specification, relative address specification, etc., the access itself is permitted, It may be desirable to continue the processing of the program based on the access result even after the access detection processing. In that case, the operation unit is notified as an interrupt, and after the access result is checked by the interrupt program, the processing of the program is continued, but in the prior art, access to the access detection area is prevented entirely. Therefore, there is a problem that it is difficult to continue the processing of the program.

An object of the present invention is to provide an access detection device that improves the efficiency of operation confirmation.

[0007]

In order to achieve the above object, the present invention provides means for designating an access detection area and whether or not an access from a computing unit is within the access detection area designated by the means. Means for comparing and outputting a detection signal to the arithmetic unit when in the access detection area; means for specifying whether or not the arithmetic unit gives an access strobe to the slave target when the detection signal is output; A means for determining whether or not to give the access strobe to the slave object is provided based on the content and the output of the detection signal.

[0008]

When the arithmetic unit is accessing the inside of the access detection area, the arithmetic unit recognizes that the inside of the access detection area is accessed by notifying the arithmetic unit. It is possible to specify whether the access operation is prohibited or allowed, and if the access permission is specified, it is possible to continue checking the normal operation of the operation check target program executed by the arithmetic unit. Further, after the arithmetic unit recognizes that the access detection area is being accessed, it executes the interrupt program corresponding to the recognition and confirms whether the access operation is correctly performed by the interrupt program. On the contrary, when the arithmetic unit is accessing the access detection area, if the prohibition of the access operation from the arithmetic unit to the slave target is specified, the access is prevented, so the slave target is protected and It is possible to detect abnormalities in the program being checked or running.

When the arithmetic unit is accessing the outside of the access detection area, the arithmetic unit is not notified and the operation of accessing the slave target is performed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention. The arithmetic unit 1 that arbitrarily reads and writes is connected to the memory 12 and the peripheral I / O 13 via AB and DB. The arithmetic unit 1 outputs an address for accessing AB. WR when the arithmetic unit 1 writes
The write strobe is output to, and at that time, the arithmetic unit 1 outputs the write data to the DB. When the arithmetic unit 1 reads out, it outputs a read strobe to RD, and at that time, the arithmetic unit 1 reads out the data output to DB.

The memory 12, peripheral I / O 13 and write inhibit gate 11 are connected using SWR. When the slave write strobe is output from the write inhibit gate 11 to the SWR and the address output from the arithmetic unit 1 using AB is the address assigned to the memory 12, the content of DB is the area of the memory 12 corresponding to the address. Stored in.

The memory 12, the peripheral I / O 13 and the read inhibit gate 10 are connected using SRD. If a slave read strobe is output from the read inhibit gate 10 to the SRD and the address output from the arithmetic unit 1 using AB is the address assigned to the memory 12, the memory 12 is stored in the area corresponding to the address. Output contents to DB.

Peripheral I / O 13 is connected to peripheral devices such as a keyboard and a display, and takes in the input contents from the keyboard and outputs the output contents from the arithmetic unit 1 to the display and the like. When the slave write strobe is output to SWR and the address output by the arithmetic unit 1 using AB is the address assigned to the peripheral I / O 13, the peripheral I / O 13 assigns the contents of the DB to the address. Output to the device. If a slave read strobe is being output to SRD and the address output from the arithmetic unit 1 using AB is the address assigned to the peripheral I / O 13, the peripheral I / O 13 will display the contents of the peripheral device assigned to the address. Output to DB.

Access detect trap (hereinafter referred to as ADT
(Abbreviated as 7) and the arithmetic unit 1 are connected by AB, RD, and WR. In addition, the ADT 7 includes an arithmetic unit 1 and a read inhibit gate 1
0 and write inhibit gate 11 are connected by IRQ. A
An access detection area can be designated in the DT 7, and it is determined whether or not the designated access detection area includes an address accessed by the arithmetic unit 1 using AB. Separately, the execution or prohibition of the read detection can be designated in the ADT 7, and when the read detection execution is designated when the access detection area includes the access address from the arithmetic unit 1, the access is read by the RD from the arithmetic unit 1. When recognizing that, ADT7 outputs an interrupt signal to IRQ. Separately, execution or prohibition of write detection can be specified in the ADT 7, and when the write detection execution is specified when the access detection area includes an access address from the operation unit 1, the access is written by the WR from the operation unit 1. When recognizing that, ADT7 outputs an interrupt signal to IRQ.

The arithmetic unit 1 sequentially executes a normal program, but when an interrupt signal is input from the ADT 7 by the IRQ, the normal program is stopped and the interrupt program is executed. When the interrupt program ends, the process can be restarted from the point where the normal program was stopped.

In the access prohibition designating section 17, read prohibition or permission and write prohibition or permission are designated.
The access prohibition designation unit 17 and the read prohibition gate 10 are connected by RDINH. When the access prohibition designation unit 17 is designated to read out, a read prohibition designation signal is output to RDINH. The access prohibition designating section 17 and the write prohibition gate 11 are connected by WRINH, and when write prohibition is designated in the access prohibition designating section 17, a write prohibition designating signal is output to WRINH.

The read prohibition gate 10 is connected to the ADT 7 by using IRQ, is connected to the arithmetic unit 1 by using RD, and is connected to the access prohibition designating unit 17 by using RDINH.

The write prohibition gate 11 is connected to the ADT 7 by using IRQ, is connected to the arithmetic unit 1 by using WR, and is connected to the access prohibition specifying unit 17 by using WRINH.

In this computer system, read strobes and write strobes are output to RD and WR at the timings when valid information is output to AB and DB, respectively, and only one of them is valid, and both are not valid at the same time. .

FIG. 2 shows an example of the internal circuit of the read inhibit gate 10 used in the computer system of FIG.

In the configuration of FIG. 2, RDINH and IRQ
Is connected to the input of the NAND gate 50, and the NAND gate 50 outputs the NAND of RDINH and IRQ to the AND gate 60 using SREN. RD and SREN are connected to the input of the AND gate 60, and the AND gate 60
Outputs the logical product of RD and SREN to SRD.

With this configuration, the read strobe of the RD is transmitted to the SRD when the interrupt signal is not output to the IRQ. When an interrupt signal is output to IRQ and a read inhibit designating signal is output to RDINH, the read strobe of RD is prohibited and is not transmitted to SRD. Even if the interrupt signal is output to IRQ, the read strobe of RD is S when the read inhibit designating signal is not output to RDINH.
It is transmitted to RD.

FIG. 3 shows an example of the internal circuit of the write inhibit gate 11 used in the computer system of FIG.

In the configuration of FIG. 3, WRINH and IRQ are used.
Is connected to the input of the NAND gate 70, and the NAND gate 70 outputs the NAND of WRINH and IRQ to the AND gate 80 by using SWEN. WR and SWEN are connected to the input of the AND gate 80, and the AND gate 80
Outputs the logical product of WR and SWEN to SWR.

With this configuration, the write strobe of the WR is transmitted to the SWR when the interrupt signal is not output to the IRQ. When the interrupt signal is output to IRQ and the write inhibit designating signal is output to WRINH, the write strobe of WR is prohibited and is not transmitted to SWR. Even if the interrupt signal is output to IRQ, the write strobe of WR is S when the write inhibit designating signal is not output to WRINH.
It is transmitted to WR.

FIG. 4 shows an example of a flow chart of a test program for confirming the operation of the program using the computer system of FIG. Further, FIG. 5 shows an example of a flowchart of an interrupt program executed by the arithmetic unit 1 when an IRQ interrupt signal is input to the arithmetic unit 1 as an aid to the test program of FIG. In these flowcharts, it is checked whether the program whose operation is to be confirmed normally accesses the peripheral I / O 13. As an example of the operation confirmation, a method for confirming whether the peripheral I / O 13 is normally written will be shown below.

First, as a preparation process for operation confirmation, process 1
As shown in 00, the access range of the peripheral I / O 13 is designated in the access detection area of the ADT 7. In this processing, the address range of the peripheral I / O 13 and detection of write access are specified. Detection of read access is not specified. Next, as shown in process 120, access permission is designated in the access prohibition designation unit 17. In this process, write access permission is specified. In process 140, an interrupt detection flag is provided in the memory 12 and this flag is cleared. After that, the computing unit 1 executes the program whose operation is to be confirmed as shown in process 160.

When a write access is made to the peripheral I / O 13 which is the access detection area of the ADT 7 designated in the process 100 during execution of the program to be checked for operation, AD
T7 outputs an interrupt signal to IRQ. Although the IRQ interrupt signal is input to the write inhibit gate 11, processing 12
At 0, the write inhibition is designated in the access inhibition designating unit 17, so that the write inhibition designating signal is not output to WRINH, and the slave write strobe is output to SWR to perform the writing. Separately from that, the IRQ interrupt signal is transmitted to the arithmetic unit 1, and the arithmetic unit 1 shifts to the interrupt program processing. In the interrupt program, first, as shown in process 300, a process of accepting an interrupt is performed. In the subsequent process 320, it is confirmed whether the peripheral I / O 13 is normally accessed. In this case, the inside of the peripheral I / O 13 is read, and it is confirmed from the read contents whether or not the peripheral I / O 13 is normally accessed. If it is normal, the process 340 is executed, and if abnormal, the process 360 is executed. At this time, ADT
Since the detection of the read access is not designated in 7, the interrupt signal is not output to the IRQ, and the normal reading can be performed. In process 340, normal detection is set in the interrupt detection flag, and the process proceeds to process 380. In process 360, abnormality detection is set in the interrupt detection flag, and the process proceeds to process 380. In the subsequent process 380, recovery from the interrupt acceptance process performed in process 300 is performed, and this interrupt process ends.

After the execution of the program whose operation is to be confirmed shown in process 160, the interrupt detection flag is evaluated as shown in process 180 to determine whether or not the access to the peripheral I / O 13 is normal. If normal detection is set in the interrupt detection flag, the operation confirmation is normal, and the normal termination process of this test program is performed as shown in process 200. If abnormality detection is set in the interrupt detection flag, it is determined as an operation confirmation abnormality, and the error termination processing of this test program is performed as shown in processing 220. In this case, the method of accessing the peripheral I / O 13 from the program whose operation is to be confirmed may be abnormal. When the interrupt detection flag is clear, it is determined that the access is not executed, and the non-detection process of this test program is performed as shown in process 240. In this case, the program whose operation is to be confirmed may not be accessing the peripheral I / O 13.

In this example, since detection of write access to the peripheral I / O 13 and write access permission are designated,
The write access to the peripheral I / O 13 is executed by the program whose operation is to be confirmed in the process 160. If this is the write access prohibition only as in the conventional technique, the write to the peripheral I / O 13 is blocked, so that the peripheral I / O is blocked.
It is not possible to confirm from the operation of No. 13, the output signal from the peripheral I / O 13, or the read data of the peripheral I / O 13 whether the program whose operation is to be confirmed operates the peripheral I / O 13 normally. Peripheral I / O 1 is used in this example.
A program that uses 3 calculates the access address during execution of the program, such as indirect address specification, relative address specification, index address specification, etc., and the processing specifications to access the peripheral I / O 13 at the address resulting from the calculation. There are cases such as checking whether or not you are accessing the street, and for example, you have multiple peripheral I / O, such as a communication buffer, but you can change multiple peripheral I / O by changing the specified value of the indirect address. Check the operation when operating with.

When both the read access detection and the write access detection are specified in the ADT 7 in the processing 100 of the example of FIG. 4, and the read access prohibition and the write access permission are specified in the access prohibition designating unit 17 in the processing 120,
When the arithmetic unit 1 writes the access detection area designated as the detection target of the ADT 7 in the process 100, an interrupt signal is output to the IRQ, the arithmetic unit 1 recognizes the writing to the access detection area, and the writing is executed. However, in the case of reading, the operation unit 1 performs IR reading to the access detection area.
Although it is recognized that the Q interrupt signal is input, the IRD interrupt signal and the RDINH write inhibit designating signal are input to the read inhibit gate 10, so that the SRD is disabled and the read is blocked. . This is the peripheral I / O 13
It can be used to check the operation of the program that prohibits reading or accessing the write-only register. On the contrary, when the read access permission and the write access prohibition are designated, it can be used to confirm the operation of the program that prohibits the write in the peripheral I / O 13 and the read-only register.

If read access prohibition and write access prohibition are designated separately from this, when ADT7 outputs an interrupt signal to IRQ, SRD and SWD become invalid and ADT7.
Access protection can be performed on the detection target of. Therefore, this access detection device can be used as a conventional unauthorized access prevention device during the actual operation.

[0034]

As described above, according to the present invention, it is possible to selectively specify write or read prohibition or permission to a slave target when an access is detected. The present invention is effective in preventing unauthorized access during the actual operation of a computer system using the access detection device of the invention, and also in preventing system down.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system using an access detection device of the present invention.

FIG. 2 is an internal circuit diagram of the read inhibit gate shown in FIG.

3 is an internal circuit diagram of the write inhibit gate shown in FIG.

FIG. 4 is a test program side flowchart for confirming the operation of a program using the computer system of FIG.

5 is an IRQ to assist the test program of FIG.
3 is a flowchart of an interrupt program executed by the arithmetic unit when the interrupt signal of 1 is input to the arithmetic unit.

[Explanation of symbols]

1 ... Operation unit, 7 ... Access detect trap, 10 ...
Read inhibit gate, 11 ... Write inhibit gate, 12
... memory, 13 ... peripheral I / O, 17 ... access prohibition designation section.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuaki Kobayashi 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory

Claims (7)

[Claims] 1. In a computer system comprising an arithmetic unit for reading and writing and a slave target to be read and written from the arithmetic unit, it is determined whether an access from the arithmetic unit is included in a designated access detection area. Means for making a determination and reporting the result of the determination to the arithmetic unit; means for designating whether or not the access strobe output from the arithmetic unit is given to the slave target; and the slave based on the determination result and the designated content. An access detecting apparatus for a computer system, comprising means for determining and executing whether or not to give the access strobe to an object. 2. The access detection device according to claim 1, wherein the access detection area can be designated arbitrarily. 3. The access detection device of a computer system according to claim 1, wherein the means for reporting to the computing unit can arbitrarily designate whether or not to report. 4. A read strobe output when the arithmetic unit reads in the means for designating whether or not the access strobe output from the arithmetic unit according to claim 1 is given to the slave target, and a write strobe written by the arithmetic unit. An access detection device for a computer system capable of arbitrarily specifying whether or not to give a write strobe output at times to the slave target. 5. The access to the slave target if the access from the operation unit is not included in the access detection area in the means for determining whether or not to give the access strobe to the slave target according to claim 1. An access detection device for a computer system that gives the access strobe to the slave target regardless of whether or not a strobe is given. 6. The access strobe for the slave target when the access from the arithmetic unit is included in the means for determining whether or not the access strobe is given to the slave target according to claim 1. An access detecting device of a computer system for giving the access strobe to the slave target when the designation is given. 7. The access strobe for the slave target in the case where the access from the arithmetic unit is included in the means for determining whether to give the access strobe to the slave target according to claim 1. An access detection device of a computer system which does not give the access strobe to the slave target when the designation is made not to give.