JPH06324997A - FIFO storage device incorporating a plurality of FIFO memories - Google Patents

Abstract

(57) [Abstract] [Purpose] A FIFO memory device that does not increase the number of components even if the number of CPUs on the data writing side or the data reading side increases, and that is easy to reduce in size and cost. [Structure] A plurality of built-in FIFO memories 11, 12, 13
And the command X of the data write side CPUs 21, 22, 23
1, the data writing side CPU based on X2, X3
Input side bus converter 14 for connecting any one of the plurality of built-in FIFO memories to the data reading side CPU 3
The output side bus converter 15 connects the data read side CPU to any of the plurality of built-in FIFO memories based on the instructions Y1, Y2 and Y3 of 1, 32 and 33. Therefore, both the data writing side CPU and the data reading side CPU can freely access the built-in FIFO memory and can effectively use the built-in FIFO memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO storage device used as a data buffer for data transfer between bus systems operating at different clock frequencies and data transfer between multiprocessors.

[0002]

2. Description of the Related Art Conventionally, this type of FIFO storage device is provided with only one input port and one output port, and the method of connecting to an external CPU or the like is uniformly determined.

[0003]

SUMMARY OF THE INVENTION The above-mentioned conventional FIFO.
If there are a plurality of CPUs on the data write side or the data read side, the storage device must be provided with a plurality of FIFO storage devices, and the data write side CPUs and the data read side CPUs must be connected one-to-one. . Therefore, as the number of CPUs on the data writing side or the data reading side increases, the number of parts increases, which makes it difficult to reduce the size and cost.

In view of the above-mentioned problems, the present invention has the following advantages even if the number of CPUs on the data writing side or the data reading side increases.
It is an object of the present invention to provide a FIFO storage device that is easy to reduce in size and cost without increasing the number of parts.

[0005]

A FIFO storage device of the present invention connects a plurality of built-in FIFO memories and one of the plurality of built-in FIFO memories with the data writing side CPU based on a command from a data writing side CPU. The input side bus converter and the data reading side CPU based on a command from the data reading side CPU.
And an output side bus converter connected to any of the IFO memories.

Preferably, the input side bus converter is provided with a plurality of input ports, each input port can be connected to a data write side CPU, and the output side bus converter has a plurality of output ports. Is provided, and a data reading CPU can be connected to each output port.

[0007]

The input-side bus converter of the FIFO storage device, in accordance with the command from the data-writing CPU, connects the command-writing data-writing CPU to the commanded built-in FIFO memory. Therefore, the data writing CPU writes desired data in the connected built-in FIFO memory. At this time, if the capacity and the like are insufficient with the connected internal memory alone, it is requested to connect to another internal memory and data writing is continued. On the other hand, the output side bus converter is
According to the instruction of the data reading side CPU, the data reading side CPU that has issued the instruction is connected to the instructed built-in FIFO memory. Therefore, the data reading CPU reads desired data from the connected built-in FIFO memory.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a FIFO storage device of the present invention. In this embodiment, the FIFO storage device 10, CPUs 21, 22, 23 and CPU 3 are used.
1, 32, and 33 are configured to exert a bus exchange function.

In the FIFO memory device 10, the input ports P1, P2, P3 of the bus converter 14 are connected to the CPUs 21, 22, 2 via the buses BA1, BA2, BA3, respectively.
3 is connected. The bus converter 14 is the CPU 21,
Based on the bus connection commands X1, X2, X3 from 2, 23, the buses BA1, BA2, BA3 are connected to the buses BB1, BB.
2, BB3, CPU21,22,2
3 accesses any of the built-in FIFO memories 11, 12, and 13 so that data can be written.

Output ports Q1, Q2 of the bus converter 15
CPUs 21, 22, and 23 are connected to Q3 via buses BD1, BD2, and BD3, respectively. The bus converter 15 uses the bus connection command Y from the CPUs 31, 32, 33.
Based on 1, Y2, Y3, buses BD1, BD2, BD3
Is connected to any of buses BC1, BC2, BC3, and C
The PUs 31, 32, 33 have built-in FIFO memories 11, 1
Access any of CPUs 2, 22 and
23 makes it possible to read the data written in the built-in FIFO memories 11, 12, 13.

Next, the operation of this embodiment will be described with a specific example. In this specific example, the CPU 21 sends data to the CPU 32 via the internal memories 11 and 12. First, the CPU 21 outputs the bus connection command X1 and the bus B
It instructs the bus converter 14 to connect A1 and the bus BB1. The bus converter 14 connects the bus BA1 and the bus BB1 based on the bus connection command X1. Bus BA1
And the bus BB1 are connected, the CPU 21 designates the CPU 32 as a destination and sends predetermined data to the buses BA1 and B1.
Data is written to the internal FIFO memory 11 via B1 according to the FIFO operation.

Further, the CPU 21 sends the next bus connection command X
1 is output to instruct the bus converter 14 to connect the bus BA1 and the bus BB2. Bus BA1 and bus BB
2 is connected, the CPU 21 sets the CPU 3 as the destination.
2 is designated, predetermined data is written to the internal FIFO memory 12 according to the FIFO operation via the buses BA1 and BB2, and the writing process is completed.

The CPU 32 outputs a bus connection command Y2 to the bus converter 15 at its own data read timing,
The bus converter 15 is instructed to connect the bus BD2 and the bus BC1. After the bus BD2 and the bus BC1 are connected, the CPU 32 accesses the internal FIFO memory 11 and detects that the data is written to itself.
Read the data according to the FIFO operation. Next CPU3
2 is the bus BD2 and the bus BC2 according to the bus connection command Y2.
The bus converter 15 is instructed to connect and. Bus B
After D2 and the bus BC2 are connected, the CPU 32 accesses the internal FIFO memory 12, detects that the data is written to itself, and reads the data according to the FIFO operation.

Further, the CPU 32 commands the bus converter 15 to connect the bus BD2 and the bus BC3 by the bus connection command Y2. After the bus BD2 and the bus BC3 are connected, the CPU 32 accesses the internal FIFO memory 12, detects that no data is written to itself, and finishes reading the data.

The CPU 21, which is composed of the bus converters 14 and 15,
22, ..., 33 built-in FIFO memories 11, 12, 13
Can be freely connected by presetting, and the use of the built-in FIFO memories 11, 12, and 13 becomes more flexible, and the use efficiency is improved.

[0016]

As described above, according to the present invention, a plurality of F
In addition to incorporating the IFO memory, the CP on the data write side via the bus converter on the input side and the bus converter on the output side
Freely built-in FIFO for U and CPU for data reading
By being able to access the memory, even if the number of CPUs on the data writing side or the data reading side increases, the number of parts does not increase so much, and there is an effect that size reduction and cost saving can be facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a FIFO storage device of the present invention.

[Explanation of symbols]

 10 FIFO storage device 11, 12, 13 Built-in FIFO storage device 14, 15 Bus converter 21, 22, ..., 33 CPU BA1, BA2, ..., BD3 bus X1, X2, ..., Y3 bus connection command

Claims (2)

[Claims] 1. A plurality of built-in FIFO memories and an input side bus converter for connecting the data writing side CPU to any one of the plurality of built-in FIFO memories based on a command from the data writing side CPU, and a data reading side CPU. Based on the command of 1., a FIFO storage device having an output side bus converter that connects the data reading side CPU to any of the plurality of built-in FIFO memories. 2. The input-side bus converter is provided with a plurality of input ports, each input port can be connected to a data writing-side CPU, and the output-side bus converter has a plurality of output ports. 2. The FIFO storage device according to claim 1, wherein the FIFO storage device is provided and a data reading CPU can be connected to each output port.