JPH06325502A - Digital signal recording/reproduction device - Google Patents

Abstract

(57) [Abstract] [Purpose] As one means for improving the error correction capability of digital signal recording / reproduction using mn modulation, a plurality of heads are prepared and a plurality of series of reproduction signals obtained from those heads and Random errors are reduced by preferentially selecting a reproduction signal of a system having a small number of block errors by using a block error signal generated at the time of n-m demodulation. [Structure] A digital signal recording / reproducing apparatus has a structure in which the number of random errors is reduced by judging from a plurality of error flags and prioritizing and selecting a series having no error flag in the multiplexing means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording / reproducing apparatus for video / audio signals such as VTR.

[0002]

2. Description of the Related Art Digital signal recording has several basic features not found in analog signal recording. That is, a certain amount or less of deterioration in the RF channel is completely recovered by error correction. This feature greatly improves the reliability of digital signal recording. That is, at the time of recording, the signal is divided into several blocks, and a redundant signal for checking is calculated and added to each block. During reproduction, an error is detected and the signal is corrected based on this redundant signal. Therefore, the higher the ratio of the redundant signal to the original signal, the higher the error correction capability.

FIG. 3 shows an example of a digital VTR having an error correction function using a Reed-Solomon product code block.

1 is a digital signal input terminal, 2 is a shuffling memory circuit, 3 is an outer encoder circuit, 4
Is an ID addition circuit, 5 is an inner encoder circuit, 6 is a channel coding circuit, 7 is a sync addition circuit, 8 is a parallel / serial conversion circuit, 9 is a recording amplifier, 10 is a recording head, 11 is a reproducing head, and 12 is a reproducing amplifier. Equivalent circuit, 13 serial / parallel conversion circuit, 14 sync / ID detection circuit, 15 channel decoding circuit, 16 inner ECC decoding circuit, 17
Is an outer ECC decoding circuit, 18 is a deshuffling memory circuit, 19 is a correction circuit, and 20 is a digital signal output terminal.

FIG. 4 is a detailed view of the recording head and the reproducing head on the cylinder of the above example, 25-1, 25-
2 is a recording head, and 26-1 and 26-2 are reproducing heads.

At the time of recording, the data sample of the digital signal input from the digital signal input terminal 1 is shuffled for each field by the shuffling memory circuit 2. This enhances the correction capability for burst errors such as dropouts. Next, the inner encoder circuit 5 calculates and adds an inner check code. The check byte of the inner code is 8 bytes and 4
It is possible to correct even serious errors.

The outer encoder circuit 3 calculates and adds an outer check code. The outer code is composed of a code length of 136 bytes and a check byte of 8 bytes, which enables even double erasure correction. Furthermore I
An ID (identification signal) for each code in the D addition circuit 4 and a sync (synchronization signal) in the sync addition circuit 7
Is added. The channel coding circuit 6 is a kind of modulation circuit for further stabilizing the transmission function in the RF channel. In digital recording, various modulation methods have been conventionally studied in order to perform high density recording on a recording medium and to extract a stable reproduction signal.

However, there is no definite view as to what the optimum modulation scheme is. For example, the randomized NTZ has the advantage that the required high-frequency characteristics are relatively low, but since it has a DC component, inter-code interference easily occurs in the recording / reproducing system, and the error rate depends on the contents of the input signal. It has the drawback of being easy.

Further, the mirror square is DC-free and has a drawback that it has excellent low-frequency characteristics but relatively high required high-frequency characteristics. The mn modulation method that converts m bits to n bits (m <n) is DC-free as well as the mirror square by properly combining the correspondence maps,
Moreover, by using azimuth recording, crosstalk from adjacent tracks can be minimized.

It is also possible to suppress the occurrence of intersymbol interference in the recording / reproducing system. That is, randomized NRZ
Randomized NRZ with excellent high-frequency characteristics
It overcomes the above drawbacks. Here, 8-14 modulation is used as an example of m-n modulation, and an 8-bit signal code is 1
Convert to 4-bit channel code. The parallel / serial conversion circuit 8 converts a 14-bit parallel signal into a serial signal, and the recording amplifier 9 and the recording head 10 record the serial signal on a magnetic tape.

At the time of reproduction, the reproduction head 11, the reproduction amplifier,
A reproduction signal is taken out from the magnetic tape by the equivalent circuit 12.
Sync / ID detection circuit 14 detects the sync
The parallel conversion circuit 13 restores a 14-bit parallel signal. At this time, the ID of each code is also detected. Next, the channel decoding circuit 15 converts the 14-bit data into 8
Decode to bit data. In the inner ECC decoding circuit 16, the inner check code corrects the error in the inner code, and the outer ECC
The decoding circuit 17 corrects the error in the outer code from the outer check code. The deshuffling memory circuit 18 restores the dispersed sample data to the original state. The data which cannot be completely corrected by the error correction circuit is interpolated and corrected by the correction circuit 19 and output from the digital signal output terminal 20 as digital data.

With such a configuration, the number 1 is calculated from the random error.
It has the ability to correct up to a 000-byte burst error.

[0013]

However, if the error correction capability is increased by the above method, the number of redundant signals other than the original signal is increased, and the original amount of signals that can be recorded on the recording medium is reduced, resulting in high density recording. On the other hand, it is not practical.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the conventional problems described above and to provide a method for improving the error correction capability while suppressing the redundant signal to a certain fixed amount.

[0015]

In order to achieve the above object, the present invention defines an n-bit (m, n is an integer satisfying the relationship of m <n) digital signal code such as m-bit video and audio. Means for coding the channel code recorded on the recording medium by a plurality of reproducing heads, and a plurality of sequences for reproducing the channel code recorded on the recording medium by a plurality of reproducing heads. Corresponding to the n-bit channel code defined in the channel decoding means, a means for extracting the reproduced signal of the above-mentioned, a means for decoding the reproduced signals of the plurality of series from an n-bit channel code to an m-bit code, Means for generating an error flag when a code is played, and the plurality of channel decoding Comprising a TBC means for correcting time base fluctuations of signals and said plurality of error flag, and means for multiplexing said been time base correction signal,
It has a configuration in which the amount of random errors is reduced by judging from the plurality of error flags and prioritizing and selecting a sequence having no error flag in the multiplexing means.

[0016]

With the above structure, it is possible to provide a method of enhancing the error correction capability without increasing the number of redundant signals.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of one embodiment of the present invention, and this embodiment will be described.

In FIG. 1, components having the same functions as those in FIG. 3 are designated by the same reference numerals. For those with the same function but increased number of circuits, a hyphen (-) and the circuit number were added after the number. 21-1, 21-2 are TBC circuits, 22 is D
An ELAY circuit, a multiplex circuit 23, and a switching signal control circuit 24.

FIG. 2 is a detailed view of the recording head and the reproducing head on the cylinder of the above example. Compared to FIG. 4 of the conventional example, the reproducing heads 26-1, 26-2 and 27-1, 27-
It has two heads of 2 series.

At the time of recording, the operation is the same as that of the conventional example of FIG. PB-HEAD11-1 and PB-HEAD during playback
Reproduced signals are separately extracted from 11-2. Each one
The 4-bit signal is decoded into an 8-bit code by the 14-8 channel decoding circuits 15-1 and 15-2,
At this time, if a 14-bit channel code that is not in the 8-bit decode map is detected, an error flag is generated. Next, since these two series of signals and error flags have time axis fluctuations, time axis correction is performed by the TBC circuits 21-1 and 21-2, and PB-HEAD
The signal and PB-HEAD taken out from 11-2 in advance
To eliminate the time difference with the signal extracted from 11-1, P
The signal extracted from the B-HEAD11-2 is DELAY
It is delayed by the circuit 22 and input to the multiplex circuit 23 at the same timing.

The control circuit 24 takes in each error flag and controls the switching signal so that the multiplex circuit 23 gives priority to the sequence in which the error flag is not set. In the case of a burst error, it is highly possible that both signals are erroneous, but in the case of a random error, it is unlikely that both signals will be erroneous at the same time, and the error correction capability of the subsequent error correction circuit can be improved by the above control. It will be possible.

The signal flow after multiplexing is the same as in FIG. 3 of the conventional example, and the error is corrected by the inner error correction circuit 16 and the outer error correction circuit 17 before being output.

[0023]

As described above, the present invention provides a method of enhancing the error correction capability without increasing the redundant signal by the above-mentioned configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a cylinder head of the same embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a configuration diagram of a cylinder head of the conventional example.

[Explanation of Codes] 21 TBC circuit 22 DELAY circuit 23 Multiplex circuit 24 Switching signal control circuit

Claims (1)

[Claims] 1. Means for coding an m-bit digital signal code such as video and audio into an n-bit (m, n is an integer satisfying the relationship of m <n) fixed channel code, and the channel code is magnetic. Means for recording on a recording medium such as a tape or magnetic disk; means for reproducing a channel code recorded on the recording medium by a plurality of reproducing heads a plurality of times to extract a plurality of series of reproduced signals; Means for decoding an n-bit channel code into an m-bit code, and n defined in the channel decoding means.
Means for generating an error flag when a code not corresponding to a bit channel code is reproduced; TBC means for correcting time axis fluctuations of the plurality of channel decoded signals and the plurality of error flags; and the time axis And a means for multiplexing the corrected signal, wherein the number of random errors is reduced by judging from the plurality of error flags and prioritizing and selecting a sequence having no error flag in the multiplexing means. Signal recording / reproducing device.