JPH06326087A - Method and apparatus for manufacturing semiconductor integrated circuit - Google Patents
Method and apparatus for manufacturing semiconductor integrated circuitInfo
- Publication number
- JPH06326087A JPH06326087A JP13285593A JP13285593A JPH06326087A JP H06326087 A JPH06326087 A JP H06326087A JP 13285593 A JP13285593 A JP 13285593A JP 13285593 A JP13285593 A JP 13285593A JP H06326087 A JPH06326087 A JP H06326087A
- Authority
- JP
- Japan
- Prior art keywords
- film
- integrated circuit
- semiconductor integrated
- pressure
- tetraethoxysilane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
(57)【要約】
【目的】 膜の緻密性を確保した上で、成膜速度を速め
ることができる半導体集積回路の製造方法及びその製造
装置を提供する。
【構成】 テトラエトキシシラン３とオゾン４を、それ
らの混合気体が大気圧よりも高い圧力になるように供給
する反応ガス供給手段１，２と、反応容器１０内に配置
された半導体基板６を加熱する加熱手段５と、を備えて
いる。層間絶縁膜を成膜する際に、大気圧よりも高い圧
力のテトラエトキシシラン３及びオゾン４の混合気体で
半導体基板６上に熱気相成長法によって層間絶縁膜を成
膜する。テトラエトキシシラン３及びオゾン４の流量を
増加させた場合でも、気相中における重合反応が十分に
進行する。膜の緻密性を確保しながら、その成膜速度を
速くすることができる。
(57) [Summary] [Object] To provide a method and an apparatus for manufacturing a semiconductor integrated circuit capable of increasing the film formation rate while ensuring the film denseness. [Structure] Reactive gas supply means 1 and 2 for supplying tetraethoxysilane 3 and ozone 4 so that a mixed gas thereof has a pressure higher than atmospheric pressure, and a semiconductor substrate 6 arranged in a reaction container 10. And heating means 5 for heating. When forming the interlayer insulating film, the interlayer insulating film is formed on the semiconductor substrate 6 by a thermal vapor deposition method with a mixed gas of tetraethoxysilane 3 and ozone 4 at a pressure higher than atmospheric pressure. Even when the flow rates of tetraethoxysilane 3 and ozone 4 are increased, the polymerization reaction in the gas phase sufficiently proceeds. It is possible to increase the film formation rate while ensuring the denseness of the film.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路の製造
方法に係り、特にテトラエトキシシラン及びオゾン（Ｏ
3 ）の混合気体による熱気相成長法及び半導体集積回路
の製造装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to tetraethoxysilane and ozone (O).
The present invention relates to a thermal vapor deposition method using a mixed gas of 3 ) and a semiconductor integrated circuit manufacturing apparatus.
【０００２】[0002]
【従来の技術】半導体集積回路の製造工程において、平
坦性が良く、４００℃前後の低温にて成膜可能なＴＥＯ
Ｓ−Ｏ3 熱ＣＶＤ酸化膜が、Ａｌ配線後の層間絶縁膜と
して検討されている。このＴＥＯＳ−Ｏ3 熱ＣＶＤ酸化
膜は、枚様式の開放型装置により大気圧下で成膜され
る。ここに、上記ＴＥＯＳ（テトラエトキシシラン）
は、Ｓｉ（ＯＣ2 Ｈ 5）4 を主成分とする反応性ガスの
略称である。2. Description of the Related Art In the process of manufacturing a semiconductor integrated circuit, TEO has good flatness and can be formed into a film at a low temperature of about 400.degree.
S-O 3 thermal CVD oxide film, has been studied as an interlayer insulating film after the Al wiring. This TEOS-O 3 thermal CVD oxide film is formed under atmospheric pressure by a single-plate open type apparatus. Here, the above TEOS (tetraethoxysilane)
Is an abbreviation for a reactive gas containing Si (OC 2 H 5 ) 4 as a main component.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
方法において絶縁膜の成膜速度は、ＴＥＯＳとＯ3 の流
量を増加させることにより速くなるが、その場合、気相
中における重合反応が不十分となり、形成された膜の緻
密性が劣化するという問題があった。即ち、膜の緻密性
を確保するためには、成膜速度を犠牲にし、枚様式の装
置としてはかなり遅い成膜速度で成膜を行わざるを得な
かった。However, in the conventional method, the film formation rate of the insulating film is increased by increasing the flow rates of TEOS and O 3 , but in that case, the polymerization reaction in the gas phase is insufficient. Therefore, there is a problem that the denseness of the formed film deteriorates. That is, in order to secure the denseness of the film, the film formation speed was sacrificed, and the film formation had to be performed at a considerably low film formation speed as a single-wafer apparatus.
【０００４】そこで本発明は、膜の緻密性を確保した上
で、成膜速度を速めることができる半導体集積回路の製
造方法及びその製造装置を提供することを目的とする。Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit and a manufacturing apparatus thereof, which can increase the film formation speed while ensuring the film denseness.
【０００５】[0005]
【課題を解決するための手段】本発明による半導体集積
回路の製造方法は、層間絶縁膜を成膜する際ＴＥＯＳと
Ｏ3 の混合気体を、反応容器内に大気圧よりも高い圧力
まで導入し、基板上に熱気相成長法によって成膜するよ
うにしたものである。According to the method of manufacturing a semiconductor integrated circuit of the present invention, a mixed gas of TEOS and O 3 is introduced into a reaction vessel to a pressure higher than atmospheric pressure when forming an interlayer insulating film. The film is formed on the substrate by the thermal vapor deposition method.
【０００６】[0006]
【作用】本発明によれば、ＴＥＯＳとＯ3 の混合気体の
圧力を、大気圧よりも高くしたことにより、ＴＥＯＳと
Ｏ3 の流量を増加させた場合でも、気相中における重合
反応が十分に進行する。従って膜の緻密性を確保しなが
ら、その成膜速度を速くすることができる。According to the present invention, the pressure of the mixed gas of TEOS and O 3 is set higher than the atmospheric pressure, so that the polymerization reaction in the gas phase is sufficiently performed even when the flow rate of TEOS and O 3 is increased. Proceed to. Therefore, the film formation rate can be increased while ensuring the denseness of the film.
【０００７】[0007]
【実施例】以下、図１乃至図３に基づき、本発明の半導
体集積回路の製造方法及びその製造装置の好適な実施例
を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a method of manufacturing a semiconductor integrated circuit and a manufacturing apparatus thereof according to the present invention will be described below with reference to FIGS.
【０００８】本発明方法において、先ずスパッタリング
法により、基板上に下層のＡｌ配線を１μｍの厚さで成
膜し、エッチンングによって配線パターンを形成する。
次に、ＴＥＯＳ−Ｏ3 熱ＣＶＤ酸化膜の成膜時に生じる
下地依存性を緩和するために、下地基板及びＡｌ配線が
露出した表面層をＨＭＤＳ液による処理を行うことによ
り疎水性にし、下地とＴＥＯＳ−Ｏ3 熱ＣＶＤ酸化膜と
の漏れ性を向上させる。In the method of the present invention, first, a lower layer Al wiring having a thickness of 1 μm is formed on a substrate by a sputtering method, and a wiring pattern is formed by etching.
Next, in order to alleviate the dependency on the underlying layer that occurs when forming the TEOS-O 3 thermal CVD oxide film, the surface layer on which the underlying substrate and the Al wiring are exposed is treated with an HMDS solution to make it hydrophobic, and TEOS-O 3 Improves leaktability with a thermal CVD oxide film.
【０００９】ここでＨＭＤＳは、Hexamethyl-Disiloxan
e （Ｓｉ2 Ｏ（ＣＨ3 ）6 ）を簡略化したものである
が、上記の場合このＨＭＤＳ処理を行う代わりに、薄い
プラズマＣＶＤ酸化膜を成膜する等により表面層が疎水
性となる処理を行ってもよい。Here, HMDS is Hexamethyl-Disiloxan
This is a simplified version of e (Si 2 O (CH 3 ) 6 ), but in the above case, instead of performing this HMDS treatment, a treatment for making the surface layer hydrophobic by forming a thin plasma CVD oxide film, etc. You may go.
【００１０】上記の基板を、図３に示した高圧処理が可
能な密閉型反応容器内に搬送し、９０００Åの高圧ＴＥ
ＯＳ−Ｏ3 熱ＣＶＤ酸化膜を成膜する。この時、ＴＥＯ
Ｓの流量は５０sccm、またＯ3 の流量は１０００sccmで
ある。反応容器内の圧力は５気圧であり、基板温度は４
００℃である。上記基板上に、ＴＥＯＳ−Ｏ3 熱ＣＶＤ
酸化膜の吸湿性を防止するために、ハバー膜としてプラ
ズマＣＶＤ酸化膜を１０００Åの厚さで成膜する。次に
上記の基板上に上層のＡｌ配線をスパッタリング法によ
って１μｍの厚さで成膜し、パターン成形する。The above-mentioned substrate was transferred into a closed reaction vessel capable of high-pressure treatment as shown in FIG.
Forming an OS-O 3 thermal CVD oxide film. At this time, TEO
The flow rate of S is 50 sccm, and the flow rate of O 3 is 1000 sccm. The pressure in the reaction vessel is 5 atm, and the substrate temperature is 4 atm.
It is 00 ° C. TEOS-O 3 thermal CVD is performed on the substrate.
In order to prevent the hygroscopicity of the oxide film, a plasma CVD oxide film having a thickness of 1000 Å is formed as a Huber film. Next, an Al wiring of an upper layer is formed into a film with a thickness of 1 μm on the above substrate by a sputtering method, and pattern formation is performed.
【００１１】図３は本発明方法を実施するための装置の
構成例を示している。図において、導入管１，２を介し
て密閉型反応容器４内にＴＥＯＳ及びＯ3 （符号３及び
４）が導入される。基板加熱用ヒータ５により加熱され
た基板６の近傍位置で上記ＴＥＯＳ及びＯ3 が化学反応
を起こし、該基板６上に絶縁膜が形成される。この場
合、密閉型反応容器１０内の圧力は、排気用配管７に接
続された圧力ゲージ８によって監視されていて、任意の
圧力になるように圧力調整バルブ９に信号を送出し、開
度を可変とすることにより一定の高圧力に保持される。
なお上記の場合、基板加熱をヒータによって行う代わり
に、例えばランプ照射等により行うこともできる。FIG. 3 shows a structural example of an apparatus for carrying out the method of the present invention. In the figure, TEOS and O 3 (reference numerals 3 and 4) are introduced into the closed reaction vessel 4 through the introduction pipes 1 and 2. The TEOS and O 3 cause a chemical reaction in the vicinity of the substrate 6 heated by the substrate heating heater 5 to form an insulating film on the substrate 6. In this case, the pressure in the closed reaction vessel 10 is monitored by the pressure gauge 8 connected to the exhaust pipe 7, and a signal is sent to the pressure adjusting valve 9 so that the pressure becomes an arbitrary pressure, and the opening degree is adjusted. By making it variable, a constant high pressure is maintained.
In the above case, the substrate may be heated by, for example, lamp irradiation instead of the heater.
【００１２】図１に、成膜時の反応容器内の圧力と成膜
速度の特性曲線を示す。圧力の上昇に伴い、原料ガスで
あるＴＥＯＳ及びＯ3 の分圧がそれぞれ増加するため、
その成膜速度は速くなる。また図２に、成膜時の反応容
器内の圧力とＴＥＯＳ−Ｏ3 熱ＣＶＤ酸化膜の膜密度の
特性曲線を示す。反応容器内の圧力の上昇に伴い、原料
ガスの反応容器内における滞留時間が増加し、気相中で
のＴＥＯＳ及びＯ3 の重合反応が十分に進行する。これ
により膜密度が増加して緻密な膜を形成することができ
る。FIG. 1 shows a characteristic curve of the pressure in the reaction vessel during film formation and the film formation rate. As the pressure rises, the partial pressures of the raw material gases TEOS and O 3 increase,
The film forming speed becomes faster. Further, FIG. 2 shows a characteristic curve of the pressure in the reaction vessel at the time of film formation and the film density of the TEOS-O 3 thermal CVD oxide film. As the pressure in the reaction vessel increases, the residence time of the raw material gas in the reaction vessel increases and the polymerization reaction of TEOS and O 3 in the gas phase sufficiently progresses. Thereby, the film density is increased and a dense film can be formed.
【００１３】従って本実施例の場合のように高圧力下
で、ＴＥＯＳ−Ｏ3 熱ＣＶＤ酸化膜の成膜を行った場
合、その成膜速度が速くなり且つ膜の緻密性が高い層間
絶縁膜を得ることができる。また図３に示した構造の装
置を用いることにより、高圧下でのＴＥＯＳ−Ｏ3熱Ｃ
ＶＤ酸化膜の成膜が可能になる。Therefore, when the TEOS-O 3 thermal CVD oxide film is formed under a high pressure as in the case of the present embodiment, the film formation rate is high and the interlayer insulating film with high density is formed. Can be obtained. Further, by using the device having the structure shown in FIG. 3, TEOS-O 3 heat C under high pressure can be obtained.
It becomes possible to form a VD oxide film.
【００１４】[0014]
【発明の効果】以上説明したように本発明によれば、こ
の種の膜の緻密性を確保しながら、成膜速度を速めるこ
とが可能になる等の利点を有している。As described above, according to the present invention, there is an advantage that the film forming speed can be increased while ensuring the denseness of this kind of film.
【図１】本発明の一実施例におけるＴＥＯＳ−Ｏ3 混合
ガスの圧力と成膜速度の特性曲線を示す図である。FIG. 1 is a diagram showing a characteristic curve of a pressure of a TEOS-O 3 mixed gas and a film formation rate in one example of the present invention.
【図２】本発明の一実施例におけるＴＥＯＳ−Ｏ3 混合
ガスの圧力と膜緻密性の特性曲線を示す図である。FIG. 2 is a diagram showing a characteristic curve of pressure and film density of a TEOS-O 3 mixed gas in one example of the present invention.
【図３】本発明の一実施例における半導体集積回路の製
造装置の概略構成例を示す図である。FIG. 3 is a diagram illustrating a schematic configuration example of a semiconductor integrated circuit manufacturing apparatus according to an embodiment of the present invention.
１，２ 導入管 ３ ＴＥＯＳ ４ Ｏ3 ５ 基板加熱用ヒータ ６ 基板 ７ 排気用配管 ８ 圧力ゲージ ９ 圧力調整バルブ1, 2 introduction pipe 3 TEOS 4 O 3 5 substrate heating heater 6 substrate 7 exhaust pipe 8 pressure gauge 9 pressure adjustment valve
Claims (2)
間絶縁膜を成膜する際、テトラエトキシシランとオゾン
の混合気体を、反応容器内に大気圧よりも高い圧力まで
導入し、基板上に熱気相成長法によって成膜することを
特徴とする半導体集積回路の製造方法。1. In the process of manufacturing a semiconductor integrated circuit, when forming an interlayer insulating film, a mixed gas of tetraethoxysilane and ozone is introduced into a reaction container up to a pressure higher than atmospheric pressure, and hot air is placed on a substrate. A method of manufacturing a semiconductor integrated circuit, comprising forming a film by a phase growth method.
トラエトキシシランとオゾンを、これらの混合気体が大
気圧よりも高い圧力になるように供給する反応ガス供給
手段と、前記反応容器内に配置された半導体基板を加熱
する加熱手段と、を備え、層間絶縁膜を成膜する際に、
大気圧よりも高い圧力のテトラエトキシシラン及びオゾ
ンの混合気体で半導体基板上に熱気相成長法によって層
間絶縁膜を成膜することを特徴とする半導体集積回路の
製造装置。2. In a semiconductor integrated circuit manufacturing apparatus, a reaction gas supply means for supplying tetraethoxysilane and ozone so that a mixed gas of these gases has a pressure higher than atmospheric pressure, and a reaction gas supply means arranged in the reaction vessel. A heating means for heating the semiconductor substrate, and when forming an interlayer insulating film,
An apparatus for manufacturing a semiconductor integrated circuit, comprising forming an interlayer insulating film on a semiconductor substrate by a thermal vapor deposition method using a mixed gas of tetraethoxysilane and ozone at a pressure higher than atmospheric pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13285593A JPH06326087A (en) | 1993-05-11 | 1993-05-11 | Method and apparatus for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13285593A JPH06326087A (en) | 1993-05-11 | 1993-05-11 | Method and apparatus for manufacturing semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06326087A true JPH06326087A (en) | 1994-11-25 |
Family
ID=15091105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13285593A Pending JPH06326087A (en) | 1993-05-11 | 1993-05-11 | Method and apparatus for manufacturing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06326087A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737697B2 (en) | 2000-04-11 | 2004-05-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method and system for fabricating the same |
| JP2004158880A (en) * | 2000-04-11 | 2004-06-03 | Matsushita Electric Ind Co Ltd | Semiconductor device manufacturing equipment |
-
1993
- 1993-05-11 JP JP13285593A patent/JPH06326087A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737697B2 (en) | 2000-04-11 | 2004-05-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method and system for fabricating the same |
| JP2004158880A (en) * | 2000-04-11 | 2004-06-03 | Matsushita Electric Ind Co Ltd | Semiconductor device manufacturing equipment |
| US6939725B2 (en) | 2000-04-11 | 2005-09-06 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating semiconductor device with capacitor covered by a TEOS-03 film |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100550351B1 (en) | A film forming method of a semiconductor device and a film forming device of a semiconductor device for performing the same | |
| US5484749A (en) | Manufacturing method of semiconductor device | |
| KR100292456B1 (en) | Method and apparatus for forming germanium doped BPSG thin film | |
| US5334552A (en) | Method for fabricating a semiconductor device having a multi-layered interconnection structure | |
| CN101597754B (en) | A method and apparatus for forming a high quality low temperature silicon nitride layer | |
| US6287989B1 (en) | Method of treating a semiconductor wafer in a chamber using hydrogen peroxide and silicon containing gas or vapor | |
| KR100308447B1 (en) | How to deposit a layer on a substrate | |
| US7888273B1 (en) | Density gradient-free gap fill | |
| KR100215376B1 (en) | Deposition of Ozone / Tetraethoxysilane Silicon Oxide Films with Reduced Surface Sensitivity | |
| JP3666751B2 (en) | Insulating film forming method and insulating film forming system | |
| KR20200104923A (en) | Processing methods for silicon nitride thin films | |
| US6054735A (en) | Very thin PECVD SiO2 in 0.5 micron and 0.35 micron technologies | |
| JPH04112531A (en) | Formation of capacitive insulating film | |
| JP2005116706A (en) | Heat treatment method and heat treatment apparatus | |
| JP4044637B2 (en) | A method for improving the interface quality of plasma-excited CVD films. | |
| JP3578155B2 (en) | Oxidation method of the object | |
| JP4319269B2 (en) | Thin film formation method by plasma CVD | |
| JP2702430B2 (en) | Method for manufacturing semiconductor device | |
| JPH04343456A (en) | Manufacture of semiconductor device | |
| JP2763203B2 (en) | Chemical vapor deposition equipment | |
| JPH10176273A (en) | CVD film forming method and CVD film forming apparatus | |
| JPH06333846A (en) | Thin film forming equipment | |
| WO2006014082A1 (en) | Thermal oxide formation apparatus and the method by chemical vapor deposition in wafer | |
| JPH05218005A (en) | Forming method for insulating film of thin film | |
| JPS59177919A (en) | Selective growth of thin film |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20011211 |