JPH06326123A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] A new technique that can selectively perform ion implantation only in a desired local region (eg, near the source or drain) without causing stress or the like when obtaining a high-performance MOSFET or the like. I will provide a. [Structure] An insulating film (gate oxide film 5) is formed on the semiconductor substrate 1.
To form a first electrically conductive film (Poly Si6a) and a second insulating film (SiN spacer 8) on the side wall thereof.
To form a diffusion layer of the first conductivity type (source / drain diffusion layers 9a, 9b), and the second diffusion layer is formed close to the films 6a, 8
Of the second conductive type diffusion layer (the pocket ion implantation region 12a, 12a, 11d), the insulating film 8 is removed, and the first and second electrically conductive films 6a, 11 are used as masks.
12b) is formed, and a third electrically conductive film (silicide 10) having a lower resistance than that of the second electrically conductive film 11 is formed on the surface of the second electrically conductive film 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. INDUSTRIAL APPLICABILITY The present invention can be applied to, for example, manufacture of MOSFET, and can be used to obtain a high performance device.

[0002]

2. Description of the Related Art In recent years, the first problem with miniaturization and high performance of MOSFETs is suppression of short channel effect. Self-aligned pocket ion implantation (Self-aligned Pocket Impl
antation) technology has been proposed. This technology selectively suppresses short channel effects without reducing carrier mobility in the channel region and increasing parasitic capacitance by improving the substrate concentration by selectively implanting ions only near the source and drain. Is to do.

The process flow of this prior art will be described with reference to FIGS. Each drawing shows an upper cross section of the silicon substrate of the Nch MOS transistor portion.

Referring to FIG. After the P ⁺ buried layer 2 is formed on the substrate 1, the P-epitaxial (P-Epi) layer 3 is formed. This allows retrograde wells (Retrog
radeWell) structure is realized, and latch-up resistance is improved.

Next, after forming a LOCOS oxide film for element isolation, a gate oxide film 5 is formed. LOCOS
Gate oxide film 5 of 400 to 500 nm as an oxide film
As a result, SiO ₂ having a film thickness of ₁₀ to 20 nm is formed.
N ⁺ Poly having a film thickness of 200 to 400 nm by CVD
Si is formed and the gate electrode 6 of the MOS transistor section is formed.
With the existing dry etching technology.
Process y Si.

Next, N ⁻ ion implantation IIA is performed on the MOS transistor portion to form LDD diffusion layers 7a and 7b.
At this time, LATI (Large Angle Tilt Implamtation)
The LDD diffusion layers 7a and 7b are overlapped with the gate electrode 6 by a technique.

Next, referring to FIG. 200 by CVD
By forming SiO ₂ with a film thickness of up to 400 nm and anisotropically etching with the existing dry etching technique,
LDD spacer 8a made of sidewall-shaped SiO ₂
To form.

Next, N ⁺ ions are implanted into the MOS transistor portion to form source and drain diffusion layers 9a and 9b.

Now referring to FIG. The gate electrode 6 and the source / drain diffusion layer 9 are formed by the silicide forming technique.
a, 9b surfaces are silicidized to form silicide layers 10a,
You get 10b.

Now referring to FIG. The LDD forming spacer 8a is removed, and pocket ion implantation IIB is performed. At this time, the gate electrode 6, the source / drain diffusion layers 9a,
The silicide film 10b on 9b functions as a mask, and pocket ions can be self-aligned only in the portions 12a and 12b immediately below the LDD regions 7a and 7b near the source and drain.

By performing heat treatment, the source and drain diffusion layers 9a and 9b are activated, and each electrode is formed using the existing wiring technique (not shown).

However, the above conventional method has the following problems. That is, since the silicide films 10a and 10b on the source and drain diffusion layers 9a and 9b are used as a mask during the pocket ion implantation shown in FIG. 13, it is necessary to form the silicide film to a thickness of about 200 nm. Due to the stress of the silicide films 10a and 10b, stress is applied to the source and drain regions, which causes leakage current and crystal defects.

[0013]

DISCLOSURE OF THE INVENTION The present invention solves the above-mentioned problems of the prior art and eliminates the problems such as stress generation.
It is an object of the present invention to provide a novel technique that can selectively perform ion implantation only in a desired local region (for example, in the vicinity of a source or a drain), thereby realizing a high-performance MOSFET or the like.

[0014]

According to a first aspect of the present invention, there is provided a step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, and a step of forming the first electrically conductive film. Forming a second insulating film on the sidewall, forming a diffusion layer of the first conductivity type, and forming a second electrically conductive film in proximity to the first electrically conductive film and the second insulating film And a step of removing the second insulating film, and a step of forming a diffusion layer of the second conductivity type by using the first and second electrically conductive films as a mask. This achieves the above object.

According to a second aspect of the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, and a second insulating film on a side wall of the first electrically conductive film. A step of forming a film, a step of forming a diffusion layer of the first conductivity type,
Forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film; removing the second insulating film; and masking the first and second electric conductive films As the second
A method of manufacturing a semiconductor device, comprising: a step of forming a conductive diffusion layer; and a step of forming a low-resistance third electric conductive film on the surface of the second electric conductive film. Is achieved.

According to a third aspect of the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, and a second insulating film on a side wall of the first electrically conductive film. A step of forming a film, a step of forming a diffusion layer of the first conductivity type,
Forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film; removing the second insulating film; and masking the first and second electric conductive films As the second
A step of forming a conductive type diffusion layer, a step of forming a third electric conductive film having a lower resistance than that on the surface of the second electric conductive film, and a step of forming a fourth insulating film on a side wall of the first electric conductive film. A method of manufacturing a semiconductor device, which includes a step of forming a film, by which the above object is achieved.

According to a fourth aspect of the present invention, the step of forming an insulating film on the semiconductor substrate, the step of forming the first electrically conductive film, and the second insulating film on the side wall of the first electrically conductive film. A step of forming a film, a step of forming a diffusion layer of the first conductivity type,
Forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film; removing the second insulating film; and masking the first and second electric conductive films As the second
A step of forming a conductive type diffusion layer, a step of removing at least a part of the surface of the second electric conductive film, and a third resistance having a lower resistance than the second electric conductive film in the exposed portion after the removal. A method of manufacturing a semiconductor device including a step of forming an electrically conductive film, by which the above-mentioned object is achieved.

According to a fifth aspect of the present application, a step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, and a second insulating film on a side wall of the first electrically conductive film. A step of forming a film, a step of forming a diffusion layer of the first conductivity type,
Forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film; removing the second insulating film; and masking the first and second electric conductive films As the second
A step of forming a conductive type diffusion layer, a step of removing at least a part of the surface of the second electric conductive film, and a third resistance having a lower resistance than the second electric conductive film in the exposed portion after the removal. A method of manufacturing a semiconductor device, which includes a step of forming an electrically conductive film and a step of forming a fourth insulating film on a side wall of the first electrically conductive film, thereby achieving the above object.

The invention according to claim 6 of the present application is characterized in that the diffusion layer of the first conductivity type is formed by diffusion from the second electrically conductive film. A method for manufacturing a device, which achieves the above object.

According to a seventh aspect of the present invention, in the semiconductor device according to any one of the first to sixth aspects, the second electrically conductive film is Si, Poly Si, a-Si or a laminated film containing these. A manufacturing method for achieving the above object.

The invention of claim 8 of the present application is any one of claims 1 to 7 in which the third electrically conductive film is Ti, W, Mo, Pt, Ni, Co or an alloy layer thereof or a silicide film thereof. A method of manufacturing a semiconductor device according to claim 1, wherein the above object is achieved.

According to a ninth aspect of the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, and a second insulating film on a side wall of the first electrically conductive film. A step of forming a film, a step of forming a diffusion layer of the first conductivity type,
Forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film; removing the second insulating film; and masking the first and second electric conductive films As the second
A method of manufacturing a semiconductor device, which includes a step of forming a conductive diffusion layer and a step of forming a fourth insulating film on a side wall of a first electrically conductive film, and thereby achieves the above object. .

According to a tenth aspect of the present invention, the step of forming an insulating film on a semiconductor substrate, the step of forming a first electrically conductive film, and the second insulating film on the side wall of the first electrically conductive film. A step of forming a film, a step of forming a diffusion layer of the first conductivity type,
A step of forming a second electric conductive film and a third insulating film in the vicinity of the first electric conductive film and the second insulating film; a step of removing the second insulating film; A method of manufacturing a semiconductor device, which includes the step of forming a diffusion layer of the second conductivity type by using the electric conductive film and the third insulating film as a mask, thereby achieving the above object.

According to the invention of claim 11 of the present application, a step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, and a second insulating film on a side wall of the first electrically conductive film. A step of forming a film, a step of forming a diffusion layer of the first conductivity type,
A step of forming a second electric conductive film and a third insulating film in the vicinity of the first electric conductive film and the second insulating film; a step of removing the second insulating film; Of the semiconductor device including a step of forming a diffusion layer of the second conductivity type by using the electric conductive film and the third insulating film as a mask, and a step of forming a fourth insulating film on a side wall of the first electric conductive film. Method,
This achieves the above object.

According to a twelfth aspect of the present invention, the semiconductor layer according to any one of the ninth to eleventh aspects is characterized in that the diffusion layer of the first conductivity type is formed by diffusion from the second electrically conductive film. A method for manufacturing a device, which achieves the above object.

The invention according to claim 13 of the present application is the semiconductor device according to any one of claims 9 to 12, wherein the second electrically conductive film is Si, Poly Si, a-Si or a laminated film containing these. A manufacturing method for achieving the above object.

According to a fourteenth aspect of the present invention, an insulating film formed in close proximity to the first electrically conductive film and the second insulating film,
The method of manufacturing a semiconductor device according to any one of claims 9 to 13, wherein the second electrically conductive film is an oxide film, which achieves the above object.

[0028]

According to the present invention, specifically, Si, Poly Si, a selectively formed in the source and drain regions during ion implantation into a local region such as formation of a MOS pocket region. -By performing ion implantation using an electrically conductive film such as Si as a mask, local ions such as pocket region formation are self-aligned without being adversely affected by leak current, crystal defect, etc. due to stress of the silicide film, which has been a problem in the past. It becomes possible to form an implantation region.

As a result, the substrate concentration can be improved by selectively implanting ions only in the desired region, for example, in the vicinity of the source and drain, without lowering the carrier mobility in the channel region and increasing the parasitic capacitance. The short channel effect can be suppressed and the process flexibility can be improved, and the leakage current due to the stress of the silicide film,
The adverse effects such as crystal defects are eliminated.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. However, it should be understood that the present invention is not limited to the embodiments.

Example 1 In this example, the present invention is applied to manufacture of a MOSFET. Please refer to FIG. 1 to FIG. These figures are cross-sectional top views of the silicon substrate of the Nch MOS transistor section.

Referring to FIG. After the P ⁺ buried layer 2 (see the buried layer 2 in FIGS. 10 to 13) is formed on the substrate 1, the epitaxial (P-Epi) layer 3 is formed. As a result, a retrograde well structure is realized and latchup resistance is improved.

Next, the LOCOS oxide film 4 for element isolation is formed.
After forming, the gate oxide film 5 is formed. LOCO
SiO ₂ having a film thickness of 400 to 500 nm is formed as the S oxide film 4 and 10 to 20 nm is formed as the gate oxide film 5. A laminated film of N ⁺ Poly Si and SiO ₂ having a film thickness of 200 to 400 nm is formed by CVD, and this SiO ₂ / Poly Si laminated film is processed by the existing dry etching technique to form the gate electrode 6 of the MOS transistor part Leave. 6a shows the Poly Si part, and 6b shows SiO ₂
Indicates a part.

Next, N ⁻ ions are implanted into the MOS transistor portion to form LDD diffusion layers 7a and 7b. At this time, the LDD diffusion layers 7a and 7b are overlapped with the gate electrode 6 by the LATI (Large Angle Tilt Implamtation) technique. A SiO ₂ film 50 is formed by CVD. With the above, the structure of FIG. 1 is obtained.

Next, referring to FIG. 200 by CVD
By forming SiN having a film thickness of up to 400 nm and anisotropically etching it by a dry etching technique, the spacers 8 for forming LDD made of sidewall SiN are formed. At this time, by performing high-selection-ratio etching, it is possible to leave the gate oxide film 5 in the source / drain formation portion in some cases.

Next, N ⁺ ions are implanted into the MOS transistor portion to form source and drain diffusion layers 9a and 9b. With the above, the structure of FIG. 2 is obtained.

Next, referring to FIG. Pol by CVD
By forming ySi and etching back using the existing dry etching technique, the PolySi film 11 having a film thickness of 200 to 400 nm remains only in the source and drain forming portions of the MOS transistor portion. At this time, a selective epitaxial technique may be used. This Poly Si film
11 functions as a mask during the subsequent pocket ion implantation. With the above, the structure of FIG. 3 is obtained.

By doing so, it is not necessary to form a thick silicide film as in the prior art, and problems such as leak current and crystal defects due to the influence of stress do not occur.

Source / drain diffusion layers 9a and 9b
May be formed by diffusion from the Poly Si film 11.

Next, referring to FIG. The spacer 8 for LDD formation is removed, and pocket ion implantation IIB is performed. At this time, the gate electrode 6 and the source / drain diffusion layers 9a, 9
The Poly Si film 11 on b functions as a mask, and pocket ions can be implanted in self-alignment only in the portions 12a and 12b immediately below the LDD regions near the source and drain. With the above, the structure of FIG. 4 is obtained.

Next, referring to FIG. If necessary, the mask Poly Si11 of the source and drain portions is etched to form a thin film. This is combined with the next silicidation,
The purpose is to reduce the connection resistance at the source and drain electrodes. In some cases, it is possible to remove all of the Poly Si11. At this time, the gate oxide film 5 in the source / drain formation portion and S on the side wall of the gate electrode are formed.
The iO ₂ film 50 functions as an etching stopper. Incidentally, when leaving the Poly Si11, in the process described with reference to FIG. 2, during the formation of the SiN spacer 8, a source, a drain region 9a, it is sufficient to remove the SiO ₂ 50 on 9b.

Next, the side wall 13 of the insulating film for separating the gate, source and drain electrodes is formed. At the same time, the source and drain electrodes are silicided to form a silicide film 10 such as TiSix. At this time, when the Poly Si11 on the source and drain electrodes remains, this serves as a buffer, and the source and drain diffusion layers 9a and 9b are formed.
Acts to reduce the stress on the By performing heat treatment,
The source and drain diffusion layers 9a and 9b are activated. With the above, the structure of FIG. 5 is obtained. Thereafter, each electrode (not shown) is formed by using the existing wiring technique.

As described above, according to this embodiment,
When manufacturing a high-performance MOS LSI, when forming the pocket regions 12a and 12b of the MOS transistor portion, the source,
Si, Poly S selectively formed in the drain region
By performing ion implantation using an electrically conductive film such as i, a-Si as a mask, it is formed in a self-aligned manner without being adversely affected by leak current, crystal defect, etc. due to the stress of the silicide film, which has been a conventional problem. It becomes possible.

As described above, in this embodiment, the step of forming the insulating film (gate oxide film 5) on the semiconductor substrate 1 and the step of forming the first electric conductive film (Poly Si 6a) (FIG. 1). A step of forming a second insulating film (SiN spacer 8) on the side wall of the first electrically conductive film (Poly Si6a), and a diffusion layer of the first conductivity type (source / drain diffusion layer 9).
a, 9b) (FIG. 2), and the second electric conductive film Poly S in close proximity to the first electric conductive film (Poly Si6a) and the second insulating film (SiN spacer 8).
The step of forming i11 (FIG. 3), the second insulating film (SiN
A step of removing the spacer 8) and a step of forming a diffusion layer (pocket ion implantation regions 12a, 12b) of the second conductivity type by using the first and second electrically conductive films (Poly Si 6a, 11) as a mask (FIG. 4), the second electrically conductive film (Poly)
A third electrically conductive film (silicide 10) having a lower resistance than that of Si11) is formed on the surface of Si11) (specifically, in the present embodiment, first, the second electrically conductive film Poly Si11 is removed from the surface). The thin film is formed, and the silicide 10 such as TiSix is formed on the thin film. However, such removal may not be performed.) The semiconductor device is manufactured in a mode including the step (FIG. 5), thereby achieving the object of the present invention. It is a thing.

In this embodiment, the first electrically conductive film (P
The structure of the embodiment includes a step (FIG. 5) of forming a fourth insulating film (source / drain separation SiO ₂ sidewall 13) on the sidewall of the poly Si6a).

In this embodiment, Poly S
At least a part of i11 is removed, that is, the second conductive type diffusion layer (the pocket ion implantation region) using the first and second electrically conductive films (Poly Si6a, 11) as a mask.
After the step of forming 12a, 12b), a step of removing at least a part from the surface of the second electrically conductive film (Poly Si11) is performed, and the exposed portion after the removal is removed from the second electrically conductive film by Low resistance third conductive film (silicide 10)
Was formed.

Further, in this embodiment, after the formation of the third electrically conductive film (silicide 10), the first electrically conductive film (Po
The configuration is such that it includes a step (FIG. 5) of forming a fourth insulating film (source / drain separation SiO ₂ sidewall 13) on the sidewall of the ly Si 6a).

The second electrically conductive film (Poly Si)
11) by diffusion from the first conductivity type diffusion layer (source,
The drain diffusion layers 9a and 9b) may be formed.

The second electrically conductive film is made of Si, Pol.
It may be ySi, a-Si or a laminated film containing these.

The third electrically conductive film is made of Ti, W, M.
It is possible to use o, Pt, Ni, Co, an alloy layer of these, or a silicide film of these.

Example 2 In this example, the present invention is applied to manufacture of a MOSFET. Please refer to FIG. 6 to FIG. These figures are cross-sectional top views of the silicon substrate of the Nch MOS transistor section.

Referring to FIG. After the P ⁺ buried layer 2 (see the buried layer 2 in FIGS. 10 to 13) is formed on the substrate 1, the epitaxial (P-Epi) layer 3 is formed. This realizes a retrograde well structure and improves latch-up resistance.

Next, a gate oxide film 5 is formed after forming a LOCOS oxide film 4 for element isolation. As the LOCOS oxide film 4, a gate oxide film 5 having a thickness of 400 to 500 nm is formed.
As a result, SiO ₂ having a film thickness of ₁₀ to 20 nm is formed.
A laminated film of N ⁺ PolySi and SiO ₂ is formed with a film thickness of 200 to 400 nm by CVD, and this SiO ₂ / Poly Si is processed by the existing dry etching technique to leave the gate electrode 6 of the MOS transistor portion. 6a indicates a Poly Si portion, and 6b indicates a SiO ₂ portion.

Next, N ⁻ ions are implanted into the MOS transistor portion to form LDD diffusion layers 7a and 7b. At this time, the LDD diffusion layers 7a and 7b are overlapped with the gate electrode 6 by the LATI (Large Angle Tilt Implantation) technique. With the above, the structure of FIG. 6 is obtained.

Next, referring to FIG. 200 by CVD
By forming SiN having a film thickness of up to 400 nm and anisotropically etching it by a dry etching technique, the spacers 8 for forming LDD made of sidewall SiN are formed.

Next, N ⁺ ions are implanted into the MOS transistor portion to form source and drain diffusion layers 9a and 9b. With the above, the structure of FIG. 7 is obtained.

Next, refer to FIG. 200 by CVD
A Poly Si film having a film thickness of up to 400 nm is formed and etched back by the existing dry etching technique to leave the Poly Si film 11 having this film thickness only in the source / drain formation portion of the MOS transistor portion. At this time, a selective epitaxial technique may be used.

The surface of the Poly Si film 11 is converted to SiO ₂ by oxidation to form a mask layer 11a. This mask layer 11
a functions as a mask at the time of implanting pocket ions later (however, even if the SiO ₂ mask layer 11a is not provided, Poly is used).
The Si film 11 alone can function as a mask. With the above, the structure of FIG. 8 is obtained.

By doing so, it is not necessary to form a thick silicide film as in the prior art, and problems such as leak current and crystal defects due to the influence of stress do not occur.

Next, referring to FIG. The spacer 8 for LDD formation is removed, and pocket ion implantation IIB is performed. At this time, the gate electrode 6 and the source / drain diffusion layers 9a, 9
The SiO ₂ mask layer 11a on b serves as a mask,
Only the portions 12a and 12b immediately below the LDD region near the drain can be self-aligned for pocket ion implantation.
With the above, the structure of FIG. 9 is obtained.

Then, although not shown, SiO ₂ is CVD-deposited.
Then, a sidewall of an insulating film for separating the gate, source and drain electrodes is formed by means such as etching back the entire surface, and the source and drain electrodes are further silicidized. At this time, the source and drain electrodes of Poly Si11
Serves as a buffer, and source / drain diffusion layers 9a and 9b
Also acts to reduce the stress on the By performing heat treatment,
The source and drain diffusion layers 9a and 9b are activated, and each electrode is formed by using the existing wiring technique (not shown).

As described above, in this embodiment, the step of forming the insulating film (gate oxide film 5) on the semiconductor substrate 1 and the step of forming the first electric conductive film (Poly Si 6a) (FIG. 6). A step of forming a second insulating film (SiN spacer 8) on the side wall of the first electrically conductive film (Poly Si6), and a diffusion layer of the first conductivity type (source / drain diffusion layer 9).
a, 9b) (FIG. 7) and the second electrically conductive film (Poly Si6a) and the second electrically conductive film (SiN spacer 8) in proximity to the second electrically conductive film (Poly Si6a).
The step of forming Si11) (FIG. 8), the second insulating film (S
The step of removing the iN spacer 8) and the second conductivity type diffusion layers (pocket ion implantation regions 12a, 12) using the first and second electrically conductive films (Poly Si 6a, 11) as a mask.
The object of the present invention is achieved by manufacturing a semiconductor device in a mode including the step (b) of forming (FIG. 9).

Further, in the present example, following the configuration of the above-described mode, the fourth insulating film (S) for separating the source and drain electrodes is formed on the side wall of the first electrically conductive film (Poly Si6a).
iO ₂ side wall. (Not shown) is formed.

In this embodiment, a step of forming an insulating film (gate oxide film 5) on the semiconductor substrate 1 and a step of forming a first electric conductive film (Poly Si6a) (FIG. 6),
A step of forming a second insulating film (SiN spacer 8) on the side wall of the first electrically conductive film (Poly Si6) and a step of forming a diffusion layer of the first conductivity type (source / drain diffusion layers 9a, 9b). (FIG. 7), the first electrically conductive film (Poly)
Si6a) and the second insulating film (SiN spacer 8), and a step of forming a _second electrically conductive film (Poly Si11) and a third insulating film (SiO2 11a) (FIG. 8); Removing the insulating film (SiN spacer 8) of the first and second electrically conductive films (Poly Si6).
a, 11) and the third insulating film (SiO ₂ 11a) as a mask, the second conductivity type diffusion layer (pocket ion implantation region 12)
The object of the present invention is achieved by manufacturing a semiconductor device in a mode including a step (FIG. 9) of forming a, 12b).

Further, in the present example, following the configuration of the above-described mode, the fourth insulating film (S) for separating the source / drain electrodes is formed on the side wall of the first electrically conductive film (Poly Si6a).
iO ₂ side wall. (Not shown) is formed.

In this embodiment, it is possible to adopt a mode in which the diffusion layer of the first conductivity type is formed by diffusion from the second electrically conductive film.

The second electrically conductive film is made of Si, Poly.
It can be Si, a-Si or a laminated film containing these.

Further, the insulating film formed close to the first electric conductive film and the second insulating film can be an oxide film of the second electric conductive film.

As described above, according to this embodiment,
When manufacturing a high-performance MOS LSI, when forming the MOS pocket regions 12a and 12b, ion implantation is performed by using as a mask an electrically conductive film such as Si, Poly Si, or a-Si selectively formed in the source and drain regions. Thus, it is possible to form the self-aligned structure without being affected by leakage current, crystal defect, etc. due to the stress of the silicide film, which has been a problem in the past.

[0070]

According to the present invention, there is provided a technique capable of selectively performing ion implantation only in a desired local region (for example, in the vicinity of a source or drain) without causing a problem such as stress caused by a silicide film. This makes it possible to realize a high-performance MOSFET or the like.

[Brief description of drawings]

1A to 1C are sectional views showing steps of Example 1 in order (1).

2A to 2C are sectional views showing the steps of Example 1 in order (2).

FIG. 3 is a sectional view showing the steps of Example 1 in order (3).

FIG. 4 is a sectional view showing the steps of Example 1 in order (4).

FIG. 5 is a sectional view showing the steps of Example 1 in order (5).

FIG. 6 is a sectional view showing the steps of Example 2 in order (1).

FIG. 7 is a sectional view sequentially showing the steps of the second embodiment (2).

8A to 8C are sectional views showing the steps of Example 2 in order (3).

9A to 9C are sectional views showing the steps of Example 2 in order (4).

FIG. 10 shows a conventional process (1).

FIG. 11 shows a conventional process (2).

FIG. 12 shows a conventional process (3).

FIG. 13 shows a conventional process (4).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 5 Insulating film (gate oxide film) 6a 1st electric conduction film (Poly Si) 8 2nd insulating film (SiN spacer) 9a, 9b 1st conductivity type diffusion layer (source, drain region) 10th Third conductive film (silicide) 10a Third insulating film (SiO ₂ ) 11 Second conductive film (Poly Si) 11a Fourth insulating film (mask layer) 12a, 12b Second conductivity type diffusion layer ( (Pocket ion implantation area)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9054-4M H01L 29/78 301 P

Claims (14)

[Claims] 1. A step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, a step of forming a second insulating film on a side wall of the first electrically conductive film, A step of forming a diffusion layer of one conductivity type, a step of forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film, and a step of removing the second insulating film. A method for manufacturing a semiconductor device, which includes a step of forming a diffusion layer of a second conductivity type using the first and second electrically conductive films as a mask. 2. A step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, a step of forming a second insulating film on a side wall of the first electrically conductive film, A step of forming a diffusion layer of one conductivity type, a step of forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film, and a step of removing the second insulating film. A step of forming a diffusion layer of the second conductivity type by using the first and second electrically conductive films as a mask, and a step of forming a third electrically conductive film having low resistance on the surface of the second electrically conductive film. A method for manufacturing a semiconductor device, including: 3. A step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, a step of forming a second insulating film on a side wall of the first electrically conductive film, A step of forming a diffusion layer of one conductivity type, a step of forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film, and a step of removing the second insulating film. A step of forming a second conductive type diffusion layer using the first and second electrically conductive films as a mask, and a step of forming a third electrically conductive film having a lower resistance than the second electrically conductive film on the surface of the second electrically conductive film. And a step of forming a fourth insulating film on the side wall of the first electrically conductive film. 4. A step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, a step of forming a second insulating film on a side wall of the first electrically conductive film, A step of forming a diffusion layer of one conductivity type, a step of forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film, and a step of removing the second insulating film. A step of forming a diffusion layer of the second conductivity type using the first and second electrically conductive films as a mask, a step of removing at least a part of the surface of the second electrically conductive film, and an exposure after the removal. A method of manufacturing a semiconductor device, comprising the step of forming a third electrically conductive film having a resistance lower than that of the second electrically conductive film in the portion. 5. A step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, a step of forming a second insulating film on a side wall of the first electrically conductive film, A step of forming a diffusion layer of one conductivity type, a step of forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film, and a step of removing the second insulating film. A step of forming a diffusion layer of the second conductivity type using the first and second electrically conductive films as a mask, a step of removing at least a part of the surface of the second electrically conductive film, and an exposure after the removal. A method of manufacturing a semiconductor device, comprising: a step of forming a third electrically conductive film having a lower resistance than that of the second electrically conductive film on a portion; and a step of forming a fourth insulating film on a side wall of the first electrically conductive film. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion layer of the first conductivity type is formed by diffusion from the second electrically conductive film. 7. The second electrically conductive film is made of Si, Poly S
i, a-Si or a laminated film containing these.
7. The method for manufacturing a semiconductor device according to any one of 6 to 6. 8. A third electrically conductive film is formed of Ti, W, Mo, P.
8. The method for manufacturing a semiconductor device according to claim 1, wherein t, Ni, Co, an alloy layer thereof, or a silicide film thereof is used. 9. A step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, a step of forming a second insulating film on a side wall of the first electrically conductive film, A step of forming a diffusion layer of one conductivity type, a step of forming a second electric conductive film in the vicinity of the first electric conductive film and the second insulating film, and a step of removing the second insulating film. Manufacturing a semiconductor device including a step of forming a diffusion layer of the second conductivity type using the first and second electrically conductive films as a mask, and a step of forming a fourth insulating film on a sidewall of the first electrically conductive film. Method. 10. A step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, a step of forming a second insulating film on a side wall of the first electrically conductive film, A step of forming a diffusion layer of one conductivity type; a step of forming a second electric conductive film and a third insulating film in the vicinity of the first electric conductive film and the second insulating film; A method of manufacturing a semiconductor device, comprising: a step of removing a film; and a step of forming a diffusion layer of a second conductivity type by using the first and second electrically conductive films and the third insulating film as a mask. 11. A step of forming an insulating film on a semiconductor substrate, a step of forming a first electrically conductive film, a step of forming a second insulating film on a side wall of the first electrically conductive film, A step of forming a diffusion layer of one conductivity type; a step of forming a second electric conductive film and a third insulating film in the vicinity of the first electric conductive film and the second insulating film; A step of removing the film, a step of forming a diffusion layer of the second conductivity type by using the first and second electric conductive films and the third insulating film as a mask, and a step of forming a fourth conductive film on a sidewall of the first electric conductive film. A method of manufacturing a semiconductor device, comprising the step of forming an insulating film. 12. The method of manufacturing a semiconductor device according to claim 9, wherein the diffusion layer of the first conductivity type is formed by diffusion from the second electrically conductive film. 13. The second electrically conductive film is made of Si, Poly S
10. i, a-Si or a laminated film containing these,
13. The method for manufacturing a semiconductor device according to any one of 1 to 12. 14. The semiconductor according to claim 9, wherein the insulating film formed close to the first electric conductive film and the second insulating film is an oxide film of the second electric conductive film. Device manufacturing method.