JPH06326311A - MIS type semiconductor device - Google Patents

Abstract

(57) [Summary] [Objective] By making the recombination center density, electrical conductivity, and diffusion length of electrons and holes a semiconductor having properties intermediate between those of amorphous semiconductors and crystalline semiconductors,
An MIS type semiconductor device having excellent characteristics is obtained. [Structure] By performing heat treatment of a semiconductor having an amorphous structure at a temperature equal to or lower than a crystallization temperature, the amorphous semiconductor is transformed into a semiconductor in which an amorphous material remains between the microcrystalline materials. The channel formation region in the MIS type semiconductor device is 0.1 mol atom%
To a semiconductor containing hydrogen in an amount of 5 to 5 mol atom%.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has a third structure which is an intermediate structure between an amorphous structure and a crystalline structure (including single crystal and polycrystal) and which is stable in terms of free energy. The present invention relates to a MIS type semiconductor device using a semiconductor having a state.

[0002]

2. Description of the Related Art Conventionally, an amorphous semiconductor has been defined as having a random interatomic distance and a random crystallographic arrangement. Further, the amorphous semiconductor is not always stable in terms of free energy as compared with the crystalline semiconductor (CRYSTALLINE SEMICONDUCTOR) because the interatomic distance and the crystallographic arrangement are random. Further, in such an amorphous semiconductor, there are a large number of unpaired bonds that are not chemically bonded to others due to the randomness. This dangling bond becomes a recombination center, which extremely shortens the lifetime of the carrier, and was most expected to be eliminated as a carrier killer.

As a method of removing such dangling bonds, neutralization with hydrogen or halogen has recently been known. That is, this method can be represented by the following reaction formula, assuming that the semiconductor is silicon. Si · + H · → SiH Si · + F · → SiF silane (SiH _4), with respect to silicon tetrafluoride (SiF _4), or a mixture gas, glow discharge or plasma CV
The film produced by the D method is 10 ²⁰ cm ^-3 to 10 ²² cm of amorphous semiconductor without addition of hydrogen and halogen.
^-3 as the density of recombination centers, while the recombination center densities are 10 ¹⁷ cm ^-3 to 10 ¹⁹ cm ^-3 and 10 ⁴ to 10 ⁶
It has been noted that the density of the recombination centers can be reduced to one-tenth.

[0004]

Amorphous semiconductors are not only easier to manufacture than single-crystal semiconductors, but also can form large-sized (large area and uniform) coatings. However, the amorphous semiconductor is not sufficient as a MIS type semiconductor device in terms of density of recombination centers and electric conductivity. Therefore, the amorphous semiconductor is
It was not suitable for use in MIS type semiconductor devices. In order to eliminate this defect, the amorphous semiconductor is annealed to promote crystallization. That is, the amorphous semiconductor was considerably inferior in characteristics as compared with the single crystal semiconductor, though the processing for promoting crystallization took time and labor. For example, an amorphous semiconductor has a density of recombination centers of 10 ¹³ cm ^-3 to 10 ¹⁶ cm ^-3 and an electric conductivity required for a MIS type semiconductor device.
10 ^-6 (Ωcm) ^-1 to 10 ^-4 (Ωcm) ^-1
It is difficult to obtain a diffusion length of 1 μm to 50 μm. In order to solve the above problems, the present invention provides
By making the recombination center density, the electric conductivity, and the diffusion length of electrons and holes to be a semiconductor having an intermediate property between an amorphous semiconductor and a crystalline semiconductor, M having excellent characteristics can be obtained.
An object is to provide an IS type semiconductor device.

[0005]

In order to achieve the above-mentioned object, a MIS type semiconductor device of the present invention comprises a source region (43, 43 ') and a drain region on a substrate (40) having an insulating surface.
(44, 44 ') and a semiconductor formed of a channel forming region (45, 45'), and a gate insulating film (42, 42 ') and a gate electrode (41, 4') on the channel forming region (45, 45 ').
1 ') are provided, and the channel forming regions (45, 4
5 ') is characterized by having a mixed state of crystal and amorphous by adding hydrogen or a halogen element. Further, the channel formation region (45, 45 ') in the MIS type semiconductor device of the present invention is characterized by being made of a semiconductor containing 0.1 mol% to 5 mol% of hydrogen.

[0006]

[Operation] The present invention is an MI using a semiconductor having both the advantages of a single crystal semiconductor and the advantages of an amorphous semiconductor.
The focus is on manufacturing an S-type semiconductor device.
The amorphous semiconductor that has been subjected to the predetermined heat treatment is transformed into a semiconductor in which the amorphous remains between the microcrystals. That is, since the semiconductor is amorphous which exists between the microcrystals, there is no interface between the microcrystals, and the crystal and the amorphous state are mixed, and electrons (electrons) or holes ( It becomes easy to move the hole). Therefore, for example, a semiconductor having an amorphous structure formed by a sputtering method, but by being transformed into a semiconductor having the above structure, an inexpensive and excellent electric conductivity was obtained. On the other hand, in the polycrystalline semiconductor, microcrystals are mixed and an interface exists between the microcrystals. Therefore, in the polycrystalline semiconductor, the movement of electrons or holes is hindered by the interface existing between the microcrystals, resulting in poor electric conductivity.

Further, the above semiconductor has a crystallized lattice structure, and its crystal has lattice distortion, and is in a third stable state different from an amorphous semiconductor or a single crystal semiconductor. Due to this lattice distortion, the light transition has the same direct transition as in the amorphous semiconductor,
It is advantageous as a type semiconductor. Furthermore, the applicant has found that even if the amount of hydrogen in the semiconductor is 0.1 mol% to 5 mol%, the electric conductivity is improved as compared with the amorphous semiconductor. That is, unlike the amorphous semiconductor, it is not necessary to add a large amount of hydrogen such as 20 mol atom% to neutralize dangling bonds, which is convenient for the MIS semiconductor device.

The present invention is a semiconductor (semi-amorphous) having the above structure.
Is defined as a semi-amorphous semiconductor, and a semiconductor device in which such a semiconductor and an amorphous semiconductor are adjacent to each other, a semi-amorphous semiconductor having such an intermediate structure and an amorphous semiconductor are locally controlled. Is characterized by having a higher conductivity than that of an amorphous semiconductor. The present invention allows an amorphous semiconductor to flow a current, particularly a pulsed current, in combination with the energy of photoexcitation by light irradiation or thermal excitation by heating to a specific passage, whereby the recombination center of this current by a dangling bond. Local multi-heating, quenching at such parts by recombining via
In particular, it is characterized by freezing (quinch) the material state by this extremely rapid cooling when the electric current is stopped.

That is, by activating this dangling bond and binding this dangling bond to another dangling bond in the vicinity thereof or to a dangling bond neutralized with other hydrogen or the like, a normal bond is formed. A semi-amorphous semiconductor (SEMI-AMORPHOUS) that has an interatomic distance, offsets the unpaired bonds, and freezes the neutralized state.
SEMICONDUCTOR). The present invention causes a reaction such as Si. + Si..fwdarw.Si-SiSi. + Si-H.fwdarw.Si-Si + H .., in a semiconductor, for example, silicon, to be physically caused by an overcurrent, and thus the density of unpaired bonds. In addition to reducing the amount of hydrogen, it is characterized by promoting the rearrangement of atoms in the short range order due to the heat generated by such a reaction.

[0010]

EXAMPLES Example 1 This example mainly describes the manufacturing principle and existence theory of a semi-amorphous semiconductor. FIG. 1 is a diagram for explaining an embodiment of the present invention. In FIG.
The semiconductor device is such that a conductor or semiconductor electrode (3) (METAL) is selectively formed in an amorphous structure on an insulating substrate (4) having an amorphous structure, and the semiconductor (1) (SEMICOND
UCTOR: A semiconductor that is a generic term for amorphous semiconductors or semi-amorphous semiconductors), a semi-transparent metal, or a counter electrode of a transparent electrode such as indium tin oxide (ITO).
(2) (METAL) is sequentially formed.
That is, the semiconductor device has a structure in which a metal, a semiconductor, and a metal are sequentially stacked (MSM structure).

The semiconductor (1) shown in FIG. 1 is a semiconductor containing silicon as a main component in this embodiment. This semiconductor (1)
First, silane (SiH ₄ ), SiF ₄ , SiH ₂ C
A glow discharge method using a silicide gas such as l ₂ or plasma C
It is formed by the VD method to a thickness of 0.1 μm to 10 μm, and particularly 1 μm to 5 μm. Instead of these methods, the semiconductor (1) is formed by sputtering method, vacuum deposition method, reduced pressure C
You may form using either method of VD method. The semiconductor (1) formed by any of these methods is formed as an amorphous semiconductor. Next, in the state immediately after the growth of the amorphous semiconductor (as grown state), a semi-amorphous semiconductor is mixed in the amorphous semiconductor in an amount of 1% to 50% to transform the amorphous semiconductor into a semi-amorphous semiconductor. Also, the amorphous semiconductor may be modified so that it approaches a 100% semi-amorphous semiconductor. In order to transform a part of the amorphous semiconductor into a semi-amorphous semiconductor, the semi-amorphous semiconductor is heated at a temperature of 450 ° C. to 700 ° C. which is 30 ° C. to 150 ° C. lower than the crystallization temperature. Completed as a semiconductor.

Thereafter, the transformed semi-amorphous semiconductor is mixed with H and He in a mixed atmosphere, for example, H ₂ : 0%.
To 10%, He: 90% to 60% mixed atmosphere, 1 MHz to 100 MHz or 1 GHz to
Plasma is generated with inductive energy having an output of 300 W to 3 KW at a frequency of 10 GHz to neutralize dangling bonds. He in the mixed atmosphere has the largest ionization voltage among all the atoms. This He is neon with a thermal conductivity of 0.123 Kcal / mHr C for sustaining the plasma state.
Compared with 0.0398, Argon 0.0140, Nitrogen 0.0206, etc., it is the largest of all gas elements, so in order to carry out soaking reaction,
Especially important.

The present embodiment further improves the existence probability of the semi-amorphous semiconductor in the amorphous semiconductor and grows it into a semiconductor in a state immediately after growth (as grown state) having an existence probability of approximately 100% of 95% or more. The purpose is to let. In the structure shown in FIG. 1, before and after the step of forming the amorphous semiconductor, each of a semiconductor electrode (3) heavily doped with a metal or impurities and a counter electrode (2) made of an impurity electrode is vacuum-deposited. Method, plasma CVD method or low pressure CVD method. A forward voltage of 1.0 Å / cm ² to 5 × 10 ⁴ Å / c is applied to each of the two electrodes (3) and (2).
100 msec in the range of m ² , especially 0.01 sec to 2 sec,
A current, especially a pulse current, is passed.

At this time, the amorphous semiconductor has an electrical conductivity σ of 10 ⁻⁹ (Ωcm) ⁻¹ to 10 ⁻¹² (Ωcm) ^{−1 when} it is not doped with impurities, which is equivalent to an insulating property. However, when light is irradiated to a predetermined portion of the amorphous semiconductor in a spot shape having a diameter of 1 μm to 1 mm with an illuminance of 10 ⁴ LX or more, the electrical conductivity σ is increased at the portion where the light irradiation is performed. Is 10 ^-1 (Ωcm) ^-1 to 10 ^-6 (Ω
cm) ^-1 and 10 ⁶ times increase. When this photocarrier is used, a large current can flow only in the portion where the light irradiation is performed, and the amorphous semiconductor is transformed into a semiamorphous semiconductor. Furthermore, since no current flows in the periphery adjacent to the region transformed into this semi-amorphous semiconductor, the structure as an amorphous semiconductor remains.

Further, regarding the characteristics of this semi-amorphous semiconductor, an example thereof will be shown. FIG. 2 is a diagram showing the relationship between the electric conductivity and the absolute temperature of the semi-amorphous semiconductor of this example. In FIG. 2, the vertical axis represents the electrical conductivity σ, in particular, the electrical conductivity σ of dark current without light irradiation, which is a logarithm (Log).
Is indicated by the coordinates, and the abscissa indicates the absolute temperature. A curve (10) shown in FIG. 2 is an electric conductivity characteristic of an amorphous semiconductor. This amorphous semiconductor has 3 × 10 A / cm ² , 10 ³ A
Applying a current of / cm ² for 0.5 seconds each, the curve (1
0) changes to curves (11) and (12) respectively. That is, at room temperature, the electric conductivity of an amorphous semiconductor is 10 ^-10 (Ωcm) ^-1 , whereas the electric conductivity of a semi-amorphous semiconductor is 10 ^-6 to 10 ^-10.
It can be increased by ^-4 (Ωcm) ^-1 and 10 ⁴ times.

Further, the amorphous semiconductor is a V-valent impurity such as As and Sb which are metallic impurities having a large atomic weight, a III-valent impurity such as Ga and In, and Sn and P.
IV valence impurities such as b from 0.1 mol% to 10 mol%
When (atomic%), for example, 1.2 mol% (atomic%) is added, the electric conductivity characteristic of the curve (10 ') shown in FIG. 2 is obtained. Similarly, the amorphous semiconductor to which this impurity is added shows a curve when a current for semi-amorphous semiconductor is applied.
From (10 ′), the electric conductivity characteristics shown in the curves (13) and (14) can be obtained. As a result, the metallic impurities having a large atomic weight of III, IV, and V each serve as an auxiliary agent for promoting the formation of a semi-amorphous semiconductor. On the other hand, B having the smallest atomic weight among III valences,
Impurities such as P having a small atomic weight among V valences have no auxiliary action, and therefore have different characteristics as impurities.

FIG. 3 is a diagram showing the relationship between the spin density and the current density of the semi-amorphous semiconductor of this embodiment. Figure 3
In, the vertical axis represents the spin density of the dangling bonds in electron spin resonance (ESR), and the horizontal axis represents the current density. Application time to semi-amorphous semiconductor is 0.1 seconds, 0.5 seconds, 2.5
When changing the current for each second and adding the current, the curves (17), (16),
Each of (18) can be obtained, and the semi-amorphous semiconductor also shows an increase in electrical conductivity from the measurement results. That is, the number of dangling bonds in the amorphous semiconductor is reduced by the semi-amorphous semiconductor. The semi-amorphous semiconductor has an improved electric conductivity σ, which in turn can improve the carrier mobility by 10 ³ to 10 ⁶ times. However, when these electron beam diffraction images were taken, these semiconductor films had a crystallized lattice structure, and strain was present in the crystal lattice.

Further, in the amorphous semiconductor, the contained hydrogen contained 20 mol% (atomic%), but this hydrogen content was reduced by the semi-amorphous semiconductor, and
Only about 1 to 5 mol% (atomic%) was mixed. Therefore, it is considered that the result of the electron spin resonance is that hydrogen is not neutralized by the dangling bonds, but silicon (Si) is mutually bonded and neutralized.

From the above characteristics, the film formed of a so-called amorphous semiconductor has a structure in which the distance between crystal lattices and the position of the crystal lattice are random, whereas the film formed of a semi-amorphous semiconductor has a stable free energy. Further, it is assumed that it has a third stable point which is different from the crystal structure which is stable in terms of thermal energy in terms of free energy. Figure 4 shows the coordinates of the general phase space (CO
It is a figure which shows the relationship between NFIGURATIONAL COORDINATE) and free energy. The horizontal axis of FIG. 4 represents coordinates of a general phase space, and the vertical axis represents free energy. In FIG. 4, three states of amorphous semiconductors (21) and (21 ′), semi-amorphous semiconductor (22), and crystalline semiconductor (23) are shown. The semi-amorphous semiconductor (22) is amorphous semiconductor (21) and It was found that the state is the third stable state rather than the metastable state for converting from (21 ′) to the crystalline semiconductor (23).

In FIG. 2, the substrate temperature (temperature of the insulating substrate (4)) is higher than room temperature by 200 ° C. or 400 ° C.
In each case, low current densities of 3 A / cm ² and 10 ² A / cm ² are obtained, respectively, as shown by the curves (11) and (12) at room temperature. The feature of this embodiment is that a photocarrier is generated by local light irradiation (light spot) when an electric current is applied to the amorphous semiconductor, and the light spot is scanned (scan), and the semiconductor is moved according to the scanned optical path. To make an amorphous semiconductor. In addition, at this time, it is extremely effective to promote thermal excitation by heating together, which is practically practical and which applies a current uniformly to a wide region. The current density in this embodiment means the average of the densities of currents flowing per unit area. The current density means the density of the current locally flowing in the region under the electrode. In other words, the present embodiment can be applied not only to a small area of 1 mm × 1 mm or less, but also to a large area of 10 cm × 10 cm.

As described above, in FIG. 1, the counter electrode is
The semiconductor (1) immediately below (2), that is, the region (20) is a semi-amorphous semiconductor. Further, since the semiconductor (1) in the region (19) shown in FIG. 1 does not have the lower electrode (3), the semiconductor (1) which is in the state immediately after growth (as grown state) or the amorphous semiconductor and the semi-amorphous semiconductor are It becomes a mixed semiconductor. Furthermore, the semiconductor (1) in the region (19 ') is
It has an intermediate structure between the amorphous semiconductor immediately after growth (as-grown state) and the semiconductor (1) in the region (20).

Although the semiconductor (1) shown in FIG. 1 is made of amorphous silicon, Ge, GeSix (0 <x <1), Si
_{O 2- x (0 <x <} 2), SiC 1- x (0 <x <1), Si 3 N 4- x (0 <x <4)
The same can be applied to a compound or mixture such as The semiconductor according to the present invention also includes a semi-insulator in the limit that allows a current to flow. Thus, in the case of silicon, the amorphous semiconductor had a carrier diffusion length of only about 300 Å. In contrast, the semi-amorphous semiconductor of this example has a carrier diffusion length of 1 μm to 50 μm.
Increased ¹⁰⁴ times, the carrier diffusion length 1/10 monocrystalline
I was able to get closer to 1/1000.

When a semi-amorphous semiconductor was examined by an electron beam or X-ray diffraction method, the interatomic distance of this semi-amorphous semiconductor was found to be 2.2 in silicon.
It was Å or 2.5 Å, which had a strain extending in the long distance direction, while roughly matching the interatomic distance of 2.3 Å of the single crystal. However, the crystal structure of a semi-amorphous semiconductor does not have the same diamond structure as a single crystal in the long range order, but has a crystalline diamond structure having strain in the single crystal. The crystal structure of the semi-amorphous semiconductor has a diamond structure on the short range order,
In the range examined by the diffraction image, the peak position was deviated from that of the single crystal, and there were many lattice distortions. Due to this lattice distortion, it was found that the light transition of the semi-amorphous semiconductor has a direct transition like the amorphous semiconductor, unlike the indirect transition of single crystal silicon.

Example 2 Example 2 relates to a MIS-FET (insulated gate type field effect semiconductor device). MIS of this embodiment
FIG. 6 is a vertical cross-sectional view for explaining what has an FET structure of an inverter and is provided on a substrate. MIS-F shown in FIG.
ET is SOS (SILICON ON SAPPHIRE or SILICONO
N SILICON) structure. This SOS structure has about 1 oxide layer on a glass, ceramic or silicon substrate.
A silicon semiconductor layer in which an amorphous semiconductor is not doped with impurities is formed on an insulating substrate (40) having a thickness of μm and having a so-called amorphous surface. MIS-FE
T is formed of a semi-amorphous semiconductor by selectively making a part of the silicon semiconductor layer a semi-amorphous semiconductor.

This MIS-FET is formed by the following method. First, according to the method shown in Example 1,
An amorphous semiconductor having a thickness of 0.3 μm to 1 μm is manufactured. Then, the amorphous semiconductor is provided with a masking film that has a masking action against oxidizing gas and that can bury the oxide film by oxidizing the other part, that is, silicon nitride (42).
It is selectively formed to a thickness of 0.2 μm to 0.5 μm. Next, using the mask coating, a part of the surface of the amorphous semiconductor is selectively oxidized to form an oxide (49) buried in a part of the surface of the amorphous semiconductor.

After that, the mask film is removed, and the gate insulating films (42) and (42 ') are formed again on the surface of the amorphous semiconductor by a high pressure or plasma oxidation method to a thickness of 500Å to 1000Å. Next, a silicon semiconductor film for the gate electrodes (41) and (41 ′) is formed as an amorphous semiconductor or a semi-amorphous semiconductor on the surfaces of the gate insulating films (42) and (42 ′). Particularly, in the case of a semi-amorphous semiconductor, Sb and As, which are conductive metals, are added to make them N-type, and In and Ga, respectively, to make them P-type, are added by 0.1 mol% to 5 mol% (atomic%). . Thereafter, the silicon semiconductor film for the gate electrodes (41) and (41 ') is photo-etched, and the gate electrodes (41) and (41') and any electrode lead of the source region or the drain region are etched.
(50), (50 ') and (50'') are formed.

Next, in the case of an N-channel type MIS-FET, the gate electrode (41) is used as a mask and self-alignment is performed to dope As by the ion implantation method, and the source regions (43), (4
3 ') and drain regions (44) and (44') are formed. In the MIS-FET, the output electrode lead (50 ') connected to each of the drain regions (44) and (44') is overcoated (interlayer) with respect to the V _DD electrode lead (50). Upper layer lead formed on the insulating film)
Connected to (48). MIS-FE configured in this way
According to the first embodiment, T is a semi-amorphous semiconductor in each of the channel forming regions (45) and (45 ') when a pulse current is passed, and at the same time, the source regions (43), (43') and the drain are formed. Each of the regions (44) and (44 ') is also made into a semi-amorphous semiconductor. Thus, the channel forming region (4
5), (each 45 '), an intrinsic or substantially consists of intrinsic silicon semiconductor, 10 ^-6 ([Omega] cm) ^-1 to 10 ^-4 ([Omega] cm showed that electrical conductivity in Example 1) ^- Could be ¹ . Further, as shown in Example 1, unnecessary dangling bonds were eliminated by hydrogen annealing.

The MIS-FET is loaded with a MIS-F for loading.
When used as an ET, the gate electrode (41 ') is formed as an N + type to make it a depletion type. Also,
When the MIS-FET is used as a driver MIS-FET, the gate electrode (41) is formed of a P + type different from the respective conductivity types of the source region (43) and the drain region (44). The MIS-FET of this embodiment is a depletion type MIS-FET (DIS
-FET). Further, in the MIS-FET, when minority carriers are used, each of the channel forming regions (45) and (45 ′) of the N-channel MIS-FET is formed into a P type. In addition, this embodiment shows an example in which an inverter is composed of MIS-FETs.
An integrated circuit (IC) in which a plurality of S-FETs or inverters are integrated may be configured. In addition, the present invention relates to MIS
-Not limited to FETs, integrated circuits (ICs) that integrate bipolar transistors, SIT (STATIC INDUCTION TRA)
Application to NSISTER), IIL (INTEGRATED INJECTION LOGIC), etc. is also possible. In this case, element regions such as bipolar transistors and diodes are made of a semi-amorphous semiconductor, and part or all of the isolation region around the element region is made of an amorphous semiconductor.

According to this embodiment, an amorphous semiconductor can be easily changed to a semi-amorphous semiconductor only by applying light and current, so that regions having different electric conductivity can be easily formed. As is clear from the above description, the provision of the amorphous semiconductor and the semi-amorphous semiconductor of the present invention in the same semiconductor means that the MIS photoelectric conversion device and the MIS-FET which are the embodiments thereof are provided.
Can be applied to integrated circuits, optical memories, etc.
Further, many applications based on the same technical idea are possible.

[0030]

According to the present invention, a semiconductor having an amorphous structure formed on a substrate is heated at a temperature not higher than a crystallization temperature, so that a semiconductor having an intermediate structure between an amorphous semiconductor and a crystalline semiconductor is electrically conductive from an amorphous semiconductor. Improved the rate. Further, according to the present invention, since the above semiconductor is used for the channel formation region, it is possible to obtain the MIS type semiconductor device which is inexpensive and has excellent characteristics. In addition, since the above-mentioned semiconductor is in a mixed state of crystal and amorphous, it was possible to directly transit light similarly to the amorphous semiconductor, and to obtain a MIS type semiconductor having excellent characteristics.
Furthermore, even if the amount of hydrogen in the semiconductor is 0.1 mol% to 5 mol%, the electric conductivity is improved as compared with the amorphous semiconductor, and the MIS semiconductor device having excellent characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between the electrical conductivity and the absolute temperature of the semi-amorphous semiconductor of this example.

FIG. 3 is a diagram showing the relationship between the spin density and the current density of the semi-amorphous semiconductor of this example.

FIG. 4 is a diagram showing a relationship between general phase space coordinates and free energy.

FIG. 5 is a vertical cross-sectional view for explaining the MIS-FET of this embodiment having an inverter structure and provided on a substrate.

[Explanation of symbols]

 40 ... Insulating substrate 41, 41 '... Gate electrode 42, 42' ... Gate insulating film 43, 43 '... Source region 44, 44' ... Drain region 45, 45 '... Channel forming region 46, 46 '... Isolation region 50, 50' ... Electrode lead

Claims (2)

[Claims] 1. A semiconductor device comprising a semiconductor having a source region, a drain region, and a channel forming region on a substrate having an insulating surface, and a gate insulating film and a gate electrode provided on the channel forming region, wherein the channel A MIS type semiconductor device characterized in that the formation region has a mixed state of crystal and amorphous to which hydrogen or a halogen element is added. 2. A semiconductor device in which a semiconductor having a source region, a drain region, and a channel forming region is provided on a substrate having an insulating surface, and a gate insulating film and a gate electrode are provided on the channel forming region. The formation region is formed of a semiconductor containing hydrogen in an amount of 0.1 mol% to 5 mol%, and a MIS type semiconductor device.