JPH06333955A - Field effect transistor and its manufacture - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a field-effect transistor having excellent high frequency characteristics by reducing gate parasitic capacitance and parasitic resistance. [Constitution] The recess 82 has a bottom surface 82A and a first taper surface 8
2B, the second tapered surface 82C, and the lower end of the pillar portion 1A of the gate electrode 1 is on the bottom surface 82. Also,
By matching the lower edge of the side wall of the pillar 1A with the lower edge of the first tapered surface 82B, the gate parasitic capacitance and parasitic resistance can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly to a field effect transistor such as a high electron mobility transistor (HEMT) having a recess formed in a portion where a so-called T-shaped gate is provided. Involve

[0002]

2. Description of the Related Art Conventionally, as a method for manufacturing a field effect transistor of this type, there is a method as shown in FIGS. 8 (A) and 8 (B). In this method, as shown in FIG. 8A, a resist (or an insulating film may be used) 21 is patterned on the semiconductor layer 20, and recess etching is performed using the resist 21 as a mask to form the recess 20A in the semiconductor layer 20. Form. next,
After depositing the gate metal as it is, the gate metal is patterned to form a T-shaped gate 22 as shown in FIG.
To form. However, in this manufacturing method, as shown in FIG. 8C, even if the resist 21 or the insulating film is slightly recessed by recess etching, the pillar portion 22A of the T-shaped gate 22 rides on the upper portion of the sidewall of the recess 20A. Therefore, there is a problem that the parasitic capacitance increases.

Further, as a method for providing a distance between the recess side wall and the pillar of the T-shaped gate, a method as shown in FIGS. 9A and 9B is known. In this method, as shown in FIG. 9A, an insulating film 23 and a resist 24 are formed on the semiconductor layer 20, and then the resist 24 is patterned,
Using this as a mask, an opening is formed in the insulating film 23, and then recess etching is performed. Next, as shown in FIG. 9B, a T-shaped gate 22 is formed by depositing a metal and patterning the metal. In this method, as shown in FIG. 9 (B), the column 22A of the T-shaped gate 22 and the side wall of the recess 20A can be provided with a distance d to reduce the parasitic capacitance, but if this distance d is large. There is a problem that it causes an increase in parasitic resistance. As described above, in order to reduce both the parasitic capacitance and the parasitic resistance, it is extremely difficult to control the gate position in the recess.

On the other hand, as shown in FIG. 10, when wet etching is performed using the insulating film 23 or the like as a mask, stress may cause abnormal etching at both ends 20B of the recess 20A, resulting in etching deeper than the central portion. However, this also causes an increase in parasitic resistance.

The problem to be solved by the present invention is what kind of means should be taken to reduce the gauge parasitic capacitance and the source parasitic resistance to improve the high frequency characteristics.

[0006]

According to a first aspect of the present invention, a recessed groove-shaped recess is formed on the surface of a semiconductor layer.
In the field effect transistor in which the gate electrode is erected on the bottom of the recess, the side wall of the recess is formed by a plurality of tapered surfaces so that the inclination increases in multiple steps from the groove bottom side to the groove top side. Is the solution. Further, the invention according to claim 2 is characterized in that the side wall of the recess is formed by a two-step tapered surface. Further, the invention according to claim 3 is characterized in that the side wall lower end edge of the gate electrode is substantially located at the side wall lower end edge of the recess. Further, the invention according to claim 4 is characterized in that the lower end portion of the gate electrode is located closer to the source. The invention according to claim 5 of this application is
A step of sequentially forming a first insulating film and a second insulating film on the semiconductor layer, and after applying a resist on the second insulating film, exposure and development are performed to form an opening of a predetermined width. And a step of performing anisotropic etching using the resist as a mask to open the second insulating film, and wet etching the first insulating film and the semiconductor layer through the opening of the second insulating film. Etching in the depth direction of the semiconductor layer while maintaining the bottom structure of the primary recess with a step of forming a primary recess in the semiconductor layer and an etching solution that selectively etches only the semiconductor layer. And forming a secondary recess, and depositing a gate metal on the second insulating film, and then patterning the gate metal to form a T-shaped gate. , As a solution.

Further, the invention according to claim 6 of this application comprises a step of forming an insulating film on the semiconductor layer, a step of sequentially laminating a positive resist layer and a negative resist layer on the insulating film, and After forming a first opening having a width corresponding to the width of the wide head of the T-shaped gate in the negative resist layer,
Forming a second opening having a width corresponding to the width dimension of the pillar of the T-shaped gate in the positive resist layer in the first opening, and through the first opening and the second opening A step of performing wet etching to etch the insulating film and the semiconductor layer to form a primary recess, and an etching solution that selectively etches only the semiconductor layer maintains the bottom structure of the primary recess. And a step of forming a secondary recess by performing etching to the depth method of the semiconductor layer, and a step of removing the positive resist layer and the negative resist layer and lifting off after the gate metal is deposited, The solution is to provide. Further, the invention according to claim 7 is characterized in that the gate metal is obliquely vapor-deposited so as to be deposited closer to the source in the secondary recess. Further, the invention according to claim 8 is characterized in that the semiconductor layer is made of a III-V compound containing arsenic as a group V element, the insulating film on the semiconductor layer is made of SiO ₂ , and the insulating film and the semiconductor layer are Is subjected to wet etching using a mixed solution of hydrofluoric acid, hydrogen peroxide solution and ammonium fluoride as an etching solution to form a primary recess.

[0008]

In the invention according to claims 1 to 3 of the present application, since the sidewall of the recess becomes multisteply inclined from the groove bottom side to the groove top side, the sidewall of the gate electrode approaches the recess sidewall. Can be prevented, and an increase in parasitic capacitance can be prevented. Further, if the side wall lower end edge of the gate electrode is located substantially at the side wall lower end edge of the recess, an increase in parasitic resistance can be prevented.

In the invention according to claim 4 of this application, the lower end of the gate electrode is located closer to the source, so that the source resistance is reduced.

In the invention according to claim 5 of this application, since the second insulating film is anisotropically etched using the resist as a mask, the width dimension of the opening is the same as the planned width of the opening of the resist. Become. Further, by performing the wet etching through the opening of the second insulating film, the primary recess is formed while the surface of the second insulating film having the opening width is maintained. Furthermore, by performing etching with an etchant that selectively etches only the semiconductor layer, the etching proceeds with the surface of the planned width maintained,
A secondary recess is formed in which the side wall is a two-step tapered surface. Then, by depositing the gate metal on the second insulating film, the gate electrode can be formed in a self-aligned manner on the bottom surface of the secondary recess having a predetermined width.

According to the invention of claim 6 of this application, a gate electrode having the same structure as that of claim 5 can be formed by the lift-off method.

Further, in the invention according to claim 7 of this application, the gate metal is deposited in the secondary recess toward the source, so that the lower end portion of the gate electrode is located toward the source and the source resistance is increased. Reduce.

Next, in the invention of claim 8 of this application, the semiconductor layer made of a III-V compound containing arsenic as a group V element and the insulating film made of SiO ₂ are hydrofluoric acid and hydrogen peroxide solution. It becomes possible to perform etching with a mixed solution of ammonium fluoride and ammonium fluoride, and it is possible to form a primary recess.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The field effect transistor according to the present invention and the manufacturing method thereof will be described in detail below with reference to the embodiments shown in the drawings.

(Embodiment 1) In this embodiment, the present invention is applied to a HEMT as a field effect transistor. FIG. 1 is a plan view showing the entire chip pattern of this embodiment, and FIG. 2 is a sectional view taken along line XX of FIG. 1 in FIG.
Is a gate electrode, 2 is a source, and 3 is a drain. In FIG. 2, 4 is a channel layer made of i-GaAs, and 5 is 2
Dimensional electron gas, 6 is an electron supply layer made of Si-doped N-AlGaAs, and 7 is a cap layer made of N ⁺ -GaAs. The illustrated channel layer 4 to the gap layer 7 are semiconductor layers, and a recess 82 is formed from the surface for such a structure. The recess 82 is formed in a groove shape along the longitudinal direction of the gate electrode 1,
As shown in FIG. 1, the bottom surface 82A and the first tapered surface 82
B, 82 and second tapered surfaces 82C, 82C. Further, a SiO ₂ film 9 as a first insulating film is formed on the cap layer 7, and a SiN film 10 as a second insulating film is formed on the SiO ₂ film 9. The SiO ₂ film 9 has an opening 9a having substantially the same width as the recess 82 formed in the semiconductor layer, and the recess 82 is exposed by this opening 9a. Then, in the SiN film 10, an opening 10a having the same width as the bottom surface 82A of the recess 82 is formed right above the bottom surface 82A. The gate electrode 1 is
The pillar portion 1A is erected from the opening 10a to the bottom surface 82A, and the wide portion 1B is formed on the SiN film 10.

In the structure of this embodiment, the first taper surface 82
B and 82B are formed from the lower end side edge of the pillar portion 1A of the gate electrode 1, and the second tapered surface 82C is formed from the upper end edge of the first tapered surface 82B. Therefore, the parasitic resistance is reduced. In addition, the inclination of the second tapered surface 82C is the first
It is larger than the inclination of the tapered surface 82B. Recess 8
2 has a structure in which the pillar 1A of the gate electrode 1 is surrounded by a space. Therefore, the parasitic capacitance is reduced.

Next, the manufacturing process of the field effect transistor of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 3A, a SiO ₂ film 9 is formed on the semiconductor layer S by a CVD method to a film thickness of 0.1 to 0.2.
The film is formed to have a thickness of μm. Then, a SiN film 10 is formed on the SiO ₂ film 9 by the CVD method in a thickness of 0.1 to 0.2.
The film is formed to have a thickness of μm. Next, after applying a resist 11 on the SiN film 10, an opening 11 equal to the pillar width (0.1 to 0.2 μm) is formed at a position for forming the pillar of the gate electrode.
A is formed on the resist 11. This resist patterning can form a fine pattern by, for example, EB direct drawing.

Next, anisotropic dry etching such as reactive ion etching (RIE) is performed using the resist 11 as a mask, and the SiN film 1 is formed as shown in FIG. 3 (B).
An opening 10a is formed at 0. After that, the resist 11 is removed as shown in FIG. It should be noted that this anisotropic dry etching needs to have selectivity so that the underlying SiO ₂ film 9 is not so much etched.

Next, the SiO ₂ film 9 is wet-etched through the opening 10a of the SiN film 10. As this etching solution, for example, a mixed solution of hydrofluoric acid: hydrogen peroxide solution: ammonium fluoride = 12: 1: 100 is used. The etching rate of SiO ₂ by this etching solution is about 20Å / sec at a temperature of 20 ° C., and GaA forming the semiconductor layer S is
The etching rate of s is about 7Å / sec. Figure 3 (C)
Shows a state in which the SiO ₂ film 9 is etched to form the opening 9a and the semiconductor layer S is just exposed. Next, wet etching is further advanced from this state to etch the semiconductor layer S as well, thereby forming a primary recess 81 as shown in FIG. This first recess 8
The bottom surface 81A of No. 1 has the same width dimension as the opening 10a of the SiN film 10. This is SiO 2 as shown in FIG.
_{When the second} film 9 is etched to expose the semiconductor layer S, the opening width t of the SiO ₂ film 9 is equal to the opening 10 of the SiN film 10.
Since the width is the same as the width a, and the semiconductor layer S is etched from the exposed region even in the etching of the primary recess 8, this width t is transferred and becomes the width of the bottom surface 81A.
At this time, since the opening 9a of the SiO ₂ film 9 recedes as the etching progresses, the first taper surface 8 having a small inclination is formed.
1B is formed on both sides of the bottom surface 81A.

Next, the opening 10a of the SiN film 10 and SiO
₂ wet etching is performed with an etchant for etching only the semiconductor layer S through the opening 9a of the film 9,
A secondary recess 82 is formed as shown in FIG. Examples of this etching solution include phosphoric acid: hydrogen peroxide solution:
A mixture of water = 3: 1: 100 is used. The depth of the secondary recess 82 is controlled so that the threshold voltage of the field effect transistor has a desired value. The bottom surface 82A of the secondary recess 82 has the same dimension t as the width of the bottom surface 81A of the primary recess 81 is transferred. Further, the first tapered surface 82B of the second recess 82 is etched in a state where the first tapered surface 81B of the primary recess 81 is transferred. Further, the second tapered surface 82C is formed by being dug down by wet etching that etches only the semiconductor layer S, so that the inclination thereof is steep.

Next, as shown in FIG. 4B, a gate metal 1C (eg, Al, Ti / Au, etc.) is deposited. The width of the pillar portion 1A grounded in the second recess of the gate electrode is
The width of the opening is the same as that of the SiN film 10, and the lower end side edge of the pillar 1A coincides with the lower edge of the first tapered surface 82B.

Next, as shown in FIG. 4C, a resist 12 is patterned on the gate metal 1C and left above the recess, and the gate metal 1C is dry-etched (or ion milled) using the resist 12 as a mask.
By removing the resist 12, a gate structure as shown in FIG. 2 is obtained.

(Embodiment 2) This embodiment is an example to which the present invention is applied when the gate electrode is formed by the lift-off method.

First, in this embodiment, S is formed on the semiconductor layer S.
The iO ₂ film 9 formed by the CVD method, on the SiO ₂ film 9 (E
B: Electron beam positive resist (for example, S manufactured by Shipley)
AL110-PLI) 13 is formed to a thickness of 0.3 μm, and a negative resist (for example, R manufactured by Hitachi Chemical Co., Ltd.) is formed thereon.
D2000N) 14 to a thickness of ˜1 μm.

Then, in the negative type resist 14, a pattern opening (about 1 μm) corresponding to the upper wide portion 1B of the gate electrode 1 is formed.
m) Form 14A. At this time, the negative resist 14
Therefore, the positive resist 13 in the opening 14A is not exposed and remains as it is. It should be noted that the types of both resists may be such that they do not intersect during coating, do not affect each other during each development, and have resistance during etching of the SiO ₂ film 9 and the semiconductor layer S. Further, it is desirable that the opening cross-sectional shape of the negative resist has an inverse taper shape as shown in FIG. Next, the same figure (A)
As shown in FIG. 1, the opening 1 is formed on the positive resist 13 in the opening 14A of the negative resist 14 by using electron beam direct drawing or the like.
An opening (about 0.2 μm) 13A narrower than 4A is formed.

After that, S is passed through the openings 14A and 13A.
The iO ₂ film 9 is wet-etched. As the etching solution, a mixed solution of hydrofluoric acid: hydrogen peroxide solution: ammonium fluoride = 12: 1: 100 is used as in the first embodiment.
After forming a primary recess (not shown) similar to that of the first embodiment in the semiconductor layer S by this etching, the etching solution is changed to a mixed solution of phosphoric acid: hydrogen peroxide solution: water = 3: 1: 100. Then, as shown in FIG. 5B, the second recess 82
To form.

The width of the bottom surface 82A of the secondary recess 82 is the same as the width of the opening 13A of the positive resist 13.

Next, as shown in FIG. 6A, the gate electrode 1 can be formed by depositing the gate metal 1C.

Then, the negative resist 14 and the positive resist 13 are removed to perform lift-off.

Also in this embodiment, the pillar portion 1A of the gate electrode 1 overlaps with the bottom surface 82A of the secondary recess 82 and is aligned with the lower end edge of the first tapered surface 82B, so that the pillar portion similar to that of the first embodiment is formed. A standing structure can be obtained.

(Embodiment 3) In this embodiment, as shown in FIG. 7, the lower end of the pillar 1A of the gate electrode 1 is located closer to the source side. Therefore, the source resistance of the field effect transistor can be reduced. The method of forming the gate electrode is as shown in FIG.
The gate metal may be obliquely deposited in the state shown in FIG.

Although the respective embodiments of the present invention have been described above, the present invention is not limited to these embodiments and various modifications can be made within the scope of the gist of the configuration.

For example, in the above embodiment, the etching solution for the SiO ₂ film is hydrofluoric acid: hydrogen peroxide: ammonium fluoride = (2: 1: 100).
The present invention is not limited to this, and other ratios or other etching solutions may be used. Incidentally, in the above mixing ratio, the etching rate of SiO ₂ becomes faster when the ratio of hydrofluoric acid is increased, and the etching rate of GaAs becomes faster when the ratio of hydrogen peroxide solution is increased.

In the above embodiment, the insulating film is made of Si.
Although O ₂ , SiN, resist and the like are used, other material films may be used.

[0036]

As is clear from the above description, according to claims 1 to 6 and claim 8 of the present application, the gate parasitic capacitance is reduced and the gate parasitic resistance is reduced, so that the high frequency of the field effect transistor is improved. It has the effect of improving the characteristics. Further, since the positional relationship between the bottom surface of the recess and the side wall of the pillar of the gate electrode is uniquely determined by self-alignment, the reproducibility of the characteristics of the field effect transistor is stabilized.

Further, according to claim 7 of the present application, in addition to the above effects, the source parasitic resistance of the field effect transistor can be particularly reduced, so that there is an effect of further improving the high frequency characteristics.

[Brief description of drawings]

FIG. 1 is a plan view showing an entire chip pattern according to a first embodiment of the present invention.

2 is a sectional view taken along line XX of FIG.

3A to 3D are cross-sectional views of a main part showing the manufacturing process of the first embodiment.

4A to 4C are cross-sectional views of a main part showing the manufacturing process of the first embodiment.

5A and 5B are cross-sectional views of a main part showing the manufacturing process of the second embodiment.

6A and 6B are cross-sectional views of a main part showing the manufacturing process of the second embodiment.

FIG. 7 is a cross-sectional view of a main part of the third embodiment.

FIG. 8A to FIG. 8C are cross-sectional views of a main part of a conventional example.

9A and 9B are cross-sectional views of a main part of a conventional example.

FIG. 10 is a sectional view of a main part of a conventional example.

[Explanation of symbols]

S ... semiconductor layer 1 ... gate electrode 1A ... strut 1B ... wide portion 1C ... gate metal 2 ... Source 9 ... SiO ₂ film 10 ... SiN film 10a ... opening 11 ... resist 11a ... opening 13 ... positive resist 13A ... opening 14 ... Negative resist 14A ... Opening 81 ... Primary recess 81A ... Bottom 81B ... First taper surface 82 ... Secondary recess 82A ... Bottom 82B ... First taper surface 82C ... Second taper surface

Claims (8)

[Claims] 1. A field effect transistor in which a recessed groove-shaped recess is formed on a surface of a semiconductor layer, and a gate electrode is erected on the recess bottom portion, wherein a sidewall of the recess extends from the groove bottom portion side to the groove top side. A field effect transistor, characterized in that it is formed by a plurality of tapered surfaces so that the inclination becomes large in multiple stages. 2. The field effect transistor according to claim 1, wherein a sidewall of the recess is formed by a two-step tapered surface. 3. The field effect transistor according to claim 1, wherein a lower end edge of the side wall of the gate electrode is located substantially at a lower end edge of the side wall of the recess. 4. The field effect transistor according to claim 1, wherein a lower end portion of the gate electrode is located closer to the source. 5. A step of sequentially forming a first insulating film and a second insulating film on a semiconductor layer, and a step of exposing and developing after applying a resist on the second insulating film. A step of forming an opening having a width, a step of performing anisotropic etching using the resist as a mask to open the second insulating film, and a step of opening the first insulating film and the semiconductor layer through the opening of the second insulating film. Wet etching to form a primary recess in the semiconductor layer, and using an etchant for selectively etching only the semiconductor layer, the bottom surface structure of the primary recess is maintained while maintaining the bottom surface structure of the semiconductor layer. A step of forming a secondary recess by etching in the depth direction, and a step of depositing a gate metal on the second insulating film and then patterning the gate metal to form a T-shaped gate. , Characterized in that Manufacturing method of effect transistor. 6. A step of forming an insulating film on a semiconductor layer, a step of sequentially laminating a positive resist layer and a negative resist layer on the insulating film, and a step of forming a T-shaped gate on the negative resist layer. After forming the first opening having a width corresponding to the width of the wide head, the positive resist layer in the first opening is provided with a first opening having a width corresponding to the width of the pillar of the T-shaped gate. 2 forming an opening, a step of performing wet etching through the first opening and the second opening to etch the insulating film and the semiconductor layer to form a primary recess, and only the semiconductor layer. A step of forming a secondary recess by performing etching to a depth method of the semiconductor layer while maintaining the bottom structure of the primary recess with an etchant for selectively etching, and depositing a gate metal. After that, positive resist layer and negative Method of manufacturing a field effect transistor, characterized in that it comprises a step of lift-off by removing the resist layer. 7. The method of manufacturing a field effect transistor according to claim 5, wherein the gate metal is obliquely vapor-deposited so as to be deposited closer to the source in the secondary recess. 8. The semiconductor layer wherein arsenic is a group V element II
The insulating film on the semiconductor layer is Si.
A primary recess is formed by wet etching the insulating film and the semiconductor layer together with O ₂ using a mixed solution of hydrofluoric acid, hydrogen peroxide solution and ammonium fluoride as an etching solution. 5. The method for manufacturing the field effect transistor according to claim 5 or claim 6.