JPH063385A - Detection of pulse frequency - Google Patents

Abstract

PURPOSE:To reduce the load of a CPU, maintain it constantly regardless of the pulse frequency, utilize the CPU effectively, and at the same time detect a wide range of pulse frequency with an extremely constant accuracy. CONSTITUTION:The title method is provided with a frequency-dividing circuit 2 for specifying a frequency-dividing ratio arbitrarily, a period calculation part 40 for measuring the period of output pulse of the frequency-dividing circuit 2, a frequency-dividing ratio setting part 7 for changing the frequency-dividing ratio of the frequency-dividing circuit 2 freely, and a frequency calculation part 50. The frequency-dividing ratio of the frequency-dividing circuit 2 is changed so that the period of the output pulse of the frequency-dividing circuit 2 is almost constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting the frequency of a pulse that varies over a wide range, such as a pulse generator for detecting the rotation speed of an electric motor.

2. Description of the Related Art Conventionally, there are roughly two methods for detecting the frequency of a pulse: 1) a method of measuring the number of pulses input during a fixed period, and 2) a method of measuring the pulse period. . According to the method 1), the frequency can be measured with high accuracy in the high frequency region, but the accuracy is deteriorated with respect to the low frequency. In order to accurately measure a low frequency, the measurement period must be lengthened, which has the drawback of slowing the detection speed. The method 2) can measure with high accuracy at low frequencies, but has the drawback of being less accurate at high frequencies. As described above, since it is not possible to accurately measure the pulse frequency from the high frequency to the low frequency by either one of the above methods, a method of combining the above two methods is generally performed. These methods can be relatively easily performed by using a microcomputer (hereinafter referred to as CPU). For example, there is a means for switching the method so that the number of pulses input during a certain period is measured when the frequency is high and the period of the pulse is measured when the frequency decreases. Alternatively, there is a method in which the time at which a pulse is input and the number of pulses are constantly measured and the frequency is obtained from both the number of pulses and the interval.

The above methods have drawbacks such as problems associated with switching, complicated arithmetic operations, and increased responsibility of the CPU at higher frequencies. An example of a conventional frequency detection method is shown in FIG. FIG. 3 is a block diagram thereof, 1 is a pulse generator, 3 is a pulse counter,
Reference numeral 4 denotes a clock unit, 5 denotes a frequency calculation unit, and in the pulse counter 3, the clock unit 4, and the frequency calculation unit 5, the CPU often performs these functions. Reference numeral 6 represents a CPU. The pulse counter 3 counts up or down by the pulse from the pulse generation source 1. Further, the clock unit 4 outputs the time when the latest pulse is input. FIG. 4 shows FIG.
FIG. 3 is a waveform diagram showing the principle of the frequency detection method of 1), and 1) is the waveform of the pulse generation source. The pulse counter 3 counts the rising (or falling, or both) edges of this waveform. At the same time, the clock unit 4 outputs the time at that time. In the figure, N, N + 1, ... Show the output values of the pulse counter 3, and Tn, Tn + 1 ,. 2) indicates the time point when the frequency calculation unit 5 performs a calculation operation. A case where the calculation is performed at the time points T0 and T1 in the figure will be described. At time T0, the frequency calculator 5 outputs the output value N of the pulse counter 3 at that time.
And the output value Tn of the clock unit 4 are read, and frequency calculation calculation is performed. Also, N and Tn are stored for the next calculation. At time T1 when the next arithmetic operation is performed, the frequency calculation unit 5 again reads the output value N + m of the pulse counter 3 and the output value Tn + m of the clock unit 4 at that time and performs the frequency calculation operation. At this time, the frequency calculation unit 5 determines that the output value N of the pulse counter 3 and the clock unit at the previous time T0.
And Tn and the output values N + m and Tn + m at this time T1, and the period Tp of one pulse can be calculated by the following equation. Tp = (Tn + m-Tn) / (N + m-N) Therefore, the frequency is obtained from 1 / Tp as the reciprocal of the period.

[0003]

However, the conventional method has the following drawbacks. For the frequency calculation calculation, it is sufficient to know the time and the output of the counter for the pulse immediately before the time T0 of this time and the time T1 this time, but in order to perform the calculation promptly at the scheduled time, the clock unit Therefore, it is necessary to store the time once for all the pulses that come in the period between T0 and T1. This means that as the frequency of the pulse increases, so does the CPU's duty to do. Therefore, there is a drawback that the upper limit of the measurable frequency becomes low. In order to measure a high frequency, there is a method of providing a frequency divider on the output side of the pulse generation source 1. In that case, when the frequency of the pulse becomes low, the pulse entering the counter 3 and the clock unit 4 Therefore, the detection speed for low frequencies becomes slow because the cycle becomes longer. The present invention was devised in view of the above-mentioned points, and an object of the present invention is to provide a pulse frequency detection method that eliminates such drawbacks.

[0004]

That is, the means for achieving the object is to provide a frequency dividing circuit whose frequency dividing ratio can be freely changed by the CPU, and to set the cycle of the output pulse of the frequency dividing circuit. It has a period calculator for measurement, a divider ratio setting unit that can freely change the divider ratio of the divider circuit, and a frequency calculator so that the period of the output pulse of the divider circuit becomes almost constant. In this method, the frequency division ratio of the frequency division circuit is set, and the frequency calculation unit calculates the frequency from the frequency division ratio set by the frequency division ratio setting unit and the output of the period calculation unit.

[0005]

With the above-described structure, the CPU is supplied with pulses at substantially constant intervals irrespective of the actual pulse frequency. Therefore, the CPU's duty becomes almost constant regardless of the pulse frequency. . Moreover, the duty of the CPU does not increase even when the pulse frequency is high, and the pulse of the same frequency is input to the CPU even when the pulse frequency is low. Same speed. Further, the frequency can be obtained with the same accuracy in a wide range from a high pulse frequency to a low pulse frequency. An embodiment of the present invention will be described below in detail with reference to the drawings.

[0006]

FIG. 1 is a block diagram showing an embodiment of the present invention,
FIG. 2 is a waveform diagram thereof, in which 1 is a pulse generation source,
Reference numeral 2 is a frequency dividing circuit, 40 is a period calculating unit, 50 is a frequency calculating unit, 7 is a frequency dividing ratio setting unit, and 60 is a CPU. In FIG. 1, the CPU includes a cycle calculation unit 40, a frequency calculation unit 50,
The case where the function of the division ratio setting unit 60 is fulfilled is shown. The frequency dividing circuit 2 can freely change the frequency dividing ratio. The cycle calculator 40 calculates the interval between the latest two pulses output from the frequency dividing circuit 2. Frequency division ratio setting section 7
Changes the frequency division ratio of the frequency dividing circuit 2 to be smaller when the interval of the output pulse of the frequency dividing circuit 2 from the output of the cycle calculating unit 40 is larger than the predetermined value. Is changed so that the frequency division ratio of the frequency dividing circuit 2 is increased. In FIG. 2, 1) shows the output waveform of the pulse generator 1. Further, 0, 1, 2, ... Shown on the waveform indicate the count value of the frequency dividing circuit 2. 2) shows an output waveform of the frequency dividing circuit 2, and 3) shows a time point when the frequency calculating section 50 performs a calculation. The operation of the frequency detection method according to the present invention will be described with reference to FIG. It should be noted that FIG. 2 shows the frequency division ratio of the frequency dividing circuit 2.
It shows the operation when it is set to N ″. Time Tm
In -1, the frequency divider circuit 2 resets the count value because the count value has reached the value of the frequency division ratio, and generates a pulse output. At the same time that the pulse output is generated, the period calculation unit 40 calculates the interval Tpm-1 from the latest pulse (not shown) before that.

The period calculation unit 40 stores the time Tm-1 at which the pulse output is generated. Similarly, when the frequency dividing circuit 2 generates a pulse at time Tm, the latest pulse interval is obtained by (Tm-Tm-1). Calculate Tpm. The frequency division ratio setting unit 7 changes the frequency division ratio of the frequency dividing circuit 2 to be small when the pulse interval Tpm is longer than a predetermined value. Also,
When the pulse interval Tpm is shorter than the expected value, the frequency division ratio of the frequency dividing circuit 2 is changed to be large. In other words, the frequency division ratio setting unit 40 sets the frequency division ratio of the frequency division circuit 2 so that the output of the frequency division circuit 2 becomes approximately the planned value. At time T1, the frequency calculation unit operates, the cycle of the output pulse of the pulse generation source is calculated by Tp = Tpm / N, and the frequency is calculated by 1 / Tp. In the above-described operation, the CPU measures the pulse interval generated in a predetermined cycle, and sets the frequency division ratio of the frequency dividing circuit according to the result. Therefore, regardless of the frequency of the pulse generation source, it suffices to fulfill almost a fixed duty. Moreover, according to this method, the frequency dividing circuit absorbs all the influences of high and low frequencies, so that a very wide range of pulse frequencies can be measured with the same accuracy.

[0007]

As described above, according to the present invention, C
Since the responsibility of the PU is light and can be kept constant regardless of the pulse frequency, the CPU can be effectively used and detection of a wide range of pulse frequencies with extremely constant measurement accuracy can be performed. In this embodiment, the case where the frequency dividing circuit 2 is provided outside the CPU has been described. However, when using a CPU having a counter with a preset or a counter with a prescaler, the frequency dividing circuit 2 is also included in the CPU. Can be incorporated into motion. That is, the functions of the frequency dividing circuit 2, the period calculating unit 40, the frequency dividing ratio setting unit 7, and the frequency calculating unit 50 are the gist of the present invention, and their forms are not important.

[0008]

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram thereof.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a waveform diagram thereof.

[0009]

[Explanation of symbols]

 1 pulse generation source 2 frequency divider circuit 7 frequency division ratio setter 40 cycle calculator 50 frequency calculator 60 CPU

Claims (1)

[Claims] 1. In a pulse frequency detection circuit, a frequency dividing circuit for arbitrarily designating a frequency dividing ratio, a period calculating section for measuring a period of an output pulse of the frequency dividing circuit, and a frequency dividing ratio for the frequency dividing circuit are provided. A frequency division ratio setting unit that freely changes and a frequency calculation unit are provided, and the frequency division ratio of the frequency division circuit is changed so that the cycle of the output pulse of the frequency division circuit is substantially constant. And pulse frequency detection method.