JPH06342056A - Serial signal time delay device - Google Patents

Abstract

(57) [Summary] [Purpose] When the time delay amount of the serial signal is changed,
Prevents discontinuity in the output signal. A clock frequency setting means capable of setting an arbitrary clock frequency, a clock generating means for generating a clock having a clock frequency set by the clock frequency setting means, and a periodical operation based on the clock generated by the clock generating means. A serial signal generating means for generating a serial signal and resetting after a predetermined time to start generating the serial signal from the beginning, and an arbitrary delay time when the serial signal generating means starts generating the serial signal from the beginning. A delay time setting means for setting is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial signal time delay device, and more particularly to a GPS (Global).
Positioning System) A time delay of a serial signal suitable for use in a test device of a GPS receiver capable of simulating generation of a GPS signal in order to test a GPS receiver capable of receiving a GPS signal transmitted from a satellite. Regarding the device.

[0002]

BACKGROUND OF THE INVENTION Conventionally, C / A (Clear and Acquisiti) transmitted from a plurality of GPS satellites has been used.
On) A GPS receiver is known that receives a GPS signal including a code and a navigation message to measure the relative distance and relative speed between a moving body that is navigating and each GPS satellite.

In such a GPS receiver, since it is necessary to accurately evaluate the function and performance in the manufacturing process thereof, conventionally, the navigation signal is actually received by receiving a GPS signal transmitted from a GPS satellite. The position and speed of the moving body were measured to evaluate the function and performance of the GPS receiver.

However, in the evaluation method using the GPS signal transmitted from the GPS satellite as described above, it is impossible to objectively evaluate whether or not the evaluation result measures the accurate position and speed of the moving body. There is a problem that the reliability is poor and a GPS signal received at the time of measurement cannot be reproduced, so that it is not possible to perform repeated measurement under the same conditions.

Therefore, as a means for solving the above-mentioned problems, for example, Japanese Patent Laid-Open No. 3-251778.
As disclosed in Japanese Patent Laid-Open Publication No. G, a signal simulating a GPS signal (hereinafter, simply referred to as “simulated GPS signal”) can be transmitted to a GPS receiver.
A test device for a PS receiver (hereinafter simply referred to as "test device") has been proposed.

[0006]

The above-mentioned GPS is used.
When the receiver receives GPS signals, the GPS satellites and G
Corresponding to the distance to the PS receiver, GPS satellites are GP
After outputting the S signal, the output GPS signal is output to G
There will be a time delay before the PS receiver receives it. The GPS receiver uses the GP included in the GPS signal.
The above-mentioned time delay is measured from the difference between the time information indicating the output timing from the S satellite and the reception time of the GPS signal, and the distance between the GPS satellite and the GPS receiver is calculated.

By the way, such a time delay changes every moment as the distance between the GPS satellite and the GPS receiver changes due to the relative movement between the two.

Therefore, even in the above-mentioned test apparatus, G
By generating such an ever-changing time delay when transmitting the simulated GPS signal to the PS receiver,
With the relative movement of GPS satellites and GPS receivers,
It was necessary to simulate the change in the distance between the GPS satellite and the GPS receiver.

Conventionally, as a method for generating such a time delay, for example, a time delay amount is preset in a presettable counter, and the delay amount of an input signal with respect to an output signal is adjusted by the operation of the presettable counter. A control method is known and is put to practical use in a radar receiver test device and the like.

However, in the above-mentioned conventional method, when an input / output signal handles a pulse-like signal, no problem occurs, but a C / A code and a navigation message in the GPS signal are generated. When handling continuous serial signals, when resetting the presettable counter setting value to change the delay amount,
There is a problem that a discontinuity occurs in the output signal.

The present invention has been made in view of such problems of the prior art, and an object of the present invention is to change the time delay amount of a serial signal when
An object of the present invention is to provide a time delay device for a serial signal that prevents the occurrence of discontinuity points in the output signal.

[0012]

In order to achieve the above object, a time delay device for a serial signal according to the present invention is set by a clock frequency setting means capable of setting an arbitrary clock frequency and the clock frequency setting means. A clock generating means for generating a clock of a clock frequency, and a periodic serial signal based on the clock generated by the clock generating means,
Serial signal generating means reset after a predetermined time to start generation of the serial signal, and delay time setting for setting an arbitrary delay time when the serial signal generating means starts generation of the serial signal from the head And means.

[0013]

When the clock frequency setting value is changed by the clock frequency setting means, the clock generating means changes the generation of the clock so that the clock frequency has the changed setting value. Then, the serial signal generating means generates a serial signal based on the changed clock.

Therefore, if the clock frequency is increased, the generation rate of the serial signal generated by the serial signal generating means is increased. For example, when transmitting the same amount of serial signal to the receiving side as before, the serial signal is generated more than before. The transmission can be completed in a short time. As a result, on the side receiving the serial signal, the same effect as when the time delay from the transmission to the reception of the serial signal is shortened is produced.

Further, if the clock frequency is lowered, the generation speed of the serial signal generated by the serial signal generation means becomes slower. For example, when transmitting the same amount of serial signal to the receiving side as before, transmission is performed. It will take longer than before to complete. As a result, on the side receiving the serial signal, the same effect as when the time delay from the transmission to the reception of the serial signal is lengthened is produced.

As described above, by changing the clock frequency of the clock that is the reference for generating the serial signal, the change in the time delay from transmission to reception based on the change in the distance between the transmitting side and the receiving side is simulated. can do.

In order to simulate the change in the time delay from transmission to reception based on the change in the distance between the transmitting side and the receiving side, the clock frequency of the clock that is the reference for the serial signal generation by the serial signal generating means is used. Since it is achieved by changing, it is possible to continuously change the time delay, and it is possible to prevent a discontinuity point from occurring in the serial signal.

Further, the serial signal generating means is reset after a predetermined time, and the generation of the serial signal is started from the beginning. Moreover, the delay time when the serial signal generation means starts the generation of the serial signal from the beginning can be set by the delay time setting means. Therefore, when a cumulative error occurs between the time delay due to the change in the distance between the transmitter and the receiver simulated based on the change in the clock frequency and the time delay due to the change in the actual distance,
When the serial signal generating means is reset, the delay time setting means sets a delay time indicating a time delay due to a change in the actual distance, so that the serial signal generating means can be eliminated at every predetermined time.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a time delay device for serial signals according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a serial signal time delay device according to an embodiment of the present invention.

This serial signal time delay device is constructed so that its entire operation is controlled by a control unit 10, which is a central processing unit (CPU).
And a read-only memory (ROM) storing a program of the CPU, and a working memory in which various registers necessary for the CPU to execute the program are set.
Random access memory (RAM) as an area
And is configured.

The control unit 10 starts counting when receiving a start trigger output from the control unit 10, and
A free-run counter 12 that is reset in a 2.5-minute cycle and repeats counting, and a delay time (initial delay amount) indicating the time delay in the initial state while the counter output from the free-run counter 12 is input. ) Is input to the digital comparator 14 that outputs a delay trigger when the counter output and the initial delay amount match, and the set value of the clock frequency is input from the control unit 10 based on the set value. DDS as a clock generation circuit for generating a clock of a clock frequency
(Direct Digital Synthesiz
er) unit 16 is connected.

The delay trigger output from the digital comparator 14 and the clock output from the DDS section 16 are input to the serial signal generating circuit 18, and the serial signal generating circuit 18 to which the delay trigger is input is Based on the clock output from the DDS unit 16, a C / A code and a navigation message that are periodic serial signals (hereinafter simply referred to as serial signals).
Is generated and transmitted to a GPS receiver (not shown).

The serial signal generating circuit 18 is configured to repeatedly generate a signal at a cycle of 12.5 minutes at the reference clock frequency f. The free-run counter 12 and the serial signal generation circuit 1 described above
The period "12.5 minutes" in 8 is the period of the navigation message. The cycle is not limited to "12.5 minutes", and "6" corresponding to one word of the navigation message
The time interval can be appropriately set to "00 msec" or the like.

In the above configuration, assuming that the GPS satellite and the GPS receiver in the stationary state are first assumed, the initial delay amount indicating the time delay calculated by corresponding to the distance between them is set to the control unit 10. Is output to the digital comparator 14 and set in the digital comparator 14. Further, in the control unit 10, the GPS assumed above is used.
Corresponding to the change in the distance from the GPS receiver when the satellite moves, the variation Δf from the reference clock frequency f is calculated, and the clock frequency (f) is added to the reference clock frequency f and the variation Δf. f + Δf) is output to the DDS unit 16 and set.

When the distance between the GPS satellite and the GPS receiver changes so as to become shorter, the frequency fluctuates so that the frequency becomes higher than the reference clock frequency f, so the variation Δf is It will be a positive value.

On the other hand, when the distance between the GPS satellite and the GPS receiver changes so as to become longer, it fluctuates to become a frequency lower than the reference clock frequency f, so the fluctuation amount Δf is It will be a negative value.

After the above setting is completed, a start trigger for starting the counting of the free-run counter 12 is output from the control unit 10 to the free-run counter 12, and the counting of the free-run counter 12 is started.

The count output from the free-run counter 12 is input to the digital comparator 14, and the digital comparator 14 outputs the count output and the control unit 10.
When the initial delay amount set by is matched, the delay trigger is output to the serial signal generating circuit 18 (FIG. 2).

Then, the serial signal generation circuit 18 is reset when a delay trigger is input and starts generation of a periodic serial signal.

The cycle of this serial signal is determined by the DDS unit 16
Is determined by the clock frequency (f + Δf) of the clock output from the serial signal generating circuit 18 to the serial signal generating circuit 18. If the clock frequency (f + Δf) is higher than the reference clock frequency f, the cycle of the serial signal is 12 .5
It is shorter than a minute and can simulate a state where the time delay is shortened.

For example, as shown in FIGS. 3A to 3D, when the clock frequency is the reference clock frequency f shown in FIG. 3A, the serial signal shown in FIG. 3B is generated. 3C, if the clock frequency is changed to a clock frequency (f + Δf) higher by the variation Δf as shown in FIG. 3C, the generation rate of the serial signal is increased as shown in FIG. 3D. Can be faster.

That is, if the clock frequency is increased, the generation speed of the serial signal generated by the serial signal generation circuit 18 is increased, and the same amount of serial signal as before is GP.
When transmitting to the S receiver, the transmission can be completed in a shorter time than before. Therefore, when the GPS receiver receives the serial signal, the delay time from the transmission of the serial signal to the reception is delayed. Equivalent to shortening.

On the other hand, if the clock frequency (f + Δf) becomes lower than the reference clock frequency f, the cycle of the serial signal becomes longer than 12.5 minutes, and the state in which the time delay is extended can be simulated.

That is, if the clock frequency is lowered, the generation speed of the serial signal generated by the serial signal generation circuit 18 becomes slower, and the same amount of serial signal as before is GP.
When transmitting to the S receiver, a longer time is required until the transmission is completed. Therefore, when the GPS receiver receives the serial signal, the delay time from the transmission of the serial signal to the reception is longer. Equivalent to becoming longer.

As described above, by changing the clock frequency of the clock that serves as the reference for the serial signal generation by the serial signal generation circuit 18, from the transmission to the reception based on the change in the distance between the GPS satellite and the GPS receiver. Since the simulation of the change of the time delay is achieved, the time delay can be continuously changed, and the discontinuity of the serial signal can be prevented.

Further, the free-run counter 12 has 1
It is reset every 2.5 minutes, and when the free-run counter 12 is reset, the digital comparator 14 outputs the delay trigger again (FIG. 2) and resets the serial signal generation circuit 18. Then, the generation of the periodic serial signal is restarted from the beginning.

At this time, the control unit 10 indicates to the digital comparator 14 the time delay obtained by calculation corresponding to the distance between the GPS satellite and the GPS receiver when the free-run counter 12 is reset. The initial delay amount is set, and the time delay simulated by the fluctuation of the clock frequency and the GPS satellite and G
If an error occurs between the time delay calculated corresponding to the distance to the PS receiver and the time delay calculated, the error accumulated during the 12.5 minute period (cumulative error) is -It is canceled when the counter 12 is reset.

That is, when the free-run counter 12 is reset, the time delay calculated corresponding to the distance between the GPS satellite and the GPS receiver is newly set, so that the above cumulative error is eliminated. You will be able to do it.

Thereafter, the time delay device for the serial signal is 1
Each operation described above is repeated every 2.5 minutes.

[0041]

Since the present invention is constructed as described above, it has the following effects.

A clock frequency setting means capable of setting an arbitrary clock frequency, a clock generating means for generating a clock having a clock frequency set by the clock frequency setting means, and a periodical operation based on the clock generated by the clock generating means A serial signal generating means for generating a serial signal and resetting after a predetermined time to start generating the serial signal from the beginning, and an arbitrary delay time when the serial signal generating means starts generating the serial signal from the beginning. By including the delay time setting means for setting, by changing the clock frequency of the clock that is the reference of the generation of the serial signal,
It becomes possible to simulate the change in the time delay from transmission to reception based on the change in the distance between the transmitting side and the receiving side, and this time delay can be changed continuously and the serial delay can be changed. It is possible to prevent discontinuity in the signal.

Further, the serial signal generating means is reset after a predetermined time so as to start the generation of the serial signal from the beginning, and a delay when the serial signal generating means starts the generation of the serial signal from the beginning. Since the time is set by the delay time setting means, the accumulated error between the time delay due to the change in the distance between the transmitter and the receiver simulated based on the change in the clock frequency and the time delay due to the change in the actual distance. In the case of occurrence of the above, when the serial signal generating means is reset, the delay time setting means sets the time delay due to the actual change of the distance, which can be eliminated at every predetermined time.

Therefore, according to the time delay device of the serial signal of the present invention, it is possible to prevent the occurrence of discontinuity in the output signal when the time delay of the serial signal is changed. It can be used for testing equipment of machines.

[Brief description of drawings]

FIG. 1 is a block diagram of a time delay device for a serial signal according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the relationship between a start trigger and a delay trigger in the serial signal generator.

3A and 3B are timing charts showing the operation of the serial signal generator, where FIG. 3A shows a reference clock frequency f, FIG. 3B shows a serial signal at the reference clock frequency f, and FIG. The frequency (f + Δf) is shown, and (d) shows the serial signal at the clock frequency (f + Δf).

[Explanation of symbols]

 10 control section 12 free-run counter 14 digital comparator 16 DDS section 18 serial signal generation circuit

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[Procedure amendment]

[Submission date] October 12, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Added

[Correction content]

[Figure 3]

Claims (1)

[Claims] 1. A clock frequency setting unit capable of setting an arbitrary clock frequency, a clock generating unit generating a clock having a clock frequency set by the clock frequency setting unit, and a clock generated by the clock generating unit. A serial signal generating means for generating a cyclic serial signal based on the serial signal and resetting after a predetermined time to start generating the serial signal from the beginning; and the serial signal generating means starts generating the serial signal from the beginning. And a delay time setting means for setting an arbitrary delay time when the serial signal time delay device.