JPH06342881A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] When two MOS transistors driven by different power supply voltages are provided on the same substrate, the manufacturing cost is reduced and the yield is improved while achieving high speed and high reliability. (EN) Provided is a semiconductor device and a manufacturing method thereof, which secures the performance and enables miniaturization of a MOS transistor. A gate insulating film 103 having a constant film thickness formed on the surface of an element forming region of a semiconductor substrate 101, and a second insulating film
Of the second MOS transistor which is formed in the element formation region of No. 1 and has a gate electrode 104a having a relatively low impurity concentration, and which is used by applying a relatively high power supply voltage, and the first MOS transistor formation region. A first MOS transistor having a gate electrode 104b having a relatively high impurity concentration formed by the same wiring layer as the second gate electrode and used with a relatively low power supply voltage applied. And is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a plurality of types of MOS transistors formed on the same semiconductor substrate and having different operating power supply voltages, and a method of forming the same.

[0002]

2. Description of the Related Art In recent years, demands for higher speed and higher density of semiconductor devices have been increasing more and more, and in order to satisfy these demands, long and complicated manufacturing processes and accompanying reduction in yield are inevitable. The reality is that it leads to higher costs and lower reliability.

In order to meet the demands for high speed and high density, it is natural that miniaturization of elements according to the scaling rule has been effective conventionally. According to the well-known scaling law, it is necessary to reduce the power supply voltage in order to keep the electric field constant, but in a system incorporating a semiconductor device, a unique power supply cannot be used, and normally a 5V power supply is used.

Due to such circumstances, miniaturization of the device according to the scaling rule is increasing the electric field inside the device because the device size is reduced while the power supply voltage is kept constant. Further, in order to secure the reliability of the device, it is necessary to secure a large gate oxide film thickness to some extent, and thus it is impossible to scale the gate oxide film thickness. As is well known, it is an obstacle to improving the performance of the device.

In particular, in a non-volatile memory in which a high power supply voltage is used during writing and erasing operations, miniaturization of elements becomes more difficult. Therefore, the conventional semiconductor device adopts a circuit configuration in which the number of elements to which a high voltage is directly applied is limited in the element group formed on the same semiconductor substrate and the other elements are operated at a low voltage. There is something I did.

An example of a conventional method for manufacturing a semiconductor device of this type will be described below with reference to FIGS. First, as shown in FIG. 5A, an element isolation insulating film 302 is selectively formed on the surface of a semiconductor substrate 301 of the first conductivity type, and a region excluding the element isolation insulating film 302 (element formation planned region) A silicon oxide film 303 for a gate oxide film is formed on the surface of the substrate.

A part of this element formation scheduled area is used as a second element formation scheduled area for forming an element to which a high voltage is directly applied, and the rest of the majority is applied with a low power supply voltage. It is used as a first element formation planned region for forming an element.

Next, as shown in FIG. 5B, on the second element formation planned area for forming the element to which the high voltage is directly applied and the element isolation insulating film 302 adjacent to this area. Then, a resist pattern 305 is formed.

After that, using the resist pattern 305 as a mask, the silicon oxide film 30 in the first element formation planned region for forming the element to which the low voltage is applied is formed.
3 is removed by etching. In this step, the element isolation insulating film 30 not covered with the resist pattern 305.
For No. 2, as shown in FIG. 5C, the film thickness is reduced.

Then, after removing the resist pattern 305, thermal oxidation is applied. As a result, as shown in FIG. 5C, the oxide film 303 in the second element formation planned region becomes a thicker oxide film 303a, and the resist pattern is formed.
A thin oxide film 307 is newly formed in the first element formation planned region which is removed by etching using the mask 305 as a mask. Then, after depositing polycrystalline silicon 304 on the entire surface, doping of the second conductivity type impurities is performed on the polycrystalline silicon.

Next, as shown in FIG. 5D, the polycrystalline silicon 304 is etched to form a gate electrode wiring 306, and the gate electrode wiring 306 is used as a mask to form a drain. A second conductivity type impurity region 308 for a source is formed in the surface layer portion of the semiconductor substrate 301.

The device thus formed is constructed such that some elements to which a high voltage is directly applied have a thick gate oxide film 303a, and most elements to which a low voltage is directly applied. The device is configured to have a thin oxide film 307.

As a result, most of the devices are driven by a low voltage and the applied electric field is sufficiently reduced, so that scaling with a thin gate oxide film is possible, and miniaturization and high performance of the devices are achieved. Will be possible.

A power supply voltage supplied from the outside is used as the high voltage, and a voltage generated by lowering the potential of the power supply voltage is used as the low voltage.
However, the device created by the above method is
There are the following problems.

In the step of etching away the silicon oxide film 303 in the first device formation region shown in FIG. 5B, the film thickness of the device isolation insulating film 302 recedes (that is, the end portion of the resist pattern 305). Corresponding to the element isolation insulating film 3
Since a step is formed at 02), an etching residue 309 is generated at the step portion in the gate electrode wiring forming step, as shown in FIG. 5D. This etching residue 309 is
Not only does it cause the short of the gate electrode short,
309 etching remaining after the gate electrode wiring formation
It is unavoidable that the dust generated by desorption of slag causes various defects.

Also, the element isolation insulating film 30 as described above.
The receding film thickness of 2 causes a decrease in the reverse breakdown voltage of the parasitic transistor that occurs in the element isolation region, and becomes a factor that hinders the miniaturization of the element.

Further, in the etching removal process of the silicon oxide film 303 in the first element formation planned region shown in FIG. 5B, the resist pattern 305 causes the gate oxide film 303 in the second element formation planned region. Since it exists above, it is inevitable that contaminants that may cause dielectric breakdown will intrude into the lower gate oxide film 303 from the resist pattern 305. As a result, the yield of the gate oxide film 303 is reduced due to the destruction thereof, and the reliability of the device is significantly reduced.

In addition, since the device formed as described above has more heat steps for gate oxidation than a device using one normal type of gate oxide film thickness,
In addition to increasing manufacturing costs due to an increase in manufacturing processes,
If there are many heat treatment steps, it is disadvantageous in miniaturization of the device.

[0019]

As described above, according to the conventional method of manufacturing a semiconductor device, in order to meet the demands for high speed and high density of the semiconductor device, MOS transistors driven by two different power supply voltages are provided on the same substrate. If it is provided on the upper side, there is a problem that the manufacturing cost increases and the reliability decreases.

The present invention has been made to solve the above problems, and is a MOS driven by two different power supply voltages.
When transistors are provided on the same substrate, semiconductor devices and semiconductor devices that realize high speed while ensuring manufacturing cost reduction and yield improvement, ensure high reliability, and enable high performance and miniaturization of MOS transistors It is intended to provide a manufacturing method.

[0021]

The semiconductor device of the present invention comprises:
A first conductivity type semiconductor substrate, an element isolation insulating film selectively formed on the surface of the semiconductor substrate, and a gate insulation having a constant film thickness formed on the surface of an element forming region of the semiconductor substrate. A film and a first impurity formed on the gate insulating film in the first element formation region for forming the first MOS transistor to which the first power supply voltage is applied in the element formation region. Formed on the surface of the first element formation region with a first gate electrode made of polycrystalline silicon of a second conductivity type having a concentration and a channel region below the first gate electrode sandwiched therebetween. A first source / drain region of the second conductivity type and a second MOS transistor to which a second power supply voltage higher than the first power supply voltage is applied in the element formation planned region. Gate insulating film in the second element formation region to be formed A second conductive type polycrystalline silicon having a second impurity concentration lower than the first impurity concentration and formed of the same wiring layer as the first gate electrode. Second gate electrode and a second conductive type second source formed on the surface of the second element forming region with the channel region below the second gate electrode interposed therebetween.
And a drain region.

The semiconductor device manufacturing method of the present invention is
A step of selectively forming an element isolation insulating film on the surface of a semiconductor substrate of the first conductivity type and forming a gate insulating film on the substrate surface of the element forming region; and a first power source in the element forming region. A first MOS transistor, to which a voltage is applied, is formed on the gate insulating film in the first element formation region in which the first MOS transistor is to be formed.
Forming a first gate electrode using a second conductivity type polycrystalline silicon having an impurity concentration of, and a second power supply voltage higher than the first power supply voltage in the element formation planned region. The first element is formed on the gate insulating film in the second element formation region where the second MOS transistor to be applied is to be formed.
A second impurity concentration lower than the second impurity concentration
A gate electrode forming step of forming a second gate electrode using conductive type polycrystalline silicon, and the first gate electrode and the second gate electrode are used as masks to form the first gate electrode. And a step of forming a source / drain region by doping a second conductivity type impurity on the surface of the element forming region and the surface of the second element forming region.

[0023]

In this semiconductor device, since the impurity concentration of the gate electrode (second gate electrode) of the second MOS transistor is low, when a high voltage is applied to this gate electrode, this gate electrode A depletion layer is formed on the gate insulating film side of the gate electrode, and the electric field is weakened by the effect of effectively reducing the capacitance of the gate insulating film under the gate electrode.

In other words, by controlling the impurity concentration of the gate electrode to control the effective film thickness of the gate insulating film, one type (same film thickness) of the gate insulating film can be formed. While using it, it effectively operates as a device having two types of gate insulating films.

Therefore, in a circuit configuration in which two different potentials are applied, it is possible to design a MOS transistor for each given potential without strengthening the electric field, and realize miniaturization and high performance. It becomes possible to do.

Further, in this method of manufacturing a semiconductor device, the gate insulating film forming step by thermal oxidation is required only once (the heat step is less than that of the conventional example), so that the manufacturing cost is simplified. The reduction can be realized, the diffusion rate of impurities can be easily controlled, and this is advantageous for miniaturization of MOS transistors.

Further, since there is no receding of the film thickness of the element isolation insulating film, which is a problem in the process of the conventional example, a step which causes an etching residue generated during the processing of the gate electrode is not generated and the yield is improved.

Further, since there is no step of forming a resist pattern so as to be in direct contact with the gate insulating film, contamination of the gate insulating film from the resist material does not occur, and dielectric breakdown of the gate insulating film occurs. The defects that lead to
The reliability of the device is improved.

[0029]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1A to 1D show a wafer cross-sectional structure in a manufacturing process of an N-channel semiconductor device according to the first embodiment of the present invention.

The first embodiment will be described in detail with reference to the drawings. First, as shown in FIG. 1A, a well-known LOCOS (selective oxidation) is formed on the surface of a P-type silicon substrate 101.
A 600 nm element isolation oxide film 102 is formed by the method. After that, a gate oxide film 103 is formed on the substrate 101 by thermal oxidation.

Next, as shown in FIG.
Polycrystalline silicon 104 for forming a gate electrode is deposited on the entire surface of the substrate by using PCVD (Low Pressure Vapor Deposition) method.
After that, a well-known lithography technique is used to form a resist pattern 105 on the second element formation region in which an element to which a high potential (for example, 12 V at maximum) is to be applied is to be formed. . Then, using the resist pattern 105 as a mask, a low potential (for example, a maximum of 5) is used.
V) is to be applied to the polycrystalline silicon 104 in the first element formation region to form an element.
In addition, phosphorus which is an n-type impurity has an acceleration energy of −60 ke.
Ion implantation is performed with V and a dose of 1 × 10 ¹⁶ / cm ² .

Next, as shown in FIG. 1C, after removing the resist pattern 105, phosphorus is applied to the entire surface of the polycrystalline silicon 104 at an acceleration energy of 60 keV and a dose of phosphorus.
Ions are implanted at a dose of 5 × 10 ¹³ / cm ² , and then a well-known anneal process is performed. As a result, n- with low phosphorus concentration
Type polycrystalline silicon 104a and n + type polycrystalline silicon 104b having a high phosphorus concentration are formed.

Next, as shown in FIG. 1D, the polycrystalline silicon 104a and 104b are processed by a well-known lithography technique and etching technique to process the n--type second gate electrode 104a and the n--type second gate electrode 104a. n + type first gate electrode 1
After forming 04b, the gate electrodes 104a, 104 are formed.
By doping impurities with b as a mask (for example, phosphorus is ion-implanted and annealed), an n-type diffusion layer 106 serving as a source / drain is formed on the surface of the P-type silicon substrate 101.

After that, Al is formed by a known technique.
An N-channel type semiconductor device is completed through wiring, passivation film forming steps and the like. In the semiconductor device of the first embodiment, when a potential is applied to the gate electrode having a low impurity concentration, a depletion layer is formed on the gate insulating film side of the gate electrode. Well-known fact that the electric field is weakened by the effect of effectively reducing the capacitance of the insulating film (M.
Iwase et al., "Effect of Depleted Poly-Si Gate MO
SFET Performance ", ISDM 1990, pp.271-274).

That is, since the gate electrode (second gate electrode 104a) of the second MOS transistor formed in the second element formation region has a low impurity concentration, a high voltage is applied to this gate electrode. Is applied, a depletion layer is formed on the gate insulating film side of the gate electrode. As a result, the second game
The electric field is weakened by the effect of effectively reducing the capacitance of the gate insulating film portion under the gate electrode, and the film thickness of this gate insulating film portion can be effectively increased.

In other words, by controlling the impurity concentration of the gate electrode to control the effective film thickness of the gate insulating film, one type (same film thickness) of the gate insulating film can be formed. While using it, it effectively operates as a device having two types of gate insulating films.

Therefore, in a circuit configuration in which two different potentials are applied, it is possible to design a MOS transistor for each given potential without strengthening the electric field, and realize miniaturization and high performance. It becomes possible to do.

Further, in the method of manufacturing the semiconductor device of the first embodiment, the gate insulating film forming step by thermal oxidation is required only once (the heat step is less than that in the conventional example), so that the steps are simplified. It is possible to realize a reduction in manufacturing cost due to the miniaturization, facilitate the control of the diffusion rate of impurities, which is advantageous for miniaturization of MOS transistors.

In addition, in this embodiment, the conventional example shown in FIG.
Since the thickness of the element isolation insulating film, which is a problem in the process shown in Fig. 3, does not recede, a step which causes an etching residue generated during the processing of the gate electrode does not occur, and the gate electrode is short-circuited. Various defects are drastically reduced and the yield is improved.

Further, although the receding of the film thickness of the element isolation insulating film leads to the lowering of the inversion withstand voltage of the parasitic transistor between the fields, the receding of the film thickness of the element separating insulating film does not occur in this embodiment, It is possible to prevent the inversion breakdown voltage of the parasitic transistor from decreasing.

In addition, in the present embodiment, the conventional example shown in FIG.
Since there is no step of directly contacting the gate insulating film with the resist material for the ion implantation mask like the step shown in FIG.
Contaminants do not enter the gate insulating film from the resist material. As a result, defects such as dielectric breakdown of the gate insulating film are drastically reduced, and long-term reliability (lifetime of oxide film) is greatly improved.

The impurity concentrations of the second gate electrode 104a and the first gate electrode 104b are not limited to those in the above embodiment, but the depletion layer as described above is added to the second gate electrode 104a. The second gate electrode 104a may have an impurity concentration of 3 × 10 ¹⁹ cm ⁻³ or less and the first gate electrode 104b may have an impurity concentration of 3 × 10 3.
The effect of the present invention can be obtained by setting it to exceed ¹⁹ cm ^-3 .

Further, in the step shown in FIG.
By using a Si compound such as SiO ₂ instead of the resist pattern 105, the phosphorus diffusion method can be used instead of the phosphorus ion implantation method. In addition, FIG.
The order of the step of FIG. 1 and the step of FIG. 1C may be exchanged.

The present invention can also be applied to a P-channel semiconductor device. In this case, in the first embodiment, the N-type semiconductor substrate is used instead of the P-type semiconductor substrate 101, and the p-type impurity is doped into the polycrystalline silicon 104 instead of the n-type impurity to form the gate electrode. Instead of n-type impurities, p-type impurities may be doped on the subsequent semiconductor substrate.

By the way, in general, when the gate electrode is formed only of polycrystalline silicon having a low impurity concentration, the wiring resistance of the gate electrode becomes large. Therefore, in order to suppress the increase of the wiring resistance, for example, as shown in FIG. It is desirable to manufacture it like the semiconductor device shown.

FIG. 2 shows a wafer cross-sectional structure in the process of the modification of the first embodiment. In this modified example, as shown in FIG. 1C, after the n − -type polycrystalline silicon 104a and the n + -type polycrystalline silicon 104b are formed, a refractory metal film (tungsten
Silicide WSi, titanium silicide TiSi, molybdenum silicide MoSi, etc.) 201, and then N
₂ Anneal at 900 ° C. for 30 minutes in an atmosphere.
As a result, the polycrystalline silicon layers 104a and 104b become polycide layers 204a and 204b. In this case, in this example, a WSi film as the refractory metal film was deposited to a thickness of, for example, 200 nm by the sputtering method.

After that, the polycide films 204a, 20
4b is processed to form the n @--type second polycide gate electrode 204a and the n @ + -type first polycide gate electrode 204b, whereby the wiring resistance is sufficiently reduced. It is possible to realize an electrode. Note that the polycide gate electrode may be formed by performing etching processing without heat treatment after depositing the refractory metal film and then performing annealing treatment.

The polycide gate electrode 204 is also used.
a and 204b are second polycide gate electrodes 204a having a low impurity concentration when the diffusion layer 106 to be the source / drain is formed as shown in FIG. 1D after the gate electrode is formed. Since it has the effect of preventing the impurity concentration of the polycrystalline silicon 104a from being increased more than necessary, it also has the effect of facilitating the control of the impurity concentration of the gate electrode.

FIGS. 3A to 3C and FIGS. 4A to 4C show the wafer cross-sectional structure in the manufacturing process of the CMOS type semiconductor device according to the second embodiment of the present invention. The second embodiment is an EPRO requiring a high breakdown voltage.
LDD that is expected to have a high junction breakdown voltage in the peripheral transistor of M (electrically rewritable read-only memory)
This is an example using a (Lightly Doped Drain) structure.

The second embodiment will be described in detail below with reference to the drawings. First, as shown in FIG. 3A, the N well diffusion layer 20 is formed on a part of the surface layer portion of the P-type silicon substrate 201.
Form 2. Next, a 600 nm element isolation oxide film 20 is formed on the surface of the silicon substrate 201 by LOCOS.
3 is formed. Next, a gate oxide film 204 is formed on the silicon substrate by thermal oxidation. Then, LPCVD
By the method, polycrystalline silicon 205 for forming a gate electrode is deposited.

Next, as shown in FIG. 3B, the gate electrode 205 is formed by processing the polycrystalline silicon 205 by using the lithography technique and the etching technique. Subsequently, at least the N
A resist pattern 2 is formed on the region including the well diffusion layer 202.
After forming 06, the resist pattern 206 is used as a mask and phosphorus is used as an acceleration energy of 60 keV and a dose of 5
Ion implantation is performed at × 10 ¹³ / cm ² .

Next, after the resist pattern 206 is peeled off, as shown in FIG. 3C, the N-well type element formation planned area on the element formation planned area requiring a high breakdown voltage and the N well. After forming a resist pattern 207 on the region including the diffusion layer 202, phosphorus is ion-implanted at an acceleration energy of 60 keV and a dose of 1 × 10 ¹⁶ / cm ² .

Next, by performing an annealing treatment in an N ₂ atmosphere, as shown in FIG. 4A, the n − -type polycrystalline silicon 205a having a relatively low phosphorus concentration and the phosphorus concentration having a relatively high phosphorus concentration are obtained. An n @ + -type polycrystalline silicon layer 205b, an n @-diffused layer 208 serving as a source / drain region, and an n @ + diffused layer 209 serving as a source / drain region are formed. After this, P
After a resist pattern 210 is formed in a region other than the region where the channel type device is to be formed, boron is accelerated with an energy of 20.
Ion implantation is performed with keV and a dose amount of 5 × 10 ¹³ / cm ² .

Next, as shown in FIG. 4B, a resist pattern 211 is formed in a region of the P-channel type element formation planned region excluding the element formation planned region where high breakdown voltage is not required, and then boron is formed. Acceleration energy-20 keV,
Ions are implanted at a dose of 1 × 10 ¹⁶ / cm ² .

Next, by performing an annealing treatment in an N ₂ atmosphere, as shown in FIG. 4C, p--type polycrystalline silicon 205c having a relatively low boron concentration and a relatively high boron concentration. p + type polycrystalline silicon 205d, source
A p @-diffusion layer 212 to be a drain and a p @ + diffusion layer 213 to be a source / drain are formed.

After that, Al is formed by a known technique.
A CMOS type EPROM memory device is completed through wiring, passivation film forming steps and the like. Also in the second embodiment, the same effect as in the first embodiment can be obtained.

Moreover, in the second embodiment, the doping process for the polycrystalline silicon (gate electrode) can also be used as the process for forming the source / drain on the surface of the silicon substrate. Therefore, the doping process for the polycrystalline silicon, which is to be set to a low impurity concentration, also serves as the source / drain forming process for LDD, so that the number of processes for the conventional CMOS process does not increase.

In the step of FIG. 3C, the resist pattern 207 does not have to cover the entire source / drain formation planned region of the N-channel element, which requires a high breakdown voltage, and the high breakdown voltage is high. It may be formed so as to cover the required gate electrode of the N-channel element. In this case,
It is possible to increase the impurity concentration of the drain and drain and reduce the diffusion resistance thereof.

Based on the same idea as above, in the step of FIG. 4B as well, the resist pattern 211 may cover the gate electrode of the P-channel element, which requires a high breakdown voltage, which is high. It is not necessary to cover the entire source / drain formation planned region of the P-channel device, which requires a breakdown voltage.

Further, the diffusion layers 208 and 212 in FIG. 4C have a low impurity concentration and thus have a large wiring resistance. To solve this, a metal such as Ti (titanium) is added to the diffusion layer 208. And 212 may be formed so as to be stuck on. Further, in order to reduce the resistance of the gate electrode wiring, a metal such as Ti may be adhered on the gate electrode.

The order of the process of FIG. 3B and the process of FIG. 3C may be exchanged, and similarly, the order of the process of FIG. 4A and the process of FIG. May be replaced.
Further, the annealing treatment performed in the step of FIG. 4A may be omitted, and the heat treatment performed in the step of FIG. 4C can be substituted.

[0062]

As described above, according to the present invention, when MOS transistors driven by two different power supply voltages are provided on the same substrate, high speed is realized while reducing the manufacturing cost and improving the yield. Secure high reliability,
It is possible to realize a semiconductor device and a method for manufacturing the same that enable high performance and miniaturization of MOS transistors.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a wafer cross section in a manufacturing process of an N-channel semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a wafer cross section in a process of the modified example of FIG.

FIG. 3 is a sectional view showing a wafer section in a part of the manufacturing process of the CMOS semiconductor device according to the second embodiment of the invention.

FIG. 4 is a cross-sectional view showing a wafer cross section in a process following the process of FIG.

FIG. 5 is a cross-sectional view showing a wafer cross section in a conventional single-channel semiconductor device manufacturing process.

[Explanation of symbols]

101, 201 ... P-type semiconductor substrate, 202 ... N well diffusion layer, 102, 203 ... Silicon oxide film (for element isolation), 103 ... Silicon oxide film (gate insulating film), 10
4, 205 ... Polycrystalline silicon (for gate electrode), 104
a, 205a ... N- type polycrystalline silicon (second gate electrode), 104b, 205b ... N + type polycrystalline silicon (for first gate electrode), 105, 206, 207, 2
10, 211 ... Resist pattern, 106, 208, 2
09, 212, 213 ... Source / drain diffusion layer (2
08 ... n- diffusion layer, 209 ... n + diffusion layer, 212 ... p-
Diffusion layer, 213 ... P + diffusion layer).

Claims (5)

[Claims] 1. A semiconductor substrate of a first conductivity type, an element isolation insulating film selectively formed on a surface of the semiconductor substrate, and a constant film thickness formed on a surface of an element formation region of the semiconductor substrate. And a gate insulating film formed on the gate insulating film in the first element forming region for forming a first MOS transistor to which a first power supply voltage is applied in the element forming region. , A first using a second conductivity type polycrystalline silicon having a first impurity concentration
Gate electrode and a second source / drain region of the second conductivity type formed on the surface of the first element formation region with the channel region below the first gate electrode interposed therebetween. And a gate insulating film in a second element formation region for forming a second MOS transistor to which a second power supply voltage higher than the first power supply voltage is applied in the element formation planned region A second conductive type polycrystalline silicon layer formed on the same gate wiring layer as the first gate electrode and having a second impurity concentration lower than the first impurity concentration. Second gate electrode and a second source / drain of the second conductivity type formed on the surface of the first element forming region with the channel region below the second gate electrode interposed therebetween. A semiconductor device comprising: a region. 2. The semiconductor device according to claim 1, wherein the second gate electrode is a polycide gate electrode in which a refractory metal silicide is formed on an upper surface of the polycrystalline silicon. Semiconductor device. 3. A step of selectively forming an element isolation insulating film on the surface of a semiconductor substrate of the first conductivity type and forming a gate insulating film on the substrate surface of the element forming region; At the gate insulating film in the first element formation region where the first MOS transistor to which the first power supply voltage is applied is formed, the second-conductivity-type polycrystal having the first impurity concentration is formed. The first game using silicon
Of the second element formation region in which a second MOS transistor is formed in which the second power supply voltage higher than the first power supply voltage is applied in the device formation planned region. -A gate electrode is formed on the gate insulating film to form a second gate electrode using second conductivity type polycrystalline silicon having a second impurity concentration lower than the first impurity concentration. Step, and using the first gate electrode and the second gate electrode as a mask, impurities of the second conductivity type are doped on the surface of the first element formation region and the surface of the second element formation region. -Pinging to form the source / drain regions. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the gate electrode forming step includes a step of forming polycrystalline silicon on the gate insulating film and the element isolation insulating film, Forming a resist pattern in a region where the impurity concentration of the crystalline silicon is to be set to the second impurity concentration; and doping the polycrystalline silicon with an impurity of the second conductivity type using the resist pattern as a mask. A step of doping the second conductivity type impurities into the polycrystalline silicon after removing the resist pattern, and patterning the polycrystalline silicon doped with the impurities to form the first impurity. A step of forming a gate electrode and a second gate electrode, and a method of manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the gate electrode forming step includes a step of forming polycrystalline silicon on the gate insulating film and the element isolation insulating film, Forming a resist pattern in a region where the impurity concentration of the crystalline silicon is to be set to the second impurity concentration; and doping the polycrystalline silicon with an impurity of the second conductivity type using the resist pattern as a mask. A step of doping the second conductivity type impurity into the polycrystalline silicon after removing the resist pattern, and a refractory metal on the entire surface of the polycrystalline silicon doped with the impurity. After depositing the film, perform annealing treatment,
A semiconductor device comprising: a step of forming a polycide film; and a step of patterning the polycide film to form a first polycide gate electrode and a second polycide gate electrode. Production method.