JPH06343143A - Driving method of solid-state image pickup element - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce power consumption in a method for driving a FIT CCD solid-state imaging device. A FIT-type CCD solid-state image sensor having an image pickup section for converting incident light into signal charge and transferring the signal charge, and an accumulation section for temporarily storing and transferring the signal charge from the image pickup section. In the driving method, during the sweep-out transfer period T ₃ of the excess charges generated in the image pickup unit, the transfer clock pulse applied to the vertical transfer register of the storage unit is stopped and the potential in the vertical transfer register is set to the low level of the vertical transfer register of the image pickup unit. The excess charge is swept out and transferred by fixing it to a potential of a constant level deeper than the potential of.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a solid-state image pickup device.

[0002]

2. Description of the Related Art As a CCD solid-state image sensor, a FIT (frame
Lame interline transfer) CCD solid-state imaging
Image elements are known. Figure 8 shows a typical FIT CCD
FIG. 9 is a block diagram of the solid-state image pickup device 1, showing the CCD solid-state image pickup.
Clock pulse and vertical blank for driving the image element
King pulse φV-BLK is shown. Where clock clock
Rus uses the vertical transfer registers 3 and 5 of the image pickup unit 4 and the storage unit 6.
Vertical transfer clock pulse φIM for driving₁, ΦS
T₁Only about. Other vertical transfer clock pulse φ
IM₂, ΦIM₃, ΦIM_Four, ΦST₂, ΦST₃, Φ
ST_FourIs φIM ₁, ΦST₁It is almost the same as
I will omit

As shown in FIG. 8, a FIT type CCD solid-state image sensor 1 has a large number of light receiving portions 2 which are pixels arranged two-dimensionally, and a vertical transfer register 3 having a CCD structure on one side of each light receiving portion row. Is provided, a storage unit 6 including a plurality of vertical transfer registers 5 having a CCD structure corresponding to the vertical transfer register 3 of the imaging unit 4, a horizontal transfer register 7 having a CCD structure, and a horizontal transfer register 7. Storage unit 6 of transfer register 7
A drain region 8 for sweeping out excess charge, which is provided on the opposite side to the gate part 10, and a signal charge detection part 9 connected to the final stage of the horizontal transfer register 7.

The vertical transfer register 3 of the image pickup unit 4 has four-phase vertical transfer clock pulses φIM ₁ , φIM ₂ , φIM ₃ ,
The vertical transfer register 5 of the storage unit 6 driven by φIM ₄ has four-phase vertical transfer clock pulses φST ₁ , φST ₂ , φ
Driven by ST ₃ and φST ₄ , the horizontal transfer register 7 is set to 2
It is driven by phase horizontal transfer clock pulses φH ₁ and φH ₂ . A clock pulse φ _D is applied to the gate portion 10, and a DC voltage V _D is applied to the drain region 8.

The reading operation of the FIT type CCD solid-state image pickup device 1 is performed as follows. First, in the vertical blanking period 11, the read pulse 12 causes the signal charges photoelectrically converted in each light receiving unit 2 to be read from the light receiving unit 2 to the vertical transfer register 3. Next, the signal charge is transferred from the vertical transfer register 3 of the image pickup section 4 to the vertical transfer register 5 of the storage section 6 by the frame shift transfer pulse 13. Further, the line shift transfer pulse 14 transfers the signal charge for each horizontal line from the vertical transfer register 5 to the horizontal transfer register 7, and thereafter the signal charge is 2
It is transferred in the horizontal transfer register by the phase transfer clock pulses φH ₁ and φH ₂ and output from the signal charge detection unit 9.

After that, the excess charge sweep-out transfer pulse 15
Thus, the excess charge remaining in the vertical transfer register 3 of the image pickup unit 4 is swept out to the storage unit 6. This excess charge is stored in the storage unit 6.
It is swept out to the drain region 8 through the gate portion 10. Then, the light receiving unit 2 is again driven by the read pulse 12.
The signal charge is read out from. Thereafter, this is repeated to perform the read operation of the FIT type CCD solid-state imaging device 1.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The solid-state image sensor 1 requires extra operations for frame shift transfer and excess charge sweep-out transfer, as compared with the case of a normal IT (interline transfer) CCD solid-state image sensor. Therefore, the power consumption for driving the vertical transfer registers 3 and 5 in the FIT type CCD solid-state imaging device 1 is about three times as large as that in the IT type CCD solid-state imaging device. In addition, the FIT CCD solid-state image sensor 1 is generally used in a camera with a large optical system (1 inch or 2/3 inch) in pursuit of high image quality as compared with the IT CCD solid-state image sensor. Since the number is large, the chip area of the FIT type CCD solid-state image pickup device 1 becomes large, and as a result, the power consumption tends to be further increased.

Further, the problem of increased power consumption is not limited to just that, and since it is necessary to suppress the temperature rise of the CCD solid-state image sensor due to the increased power consumption, the camera portion around the CCD solid-state image sensor cannot be made small. Also causes the problem.

These problems are caused by, for example, HDTV (High
ENG (Electric New) for large-scale cameras such as for h Definition Television
It becomes particularly remarkable when it is suitable for sGathering) applications.

In view of the above points, the present invention provides a method for driving a FIT type solid-state image pickup device capable of reducing power consumption.

[0011]

According to the present invention, an image pickup section 24 for converting incident light into signal charges and transferring the signal charges.
In the method for driving a solid-state image sensor having a storage unit 26 that temporarily stores and transfers the signal charge from the image capturing unit 24, in the sweep-out transfer period T ₃ of the excess charge generated in the image capturing unit 24, the charge is accumulated. The transfer clock pulses φST _{1 to} φST ₄ applied to the vertical transfer register 25 of the unit 26 are stopped, and the potential in the vertical transfer register 25 is fixed to a potential deeper than the low level potential of the vertical transfer register 23 of the imaging unit 24. The excess charges are swept out and transferred.

In this case, it is preferable that the potential in the vertical transfer register 25 of the accumulating unit 26 is made constant, that is, the potential is made uniform so that the excess charges are swept out and transferred.

[0013]

According to the present invention, the transfer clock pulse φS applied to the vertical transfer register 25 of the accumulating section 26 in the sweep-out transfer period T ₃ of the surplus charge generated in the imaging section 24.
T _{1 to} φST ₄ are stopped, therefore the voltage is fixed, the potential in the vertical transfer register 25 is fixed to a deeper potential than the low level potential of the vertical transfer register 23 of the imaging unit 24, and the excess charge is swept out and transferred. Therefore, low power consumption can be achieved.

That is, the vertical transfer register 23 of the image pickup unit 24.
Then, transfer clock pulses φIM _{1 to} φIM ₄ for sweeping out excess charges are applied, and excess charges are accumulated in the storage unit 26.
Of the vertical transfer register 25. Since the vertical transfer register 25 of the storage unit 26 is fixed at a constant potential,
The surplus charges swept out in the storage section 26 are swept out and transferred to the drain region 28 (which is also considered to be based on the self-induced drift and the thermal diffusion mode). Therefore, the power consumption for sweeping out and transferring the excess charges in the storage unit 26 becomes almost 0, and the power consumption for driving the entire vertical transfer registers 23 and 25 is reduced.

Further, at this time, by fixing the potential in the vertical transfer register 25 of the storage unit 26 so as to be constant, the excess charge in the storage unit 26 can be transferred more smoothly.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for driving a FIT type CCD solid-state image pickup device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a typical FIT applied to the present invention.
1 shows the overall configuration of a CCD solid-state image sensor. In this FIT type CCD solid-state image pickup device 21, as in the case of FIG. 8 described above, a large number of light receiving portions 22 to be pixels are arranged two-dimensionally, and a vertical transfer register 23 having a CCD structure is provided on one side of each light receiving portion row. An image pickup unit 24 provided, a storage unit 26 composed of a plurality of vertical transfer registers 25 having a CCD structure corresponding to the vertical transfer register 3 of the image pickup unit 24, a horizontal transfer register 27 having a CCD structure, and a horizontal transfer register 27. The drain region 28 is provided on the side opposite to the storage unit 26 via the gate unit 30, and the signal charge detection unit 29 connected to the final stage of the horizontal transfer register 27.

Vertical transfer register 23 in image pickup unit 24
Is a 4-phase vertical transfer clock pulse φIM₁, ΦI
M₂, ΦIM₃, ΦIM_FourDriven by the
The vertical transfer register 25 is a 4-phase vertical transfer clock pulse.
Ruth φST₁, ΦST₂, ΦST ₃, ΦST_FourDriven by
The horizontal transfer register 27 is a two-phase horizontal transfer clock pulse.
Ruth φH₁, ΦH₂Driven by. In addition, the gate unit 30
Clock pulse φ_DHowever, the drain region 28 has a direct current
Voltage V_DAre applied respectively.

FIG. 2 shows the vertical transfer clock pulses φIM ₁ and φI in the first embodiment of the driving method of the present invention.
M ₂ , φIM ₃ , φIM ₄ , φST ₁ , φST ₂ , φS
T ₃ , φST ₄ and vertical blanking pulse φV-BL
The timing chart of K is shown.

FIG. 7 shows transfer clock pulses φIM and φST at the time of signal charge transfer in the vertical transfer registers 23 and 25.
Shows the waveform of.

FIG. 3 shows Y of the CCD solid-state image pickup device 21 of FIG.
FIG. 4 is a potential diagram showing the state of charge transfer at each timing when the driving method of FIG. 2 is used in the cross-sectional structure on the −Y line.

In the cross-sectional structure of FIG. 3, the second conductivity type, that is, P, is formed on the silicon semiconductor substrate 41 of the first conductivity type, for example, N type.
Shaped well region 42 is formed, and N type transfer channel region 43 is formed in P type well region 42. Imaging unit 24
Transfer clock pulses φIM ₁ , φIM ₂ , and φI on the transfer channel region 43 corresponding to the respective gates via the gate insulating film.
A plurality of transfer electrodes 45 to which M ₃ and φIM ₄ are applied are arrayed to form the vertical transfer register 23. Further, transfer clock pulses φST ₁ and φST are provided on the transfer channel region 43 corresponding to the storage section 26 via a gate insulating film, respectively.
₂ , transfer electrodes 4 to which φST ₃ and φST ₄ are applied
A vertical transfer register 25 is formed by arranging 6 in an array.

The horizontal transfer register 27 are each transfer clock pulses .phi.H ₁ in a direction perpendicular to the corresponding transfer paper over the channel region 43 via the gate insulating film FIG 4, .phi.H
A plurality of transfer electrodes 47 to which ₂ is applied are arranged and formed.

The drain region 28 is formed by an N ⁺ diffusion region 48, to which a DC voltage V _D is applied. This N
^On the region 43 between the ⁺ diffusion region 48 and the horizontal transfer register 28, the gate electrode 49 to which the clock pulse φ _D is applied is formed via the gate insulating film to form the gate unit 30.

Next, the read operation of the first embodiment will be described with reference to FIGS.

First, the time t of the vertical blanking period 50.
_{In 1} , the read pulse 51 causes each light receiving portion 22
The signal charge 61 photoelectrically converted by is read from the light receiving unit 22 to the vertical transfer register 23. The signal charges are transferred below the first and third transfer electrodes 45 to which the clock pulses φIM ₁ and φIM ₃ are applied (see FIG. 4A). After that, although not shown, the signal charges 61 of two lines corresponding to the odd field and the even field of the interlace are mixed and transferred.

Next, the signal charge 61 is converted into a signal charge 61 by the frame shift transfer pulse 52 in each of the vertical transfer clock pulses φIM _{1 to} φIM ₄ and φST _{1 to} φST ₄ .
Is transferred from the storage unit 26 to the vertical transfer register 25 at high speed. FIG. 4B shows a time point t ₂ within the frame shift transfer period T ₁ .
7 shows the transfer state of the signal charges in FIG.

Further, each vertical transfer clock pulse φIM
_The signal charges 61 are transferred to the horizontal transfer register 27 for each horizontal line by the line shift transfer pulse 53 in _{1 to} φIM ₄ and φST _{1 to} φST ₄ , and then the horizontal transfer clock pulses φH ₁ and φH in the horizontal transfer register 27. ₂ and is output by the signal charge detector 29. Figure 4C
Indicates the transfer state of signal charges at time t ₃ within the line shift transfer period T ₂ . During this period T ₂ , the gate section 30 has a high level potential.

After that, the surplus charge sweep-out transfer pulse 54
As a result, excess charges 62 such as smear components and dark current components remaining in the image pickup unit 24 are swept out to the storage unit 26. The surplus charges 62 are swept out from the accumulation unit 26 to the drain region 28 through the horizontal transfer register 27 and the gate unit 30.

Then, the signal charge 61 is read from the light receiving section 22 again by the read pulse 51. After that, this is repeated to perform the reading operation of the FIT type CCD solid-state imaging device.

Therefore, in the first embodiment, in particular,
In the excess charge sweep-out transfer period T ₃ , the image pickup unit 24 drives the vertical transfer clock pulses φIM _{1 to} φIM ₄ , and thus the excess charge sweep-out transfer pulse 54, but the accumulation unit 26 drives the vertical transfer clock pulses φST _{1 to} φST.
The clock of ₄ is stopped and fixed to a high level voltage, and the potential (so-called channel potential) in the vertical transfer register 25 in the storage unit 26 is aligned at a high level. As a result, low power consumption can be achieved.

During the surplus charge sweep-out transfer period T ₃ , the vertical transfer register 23 of the image pickup unit 24 stores the surplus charge 62 by the high-speed transfer clock pulse for the surplus charge sweep-out transfer, that is, the surplus charge sweep-out transfer pulse 54. 26, and the vertical transfer register 25 of the storage unit 26 sweeps and transfers the surplus charges 62 as shown in FIG. 4D. FIG. 4D shows a charge transfer state at time t ₄ within the surplus charge sweep-out transfer period T ₃ . It is believed that this drift transfer is primarily due to self-induced drift and thermal diffusion modes.

Since the charge transfer speed is slower in this drifting transfer than in the transfer by the high-speed transfer clock pulse in the image pickup unit 24, that is, the surplus charge sweep-out transfer pulse 54, a large amount of surplus charge 62 remains in the storage unit 26. Is expected. However, even if a large amount of the surplus electric charge 62 remains in the storage unit 26, it is sufficient that it is sufficiently swept out by the imaging unit 24.
In other words, in the present embodiment, since the image pickup unit 24 sweeps out the excess charge 62 by the high-speed transfer clock pulse 54, there is no practical problem. A surplus charge 62 is stored in the storage unit 26.
Even if the residual charge remains, this residual excess charge is swept out to the drain region 28 in the subsequent frame shift transfer, and no problem occurs.

In the first embodiment described above, the power consumption for driving the entire vertical transfer registers 23 and 25 can be estimated approximately as follows.

[0035]

[Table 1]

As shown in Table 1, the image pickup unit 24 and the storage unit 2
The power consumption in each transfer in 6 is the same in the related art, but in the present embodiment, the power consumption for sweeping out and transferring the excess charge in the storage unit 26 is almost zero. Therefore,
The power consumption for driving the entire vertical transfer registers 23 and 25 is reduced to approximately 5/6.

In this embodiment, four vertical transfer registers are used.
Although the phase drive mode is used, the present invention can be similarly applied to a vertical transfer register in another drive mode such as three-phase drive.

In the present embodiment, the surplus charge sweep-out transfer is performed.
All period of sending T₃At the transfer pulse of the storage unit 26
φST₁~ ΦST_FourStop the clock of the high level voltage
Fixed to, but not necessarily required. at least,
Surplus charge sweep-out transfer period T ₃Part of the storage
26 transfer pulses φST₁~ ΦST_FourStop and high level
To some extent, even if it is fixed at a fixed voltage.
be able to.

Next, a second embodiment of the driving method of the present invention will be described. In the present embodiment, in addition to the first embodiment, in the line shift transfer period T ₂ , the clocks of the line shift transfer pulses in the vertical transfer clock pulses φIM _{1 to} φIM ₄ of the image pickup unit 24 are stopped and fixed to a constant voltage. By doing so, the effect of reducing power consumption can be further enhanced.

FIG. 5 shows vertical transfer clock pulses φIM ₁ , φIM ₂ , φIM ₃ , φIM ₄ , and φ in the second embodiment.
The timing chart of ST ₁ , φST ₂ , φST ₃ , φST ₄ and vertical blanking pulse φV-BLK is shown.

FIG. 6 shows the charges when the driving method of FIG. 5 is used.
The state of transfer is shown at each timing t₁~ T _FourPotency shown for each
FIG.

In the present embodiment, the transfer pulse φS of the accumulating section 24 in the surplus charge sweep-out transfer period T ₃ .
The clocks of T ₁ , φST ₂ , φST ₃ , and φST ₄ are stopped and fixed to high level voltages, and the potentials in the vertical transfer registers in the storage section are aligned at high levels (see FIG. 6D).

Further, in the line shift transfer period T ₂ , the transfer pulses φIM ₁ , φIM ₂ , φI of the image pickup section 24.
The clocks of M ₃ and φ IM ₄ are stopped and fixed to a constant voltage (low level voltage), and the vertical transfer register 2 of the imaging unit 24
Align the potentials within 3 to be constant (Fig. 6
(See C).

According to this driving method, the vertical rotation of the storage unit 26 is performed.
Transmission clock pulse φST₁~ ΦST _FourSurplus charge in
The sweep pulse is omitted and the vertical rotation of the imaging unit 24 is performed.
Transmission clock pulse φIM₁, ΦIM₂, ΦIM₃, ΦI
M_FourSince the line shift transfer pulse of
Furthermore, low power consumption can be realized.

Even if the line shift transfer pulse of the image pickup section 24 is stopped in this way, there is no problem because the signal charge 61 is transferred by the storage section 26 as shown in FIG. 6C.

Further, if the potential in the vertical transfer register 23 of the image pickup unit 24 during the line shift transfer period T ₂ is set to a low level as in this embodiment, the image pickup unit 2
Since the excess charge 62 generated in 4 can be constantly swept out to the storage unit 26, a large amount of the excess charge 62 does not remain in the imaging unit 24.

In the second embodiment described above, the power consumption for driving the entire vertical transfer registers 23 and 25 can be roughly estimated as follows.

[0048]

[Table 2]

As shown in Table 2, the image pickup unit 24 and the storage unit 2
The power consumption in each transfer in 6 is the same in the related art, but in the present embodiment, the power consumption for sweeping out and transferring the excess charge in the storage unit 26 and the line shift transfer in the image pickup unit 24 are performed. The power consumption is almost zero.
Therefore, the power consumption for driving the vertical transfer registers 23 and 25 is reduced to about 2/3.

In this embodiment, the vertical transfer clock pulse of the image pickup section 24 is stopped during the entire line shift transfer period T ₂ , but it is not always necessary. Even if the vertical transfer pulses φIM _{1 to} φIM ₄ of the imaging unit 24 are stopped and fixed to the low level voltage at least in a part of the line shift transfer period T ₂ , the object of the present invention can be achieved to some extent.

Further, in this embodiment, in all the periods T ₃ of the excess charge sweeping transfer, the clocks of the transfer pulses φST _{1 to} φST ₄ of the accumulating section 26 are also accumulated in a part of the excess charge sweeping transfer period T _3. Even if the transfer pulses φST _{1 to} φST ₄ of the section 26 are stopped and fixed to the high level voltage, the object of the present invention can be achieved to some extent.

Further, in the present embodiment, the vertical transfer register is 4
Although the phase drive mode is used, the present invention can be similarly applied to a vertical transfer register in another drive mode such as three-phase drive.

In the first and second embodiments described above,
In the surplus charge sweep-out transfer, the potential of the vertical transfer register of the storage unit 26 is set to a constant potential (high level voltage) so that all the potentials in the vertical transfer register 25 are adjusted to the potential of the constant level.
Even if the potential level in the vertical transfer register 25 is not uniform, at least the potential in the vertical transfer register 25 is set to the imaging unit 2.
4 transfer pulse φST ₁ ~ so that the potential is deeper than the low level potential of the vertical transfer register 23.
Even if φST ₄ is stopped, the excess charge can be swept out. However, if all the potentials in the vertical transfer register 25 are made to have a constant level potential, the excess charges can be swept out smoothly.

[0054]

According to the present invention, the power consumption of the FIT type CCD solid-state image pickup device can be reduced. As a result, it is possible to reduce the power consumption and the size of the FIT CCD camera.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a typical FIT type CCD solid-state imaging device applied to the present invention.

FIG. 2 is a timing chart of transfer clock pulses showing the first embodiment of the driving method according to the present invention.

3 is a cross-sectional view taken along the line YY of FIG.

FIG. 4 is a timing chart (t _1- ) according to the first embodiment.
t ₄₎ is a potential diagram showing the charge transfer state of each.

FIG. 5 is a timing chart of transfer clock pulses showing a second embodiment of the driving method according to the present invention.

FIG. 6 is a timing chart (t ₁ ~) in the second embodiment.
t ₄₎ is a potential diagram showing the charge transfer state of each.

FIG. 7 is a vertical transfer clock pulse φIM according to the present invention.₁
~ ΦIM_Four, ΦST₁~ ΦST _FourIt is a waveform diagram of.

FIG. 8 is a configuration diagram of a FIT type CCD solid-state imaging device used for explaining a conventional example.

FIG. 9 is a timing chart of a transfer clock pulse according to a conventional driving method.

[Explanation of symbols]

1, 21 FIT CCD solid-state imaging device 2, 22 light receiving part 3, 23 vertical transfer register 4, 24 imaging part 5, 25 vertical transfer register 6, 26 storage part 7, 27 horizontal transfer register 8, 28 drain region 9, 29 the signal charge detection unit 10, 30 a gate part φIM ₁ ~φIM ₄ vertical transfer clock pulses 12 and 51 reading pulse 13,52 frameshift transfer pulses 14,53 line shift of the vertical transfer clock pulses φST ₁ ~φST ₄ storage section of the image pickup unit Transfer pulse 15,54 Surplus charge sweep transfer pulse

Claims (2)

[Claims] 1. A solid-state image sensor having an image pickup section for converting incident light into a signal charge and transferring the signal charge, and a storage section for temporarily storing and transferring the signal charge from the image pickup section. In the driving method of, in the sweep-out transfer period of the excess charge generated in the imaging unit,
The transfer clock pulse applied to the vertical transfer register of the storage section is stopped, the potential in the vertical transfer register is fixed to a potential deeper than the low level potential of the vertical transfer register of the imaging section, and the excess charge is swept out and transferred. A method for driving a solid-state imaging device, comprising: 2. The method of driving a solid-state image pickup device according to claim 1, wherein the potential in the vertical transfer register of the accumulating section is fixed to a fixed value to perform sweep-out transfer of the excess charge.