JPH0634355B2 - Digit line balance level correction method - Google Patents

Description

The present invention relates to a digit line balance level correction method in a MOS memory device adopted in a 1/2 Vcc precharge system.

[Conventional technology]

In a MOS memory device adopting the 1 / 2Vcc precharge method, the 1 / 2Vcc precharge level is slightly smaller than the correct 1 / 2Vcc level in consideration of the leak of the "H" side of the memory cell and the influence of α rays. It is better to set it lower to balance the sense margin against "H" and "L".

Conventionally, a method as shown in FIG. 3 has been used for this correction. In this method, dummy word lines DWL1 and DWL2 are provided, and a capacitance is inserted between them and the digit lines DL and ▲ ▼.

FIG. 4 is an operation waveform diagram thereof. The case where the cell is “H” will be described below. First, the precharge signal φ _P becomes “L”, and then the word line WL rises. The digit line connected to the memory cell accompanying this ▲ ▼
The dummy word line DWL1 connected by a capacitance to the digit line DL on the opposite side falls. Then, the level of the digit line DL on the "L" side is slightly lowered from 1/2 Vcc by the coupling. Cell "H" that deteriorates due to this correction
The side sense margin is improved.

[Problems to be solved by the invention]

In the conventional digit line balance level correction method described above, since a dummy word line is added and a capacitive coupling is inserted between the dummy word line and the digit line, the coupling of the digit lines is substantially performed through the dummy word line. Therefore, there is a drawback that the digit line of interest is strongly affected by noise from other digit lines during the sensing operation.

[Means for solving problems]

The digit line balance level correction method of the present invention corrects the 1/2 Vcc level by capacitance division by short-circuiting the digit line pair and connecting an external capacitor during the precharge period.

[Work]

Since the digit line pair is short-circuited by the transistor, the digit line does not receive noise from other digit lines.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a MOS memory device to which the digit line balance level correction method of the present invention is applied.

Digit line DL, ▲ ▼ is the digit line DL, ▲
Transistors Q ₂₂ and Q ₂₃ for connecting ▼ to the external capacitance C ₂₁ are connected respectively, and a digit line balancing transistor Q ₂₁ is connected between the digit lines DL and ▲ ▼ to connect these transistors Q ₂₁ , Q ₂₂ , A precharge signal φ _P1 which becomes “H” during precharge is applied to the gate of Q ₂₃ . In addition, a transistor Q ₂₄ is connected in parallel with the external capacitor C ₂₁ to pull out the electric charge stored in the capacitor C ₂₁ during the active period of the memory and reset it. The gate of the transistor Q ₂₄ is active. reset signal phi _P2 which becomes sometimes "H" is applied.

FIG. 2 is an operation waveform diagram when the cell is "H". The precharge signal φ _P1 becomes “L”, the word line WL rises, the sensing operation starts, and the digit line “H”,
"L" is settled. During this active period, the reset signal φ _P2 becomes “H”, and the level of the node N ₂₁ is pulled down. Next, when the precharge operation is started, the reset signal φ _P2 and the word line WL fall first, and then the precharge signal φ _P1 becomes “H”. Then, the digit line DL, ▲
▼ is short-circuited by the transistor Q ₂₁ , and the level of the digit line DL and ▲ ▼ is 1/2 Vcc in principle due to capacitance division.
At the same time, the digit line DL and ▲ ▼ are connected to the external capacitance C ₂₁ by the transistors Q ₂₂ and Q ₂₃ ,
Since the capacitance division with the external capacitance C ₂₁ is also added, the level of the digit line DL, ▲ ▼ is eventually lowered from the accurate 1/2 Vcc to the corrected 1/2 Vcc level.

〔The invention's effect〕

As described above, the present invention can balance the sense margins of the cells "H" and "L" by connecting the digit line to the external capacitance during precharge and correcting the 1/2 Vcc balance level. There is an effect that it is possible and does not become a noise source at the time of sensing operation.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of a MOS memory device to which the digit line balance level correction method of the present invention is applied, FIG. 2 is a waveform diagram showing the operation of the embodiment of FIG. 1, and FIG.
FIG. 4 is a circuit diagram showing a conventional example, and FIG. 4 is a waveform diagram showing the operation of the conventional example of FIG. φ _P1 …… Pre-charge signal, φ _P2 …… Reset signal, WL …… Word line, DL, ▲ ▼ …… Digit line, Q ₂₁ , Q ₂₂ , Q ₂₃ , Q ₂₄ …… Transistor, C ₂₁ …… Capacitance , N ₂₁ …… Nodal point.

Claims (2)

[Claims] 1. A first and a second digit line connected to a sense amplifier, and a memory cell connected to the first sense amplifier. According to data of the memory cell during an active period. The first and second digit lines are respectively set to a high level or a low level, the first and second digit lines are short-circuited during a precharge period, and the capacitance is divided by the respective capacitances of the first and second digit lines. According to a digit line balance level correction method for precharging the first and second digit lines to a predetermined level, the first and second digit lines are short-circuited and external capacitance In addition to the capacitance division by the capacitance of the first and second digit lines, the capacitance division by the external capacitance is further performed. Digit line balance level correction method characterized by correcting the predetermined level to a lower level by a predetermined value than cc level. 2. The digit line balance level correction method according to claim 1, wherein the electric charge stored in the external capacitance is discharged during the active period.