JPH0634504B2 - Television receiver - Google Patents

Description

TECHNICAL FIELD The present invention relates to a television receiver.

<Prior Art> Currently, in the state of television broadcasting in Japan, the number of broadcasting stations that can be received in one region is at most 9 channels, so if an image of about 9 channels can be simultaneously displayed on one screen, the viewer will be This is convenient because you can check the broadcast contents of all broadcast channels in the area at a glance, and you do not need to perform channel switching operations many times to select the broadcast channel you want to watch.

On the other hand, conventionally, there has already been proposed a television receiver capable of simultaneously displaying two-channel images of a main and a sub-screen on one screen of a CRT (for example, Japanese Patent Laid-Open No. 49-2).
No. 419), which has been partially put into practical use.

However, the television receiver as described above can display images of only two channels on one screen, and if more images are to be displayed, tuners must be added by the number of the images. However, it is practically impossible to simultaneously display images of all broadcasting channels in one area on one screen by the conventional method.

<Objects of the Invention> The present invention has been made in view of the above problems, and a plurality of images can be simultaneously displayed on one screen by using a single tuner, and a receiver is provided. The purpose of the present invention is to make it easy to check the contents of all broadcasting channels in a region and to eliminate the trouble of selecting channels without complicating or enlarging the configuration of.

<Structure of the Invention> In order to achieve the above object, the present invention has a single tuner, switches the channels of the tuner at a fixed cycle, stores the video signal of each channel, and stores the stored video signal. In a television receiver capable of sequentially reading out and displaying images of a plurality of channels on one screen, a channel selection unit for switching the receiving channels of the tuner and one image portion of a video signal of one of the selected channels. A buffer memory for storing the audio, an audio multiplex decoder unit for determining the audio mode of the audio multiplex signal of any one of the selected channels, and a display for storing one image of each video signal of the selected multiple channels. From a memory, a buffer memory control unit that controls writing to the buffer memory based on a synchronization signal in a received radio wave, and a reference oscillation circuit And a display memory control unit for generating a television synchronizing signal based on the clock pulse and controlling writing / reading to / from the display memory in synchronization with the television synchronizing signal, and a front stage of a video output unit and a deflection output unit for the CRT. There, a video signal switching unit and a synchronization signal switching unit for switching inputs to the both units to the display memory side, a central control unit for controlling each unit, and a CRT display mode are operated for selection. When displaying a plurality of images on one screen, the central control unit stores a video signal for one image in the buffer memory during one display scanning period of the synchronization signal of the channel. The contents of the buffer memory are transferred to the display memory during the vertical blanking period of the television synchronization signal, and the contents stored in the television are also transferred. A plurality of displayed signals are read out during the display scanning period of the period signal and transmitted to the CRT, and further, the voice mode information determined by the voice multiplex decoder section during this display scanning period is also transmitted to the CRT. Each image of the channel is updated and the channel number of each channel is displayed on each of the displayed images, and the type of the audio mode of each channel is displayed in the display color of the channel number. It was done.

<Examples> Hereinafter, the present invention will be described in detail based on Examples shown in the drawings.

FIG. 1 is a block diagram of the entire television receiver of the present invention, which comprises a main body circuit portion A and an image processing circuit portion B.

The main circuit portion A includes an antenna 1 and a single tuner 2
A video amplification section 3, a video signal processing section 4, a synchronization signal processing section 5, a video output section 8, a deflection output section 9, and a CRT 1.
0 and a deflection coil 10a, a video signal switching unit 6 is provided between the video signal processing unit 4 and the video output unit 8, and a synchronization signal processing unit 5 and the deflection output unit 9 are provided. The synchronizing signal switching unit 7 is interposed between the two.

The image processing circuit portion B also selects a channel selection section 11 for switching the reception channel of the tuner 2, a multiplexer 12 for introducing the video signal from the video signal processing section 4, and an analog signal from the multiplexer 12 for converting it into a digital signal. An A / D converter 13, a buffer memory 15 for temporarily storing one field of a video signal, a buffer memory control unit 14 for controlling writing to the buffer memory 15 based on a synchronizing signal of a received radio wave, and a clock pulse. The generated reference oscillation circuit 16 and a plurality of channels (9 channels in this embodiment) to be displayed on the CRT 10.
1 field for each video signal, or 1
A display memory 18 that stores one frame of a video signal of a channel, and a display memory control unit 17 that generates a television synchronizing signal from the clock pulse and controls writing and reading to and from the display memory 18 by the television synchronizing signal. And a D / A for converting the digital video signal read from the display memory 18 into an analog amount
A central control unit (CPU) 20 for controlling the converter 19, the buffer memory control unit 14, the display memory control unit 17, the video signal switching unit 6, the synchronization signal switching unit 7, and the like.
A program ROM 21 for storing the program of the central control unit 20, a work RAM 22, an operation unit 23 operated to select a display mode of the CRT 10, and the channel selection unit based on a signal from the central control unit 20. 11, a video signal switching unit 6, and a control signal output unit 24 for operating the synchronization signal switching unit 7.

Further, when a screen of a plurality of channels is displayed on one screen, an audio IF detection unit 39 and an audio multiplex decoder 40 are provided in order to also display the type of audio multiplex broadcast on each channel screen. .

In the above configuration, by operating the operation unit 23 to select the display mode, a desired 1-channel image is displayed on the CRT 10 screen as in a normal television receiver, and the CRT 10 screen is also displayed. Images of a plurality of channels (images of 9 channels in this embodiment) are displayed at the same time, or images of 1 channel are displayed as a still image on the screen of the CRT 10. The buffer memory control unit 14 and the display will be described below. The operation in each mode will be described while describing the more detailed configuration of the memory control unit 17.

(B) Normal display mode The television radio waves of the channel received by the antenna 1 and tuned by the tuner 2 are amplified by the video amplification section 3,
It is input to the video signal processing unit 4 and the synchronization signal processing unit 5.
In the video signal processing unit 4, the video signal is a luminance signal (Y signal).
And two color difference signals (RY signal and BY signal). On the other hand, the sync signal processing unit 5 separates the received signal into a horizontal sync signal and a vertical sync signal and outputs them. At this time, in the video signal switching unit 6, the switching piece 6c is connected to the contact 6a, and the output of the video signal processing unit 4 is input to the video output unit 8. The other synchronizing signal switching unit 7
In, the switching piece 7c is connected to the contact 7a, and the output of the synchronization signal processing section 5 is input to the deflection output section 9. In this way, since the video signal is input to the main body of the CRT 10 and the synchronization signal is input to the deflection coil 10a thereof, a desired 1-channel image is displayed on the screen of the CRT 10.

(B) When the multi-mode is set in the multi-channel image display (multi-mode) operation unit 23, the CPU 20
Operates to control each unit so as to display a plurality of images on the screen of the CRT 10. First, a signal from the CPU 20 causes the control signal output unit 24 to the channel selection unit 11 to select one of a plurality of channels. 1 channel, eg A
The tuner 2 is instructed to tune to a channel, and the tuner 2 tunes in to channel A. The video signal of the A channel is input to the multiplexer 12 via the video amplification unit 3 and the video signal processing unit 4. The multiplexer 12 sequentially extracts the Y signal, the RY signal, and the BY signal from the video signals and sends them to the A / D converter 13. The A / D converter 13 converts an analog signal into a digital signal. The video signal thus converted into a digital amount is stored in the buffer memory 15 through the buffer memory control unit 14 at the timing of the buffer memory control unit 14.

FIG. 2 is a block diagram showing the internal configuration of the buffer memory control unit 14, and FIG. 3 is a time chart of the buffer memory control unit 14 in the multi-mode. The operation when controlling writing to the memory will be described. The command signal Sb from the CPU 20 is input to the writing period detector 26. The writing period detecting section 26 introduces a synchronizing signal of the received radio wave, and in response to the command signal Sb, generates a writing pulse of the display scanning period length of the one field from the synchronizing signal of the receiving radio wave. To be precise, the write pulse has a length from the falling edge of the vertical synchronizing signal of the received radio wave to the rising edge of the next vertical synchronizing signal, as shown in FIG. While the write pulse is rising, write row counter 2
7 and the write column counter 28 count clock pulses from the reference oscillation circuit 16 and output address signals in the row direction and the column direction, respectively. At this time, the changeover switches 30 and 31 connected to the write row counter 27 and the write column counter 28 respectively change the changeover piece 30.
c and 31c are connected to the contacts 30a and 31a, so that the outputs of the write row counter 27 and the write column counter 28 are supplied to the buffer memory 15, and the storage address of the buffer memory 15 is designated. On the other hand, the video signal stored in the buffer memory 15 is supplied through the multiplexer 12, the A / D converter 13 and the changeover switch 29. In the multiplexer 12, three contact points 12a, which are synchronized with the horizontal synchronizing signal of the received radio wave,
Since 12b and 12c are sequentially closed, the Y signal, the R-Y signal, and the B-Y signal are sequentially sent to the A / D converter 13 for each horizontal synchronization period, A / D converted, and stored in the buffer memory 15. It

In this way, when one field of the video signal of the required channel (A channel) is stored in the buffer memory 15, the write row counter 27 and the write column counter 28.
Operation is stopped, and in the changeover switches 30 and 31, the changeover pieces 30a and 31a are switched to the other contacts 30b and 31b, and the address signal line of the buffer memory 15 is changed to C.
The changeover piece 29c is connected to the address bus of the PU20, and the changeover piece 29c is changed over to the contact point 29b in the changeover switch 29 so that the data signal line of the buffer memory 15 is connected to the data bus of the CPU20. This state is the buffer memory 1
In the state in which the stored contents of No. 5 can be transferred to the display memory 18 and the display memory 18 side is ready to accept the transfer, the transfer is started. In FIG. 2, reference numeral 25 is a still image control unit and 32 is a ternary counter.

On the other hand, the display memory 18 is set with the same number of storage areas corresponding to the images of a plurality of channels (9 channels) to be displayed on the CRT 10, and the video signals stored in these storage areas are converted from clock pulses. The CRT1 is accessed by the generated address signal and also by the television synchronizing signal which is also generated from the clock pulse.
Displayed at 0.

The operation in this case will be described based on the block diagram of the display memory control unit 17 in FIG. In response to a command from the CPU 20, the control signal is sent from the control signal output unit 24 to the video signal switching unit 6,
It is sent to the synchronizing signal switching unit 7, and the switching pieces 6c and 7c of both switching units 6 and 7 are switched to the contacts 6b and 7b, respectively, and as a result, the input terminals of the video output unit 8 and the deflection output unit 9 are respectively displayed memory. Switch to 18 side. In the display memory control unit 17, the horizontal synchronizing signal generation counter 33 counts clock pulses to generate a television horizontal synchronizing signal, and also generates a column direction address signal for the display memory 18 synchronized with the television horizontal synchronizing signal. To do.
The vertical synchronizing signal generation counter 34 generates a television vertical synchronizing signal based on the television horizontal synchronizing signal from the horizontal synchronizing signal generating counter 33, and at the same time, generates a row direction address signal for the display memory 18. The display control circuit 35 switches the switches 36, 3 in correspondence with the television horizontal synchronizing signal and the television vertical synchronizing signal.
7, 38 are controlled. In the changeover switches 36 and 37, the changeover pieces 36b and 37b are connected to the contact points 36a and 37a, respectively.
The address signals generated in 3, 34 are respectively supplied to the display memory 18, and the address signals generate the display memory 1.
8 is accessed and the stored contents of the display memory 18 are read. At this time, since the contact 38a of the changeover switch 38 is closed, the video signal read from the display memory 18 is sent to the D / A converter 19 and converted into an analog signal. Input to the output unit 8. In addition, the horizontal synchronization signal generation counter 3
The television horizontal synchronizing signal generated in 3 and the television vertical synchronizing signal generated in the vertical synchronizing signal generation counter 34 (hereinafter, collectively referred to as television synchronizing signal) are deflected through the synchronizing signal switching unit 7 and output to the deflection output unit. Enter in 9. Then, during the display scanning period of these television synchronizing signals, the video signals of a plurality of channels stored in the display memory 18 are displayed on the CRT 10, and the image of a predetermined channel among the images of a plurality of channels in one screen is updated and displayed. It

During the vertical blanking period of the television synchronizing signal, the changeover pieces 36b and 37b of the changeover switches 36 and 37 are switched to the contact points 36c and 37c by the control signal of the display control circuit 35, and the address signal line of the display memory 18 is changed. CPU20
, And the contact 38c of the changeover switch 38 is closed to connect the data signal line of the display memory 18 to the data bus of the CPU 20. This state is
This is a state in which data transfer from the buffer memory 15 can be received. At this time, on the buffer memory 15 side, the address bus of the CPU is connected to the address signal line of the buffer memory 15, and the data bus of the CPU 20 is connected to the buffer memory 15.
If it is connected to the data signal line of, the display memory 18 and the buffer memory 15 are connected via the address bus and the data bus of the CPU 20. If connected in this way, CP
The U20 reads out the stored contents from the buffer memory 15 and transfers it to the corresponding storage area of the display memory 18.
This transfer is repeated for each vertical blanking period of the television synchronizing signal, and a required 1 channel (A channel) video signal for 1 field is transmitted. When this is displayed on the CRT 10, the next channel (B in this example) is displayed. The next cycle of storing and displaying one field of the video signal of the (channel) is started, and the same operation as the above-described operation of storing and displaying the video signal of the A channel is repeated. In this way, one field of the video signals of the B to I channels sequentially selected in this manner is temporarily stored in the buffer memory 15, then transferred to the display memory 18, read from the display memory 18, and read out from the CRT 10 screen. It is displayed at a predetermined place. Further, when one field is stored in the buffer memory 15, the audio mode of the audio multiplex signal in advance by the audio IF detection unit 39 and the audio multiplex decoder 40 is the stereo broadcast mode, the bilingual broadcast mode, or the monaural broadcast mode. This is determined in advance, and this determination output is connected to the data bus of the CPU 20. When the image data is transferred from the buffer memory 15 to the display memory 18, the program RO
Based on the output signals from M21 and the audio multiplex decoder 40, a channel number display signal whose color is designated according to the type of audio mode of each channel is also transferred. As a result, on the screen of the CRT 10, as shown in FIG. 5, the channel numbers corresponding to the respective channels are also displayed in the upper right corner of each image of the nine channels A, B, C ... I. Each channel number is color-coded according to the audio mode at that time, for example, in the case of stereo broadcasting, yellow,
It is colored red in bilingual broadcasting and cyan in monaural broadcasting.

(C) Still image display (still mode) When the still mode is selected on the operation unit 23, the CPU 20
The channel selection in the tuner 2 is fixed to any one channel (D channel in this example) by the command from.
Further, the CPU 20 outputs a command signal Sa to the still image control unit 25 of the buffer memory control unit 14, and the still image control unit 25 outputs a signal corresponding to the command signal Sa to the writing period detection unit 26. In response to this, the writing period detection unit 26 generates a writing pulse having a length of two display scanning periods of the reception radio wave of the predetermined channel (D channel) as shown in the time chart of FIG. This write pulse is exactly the length from the fall of the vertical sync signal of the received radio wave to the rise of the second vertical sync signal, and the write pulse enables writing of the video signal for one frame. . The write pulse is sent to the horizontal sync signal generation counter 33 and the vertical sync signal generation counter 34 of the display memory control unit 17. The write pulse is also sent to the changeover switches 36, 37 of the display memory control unit 17, and the changeover switches 36, 3 are
7, the switching pieces 36b and 37b are connected to the contacts 36a and 37.
Switch to a. Therefore, the address signal is supplied to the display memory 18 while the write pulse is rising, that is, during the two display scanning periods of the synchronizing signal of the received radio wave. on the other hand,
On the buffer memory 15 side, the multiplexer 12 switches the contacts in a predetermined order as shown in FIG. That is, the contact 12a is closed during the first display scan period of the received radio wave, and only the Y signal is introduced, and the two contacts 12b and 12c are alternately closed every horizontal synchronization period during the second display scan period, and R-Y signal,
The BY signals are introduced alternately. These video signals are A /
After being converted into a digital signal by the D converter 13, it is sent to the changeover switch 38 in the display memory control unit 17 via the changeover switch 29. At this time, the contact 38b of the changeover switch 38 is closed, so that the video signal sent from the buffer memory control unit 14 side is input to the data signal line of the display memory 18. An address signal synchronized with the display scanning period of the received radio wave is already stored in the display memory 18, so that one frame of a video signal of a predetermined channel is stored in a predetermined storage area by addressing the address signal. To be done.

The operation of reading the video signal for one frame stored in the display memory 18 and displaying the video signal on the CRT 10 is the same as in the case of the (b) multimode, and the video signal switching unit 6,
The respective switching pieces 6c, 7c of the synchronization signal switching unit 7 are switched to the contacts 6b, 7b, whereby the respective input terminals of the video output unit 8 and the deflection output unit 9 are switched to the display memory 18 side. In the display memory control unit 17, the horizontal synchronizing signal generation counter 33 generates a television horizontal synchronizing signal and a column direction address signal for the display memory 18 synchronized with the television horizontal synchronizing signal. Further, the vertical synchronizing signal generation counter 34 generates a television vertical synchronizing signal and a row direction address signal for the display memory 18. At this time, the changeover switches 36 and 37 are controlled by the display control circuit 35 so that the changeover pieces 36b and 37b are brought into contact with the contacts 36a and 37.
The television horizontal synchronizing signal and the television vertical synchronizing signal are supplied to the display memory 18, respectively, and the display memory 18 is accessed by the television synchronizing signal to read the stored contents of the display memory 18. Be done. Further, since the contact 38a of the changeover switch 38 is closed, the video signal read from the display memory 18 is sent to the D / A converter 19 and converted into an analog signal, and the video signal is output through the video signal switching unit 6. Enter in 8. Further, the television sync signal is input to the deflection output unit 9 through the sync signal switching unit 7. As a result, the predetermined 1-channel (D-channel) video signal stored in the display memory 18 is displayed on the CRT 10. After that, the stored contents of the display memory 18 are not updated and the same stored contents are continuously read and displayed.
At T10, an image of a predetermined channel (D channel) as shown in the configuration diagram of FIG. 7 is displayed in a still state.

<Effects of the Invention> As described above, according to the present invention, since the current audio mode of each channel is displayed together with the images of a plurality of channels, which channel is currently performing audio multiplex broadcasting? Also, it is possible to instantly confirm whether the content is a stereo broadcast or a bilingual broadcast, and it is possible to see at a glance the audio modes of a plurality of channels.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a buffer memory control unit thereof, FIG. 3 is a time chart showing a storage operation in a multi mode, and FIG. 4 is a display memory control unit. FIG. 5 is a block diagram of the CRT screen in the multi mode, FIG. 6 is a time chart showing a storage operation in the still mode, and FIG. 7 is a C in the still mode.
It is a block diagram of RT screen. 2 ... Tuner, 6 ... Video signal switching unit, 7 ... Sync signal switching unit, 10 ... CRT, 11 ... Channel selecting unit, 14 ... Buffer memory control unit, 15 ... Buffer memory, 17 ... Display memory control unit, 18 ... Display memory , 20 ... Central control unit (CPU), 23 ... Operation unit, 40 ... Audio multiplex decoder

Continuation of the front page (56) References JP-A-49-46330 (JP, A) JP-A-49-129419 (JP, A) JP-A-55-18157 (JP, A)

Claims (1)

[Claims] 1. A single tuner is provided, and the channels of the tuner are switched at a constant cycle to store the video signals of the respective channels, and the stored video signals are sequentially read to display images of a plurality of channels in one screen. A television receiver capable of displaying, a tuning unit for switching the reception channel of the tuner, a buffer memory for storing one image of a video signal of one of the selected channels, and the tuning unit. The audio multiplex decoder section that determines the audio mode of the audio multiplex signal of any of the selected channels, the display memory that stores one image of each video signal of the selected multiple channels, and the synchronization signal in the received radio wave A buffer memory control unit for controlling writing to the buffer memory based on the above; and a television receiver based on a clock pulse from the reference oscillation circuit. A display memory control unit for generating a sync signal and controlling writing / reading to / from the display memory in synchronization with the television sync signal, and a video output unit for the CRT and a deflection output unit in front of the both units. A video signal switching unit and a synchronization signal switching unit for switching the input of the respective to the display memory side, a central control unit for controlling each unit, and an operation unit operated for selecting a display mode of the CRT, When displaying a plurality of images on the screen, the central control unit stores a video signal for one image in the buffer memory during one display scanning period of the synchronizing signal of the channel, and then stores the vertical signal of the television synchronizing signal. The contents of the buffer memory are transferred to the display memory during the blanking period, and the stored contents are read during the display scanning period of the television sync signal. To the CRT and further to the CRT together with the audio mode information determined by the audio multiplex decoder section during this display scanning period to update each image of a plurality of displayed channels. A television receiver, characterized in that a channel number of each channel is displayed on each displayed image so as to be overlapped with each other, and the type of the audio mode of each channel is displayed in the display color of the channel number.