JPH06349976A - High-density wiring board and manufacturing method thereof - Google Patents

High-density wiring board and manufacturing method thereof

Info

Publication number
JPH06349976A
JPH06349976A JP15634093A JP15634093A JPH06349976A JP H06349976 A JPH06349976 A JP H06349976A JP 15634093 A JP15634093 A JP 15634093A JP 15634093 A JP15634093 A JP 15634093A JP H06349976 A JPH06349976 A JP H06349976A
Authority
JP
Japan
Prior art keywords
wiring
inspection
electrode
plating
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15634093A
Other languages
Japanese (ja)
Inventor
Kiyoshi Mizushima
清 水島
Mamoru Mori
護 毛利
Motoharu Miyakoshi
基晴 宮越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIKKO CO
Nikko KK
Original Assignee
NIKKO CO
Nikko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIKKO CO, Nikko KK filed Critical NIKKO CO
Priority to JP15634093A priority Critical patent/JPH06349976A/en
Publication of JPH06349976A publication Critical patent/JPH06349976A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】 【構成】 多層配線基板の製品部の外側に検査用電極領
域が設けられ、基板に形成した高密度配線の端子が該検
査用電極領域に導かれ、配線間隔を広げた検査用電極を
形成していることを特徴とする高密度配線基板。 【効果】 ファインピッチ配線でも、検査用電極を用い
ることによって、現用の接触型検査機によって配線を検
査できるので、従来の多層基板製造技術によって高密度
配線を有する多層配線基板を容易に製造することができ
る。検査用電極は使用後に切除するので、製品上の問題
を生じない。
(57) [Summary] [Structure] The inspection electrode region is provided outside the product part of the multilayer wiring board, and the terminals of the high-density wiring formed on the substrate are guided to the inspection electrode region to widen the wiring interval. A high-density wiring board having inspection electrodes formed thereon. [Effect] Even with fine-pitch wiring, the wiring can be inspected by an existing contact-type inspecting machine by using the inspection electrodes, so that a multilayer wiring board having high-density wiring can be easily manufactured by a conventional multilayer board manufacturing technique. You can Since the inspection electrode is cut off after use, there is no problem with the product.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体のマルチチップ
モジュール(MCM)の高密度実装が可能なファインピ
ッチ配線を有する多層配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having a fine pitch wiring capable of high-density mounting of a semiconductor multi-chip module (MCM).

【0002】[0002]

【従来技術とその問題点】電子機器の小型化・高性能化
に伴ない、半導体チップの実装基板についても、高密度
化が求められており、その対応策として、高密度配線基
板上に半導体チップをケ−ジングせずに直接基板上に搭
載するベアチップ直接実装が行なわれるようになってい
る。この典型的な例として、一つの基板上に多数のベア
チップを搭載するマルチチップモジュール(MCM)が
知られている。このMCMは高密度配線基板の上に半導
体チップを直接搭載することによってパッケージ伝達の
遅れ排除し、基板上でのチップ間の信号伝達を最小限に
して高速化を図ろうとするものである。
2. Description of the Related Art With the miniaturization and high performance of electronic devices, the mounting density of semiconductor chip mounting boards is also required. As a countermeasure, semiconductors are mounted on high density wiring boards. Bare chip direct mounting is carried out in which chips are directly mounted on the substrate without casing. As a typical example of this, a multi-chip module (MCM) in which a large number of bare chips are mounted on one substrate is known. This MCM is intended to eliminate the delay of package transmission by directly mounting a semiconductor chip on a high-density wiring board and to minimize the signal transmission between chips on the board to achieve high speed.

【0003】上記MCMは基板の材質および構造に基づ
き、一般に (a)MCM−D、 (b)MCM−C、 (d)MC
M−Lの3種に分類されている。MCM−Dは、金属基
板やセラミック基板上に、ポリイミドなどの有機絶縁材
と金属導体を用い、薄膜技術(deposition)により多層構
造の高密度配線を形成したものであり、MCM−Cはセ
ラミックや低温焼成可能な低誘電率のガラス・セラミッ
ク基板を用い、またMCM−Lは樹脂質積層板を用い、
プリント配線技術によって高密度配線を形成したもので
ある。このようなMCMにおける課題として、基板配線
の多層化とファインピッチ化が挙げられる。高密度実装
を達成するには、基板上に搭載された多数のチップに適
応した高密度の配線が必要であり、基板の配線ピッチ
は、実装密度を直接に制約する要因となる。例えば半導
体チップの電極端子が0.1 〜0.15mm程度のピッチに形成
できても、実装基板上のチップ用電極の配線ピッチがこ
れより広い限り、このピッチに応じた高密度実装を実現
しえない。
The above MCM is generally (a) MCM-D, (b) MCM-C, (d) MC based on the material and structure of the substrate.
It is classified into three types of ML. The MCM-D is one in which an organic insulating material such as polyimide and a metal conductor are used on a metal substrate or a ceramic substrate to form a high-density wiring having a multilayer structure by a thin film technology (deposition). A low dielectric constant glass / ceramic substrate that can be fired at low temperature is used, and MCM-L is a resin laminated plate.
High-density wiring is formed by the printed wiring technology. Problems in such an MCM include multilayering of substrate wiring and fine pitch. In order to achieve high-density mounting, high-density wiring adapted to a large number of chips mounted on the substrate is required, and the wiring pitch of the substrate is a factor that directly limits the mounting density. For example, even if the electrode terminals of the semiconductor chip can be formed with a pitch of about 0.1 to 0.15 mm, as long as the wiring pitch of the chip electrodes on the mounting substrate is wider than this, high density mounting corresponding to this pitch cannot be realized.

【0004】従来、スクリーン印刷による微細配線形成
の限界、配線材料として用いられていたAgのマイグレ
ーションによる配線間隔の限界、及び多層配線基板材料
として用いられるグリーンシートにおけるビアホール径
の微細化の限界等により、基板配線のファインピッチ化
が制限されてきた。しかし、製版技術の進歩やスクリー
ン印刷用ペーストの改良により線幅/ピッチ=50/5
0μm の配線印刷も可能となり、メッキによるNiのよ
うな耐マイグレーション性にすぐれた良導体の使用や、
グリーンシートの加工性の向上などにより、0.1 〜0.15
mm程度の高密度配線基板も製造可能となりつつある。そ
こで、こうした高密度配線基板について、基板上の導体
配線検査が問題となっている。
Conventionally, due to the limitation of fine wiring formation by screen printing, the limitation of wiring spacing due to migration of Ag used as a wiring material, and the limitation of miniaturization of via hole diameter in a green sheet used as a multilayer wiring board material. , The fine pitch of the board wiring has been limited. However, line width / pitch = 50/5 due to progress in plate making technology and improved screen printing paste.
It is also possible to print wiring of 0 μm, and use a good conductor with excellent migration resistance such as Ni by plating,
0.1-0.15 due to improvements in green sheet processability
It is becoming possible to manufacture high-density wiring boards on the order of mm. Therefore, for such a high-density wiring board, inspection of the conductor wiring on the board has become a problem.

【0005】半導体基板上の配線検査の方法として、一
般に、コンタクトプローブを用いた検査が行われてい
る。これは、基板の表面配線に位置合わせした複数のプ
ローブを基板に直接接触させるか、または検査を必要と
するパターンに応じて孔開けされた絶縁マスクを基板に
被せた上で上記プローブを基板に押し当て、一括または
適当なプログラムに従ってプロ−ブに電圧を引加して通
電状態を検査する方法である。しかし、従来使用されて
いるプローブはそのプローブ間のピッチ限界が0.3mm 程
度であり、ピッチが0.1 〜0.15mm程度のファインピッチ
配線を検査できない。また基本的にはプローブで配線を
傷付ける可能性があるので可能な限り配線に接触しない
検査方法が望まれる。このような非接触式の検査装置も
知られているが、これによれば上記間隔の配線検査も可
能であるが、この種の装置は高価であり、また操作も繁
雑であるため一般には使用し難い。
As a method for inspecting wiring on a semiconductor substrate, generally, an inspection using a contact probe is performed. This is done by directly contacting a plurality of probes aligned with the surface wiring of the substrate to the substrate, or by covering the substrate with an insulating mask that is perforated according to the pattern requiring inspection and then applying the probe to the substrate. It is a method of pressing and applying a voltage to the probe all at once or according to an appropriate program to inspect the energized state. However, the pitch limit between probes used in the past is about 0.3 mm, and fine pitch wiring with a pitch of about 0.1 to 0.15 mm cannot be inspected. Further, basically, the probe may damage the wiring. Therefore, an inspection method that does not contact the wiring as much as possible is desired. Although such a non-contact type inspection device is also known, it is possible to inspect the wiring at the above intervals, but this type of device is expensive and the operation is complicated. It's hard to do.

【0006】[0006]

【課題の解決手段】本発明は、上記問題を解決した高密
度配線基板とその製造方法を提供するものであり、基板
の外周に配線検査用電極を設けることにより、従来の検
査用プローブを用いても精度良く配線検査を行えるよう
にしたものである。
SUMMARY OF THE INVENTION The present invention provides a high-density wiring board and a method for manufacturing the same that solves the above-mentioned problems. By providing a wiring inspection electrode on the outer periphery of the board, a conventional inspection probe is used. Even so, the wiring inspection can be performed with high accuracy.

【0007】[0007]

【発明の構成】本発明によれば、以下の高密度配線多層
基板とその製造方法が提供される。 (1) 配線基板製品部の外側に検査用電極領域が設け
られ、基板に形成した高密度配線の端子が該検査用電極
領域に導かれ、該領域で配線間隔を広げた検査用電極が
形成されていることを特徴とする高密度配線基板。 (2) 配線基板の上記検査用電極領域の外側にメッキ
用電極領域が形成され、上記検査用電極を形成する配線
端子が該メッキ用電極領域に導かれてメッキ用電極が形
成されていることを特徴とする上記(1) の高密度配線基
板。 (3) 配線基板製品部の外側に検査用電極領域を設
け、基板に形成した高密度配線の端子を該検査用電極領
域に導くと共に該端子を検査用電極領域の外側に形成し
たメッキ用電極領域に導いてメッキ用電極を形成し、該
メッキ用電極を用いて配線をメッキ処理した後にメッキ
用電極領域を切除し、その後、検査用電極を用いて配線
検査を行い、検査後、検査用電極領域を切除して製品基
板とする高密度配線基板の製造方法。
According to the present invention, the following high-density wiring multilayer substrate and method for manufacturing the same are provided. (1) An inspection electrode area is provided outside the wiring board product part, terminals of high-density wiring formed on the substrate are guided to the inspection electrode area, and an inspection electrode having a wide wiring interval is formed in the area. High-density wiring board characterized by being (2) A plating electrode region is formed outside the inspection electrode region of the wiring board, and a wiring terminal forming the inspection electrode is guided to the plating electrode region to form a plating electrode. The high-density wiring board according to (1) above, which is characterized by (3) An electrode area for inspection is provided outside the product part of the wiring board, the terminals of the high-density wiring formed on the substrate are guided to the electrode area for inspection, and the electrode for plating is formed outside the electrode area for inspection. After forming an electrode for plating by guiding to the area, plating the wiring using the electrode for plating, cutting off the electrode area for plating, and then performing wiring inspection using the electrode for inspection, and after inspection, for inspection A method for manufacturing a high-density wiring board in which an electrode region is cut off to form a product board.

【0008】[0008]

【発明の具体的な態様】以下、図面を参照して本発明を
詳細に説明する。なお図示する実施例は本発明の例示で
あり、発明の範囲を限定するものではない。図1及び図
2は本発明に係る多層配線基板を模式的に示す概略平面
図であり、図1は表面層、図2は表面層の下側の配線層
を示す。また図3はその模式断面図であり、2層構造の
例を示す。なお基板構造は2層に限らない。図示する基
板10は、下層11と上層13の間に内部配線12が形
成されており、該内部配線12は層間を貫くビア14な
どによって層間が導通され、上層13の表面に形成した
電極15、16、17に接続している。また該上層13
の表面には絶縁性樹脂などからなる保護層18が設けら
れている。上記基板10には、図1に示すように、中央
に製品部Cが形成され、該製品部Cの周囲に検査用電極
領域Bが形成されており、該領域Bの外側にメッキ用電
極領域Aが設けられている。図2に示すように、製品部
Cの内部配線12は間隔が約0.1 〜0.15mm程度の高密度
配線であり、その表面には搭載した半導体チップ(図示
せず)の端子に接続するための電極17が形成されてお
り、該電極17はビア14によって内部配線12に接続
されている。該内部配線12の外側端部12aは次第に
配線間隔を広げて周囲の検査用電極領域Bに延び、該領
域Bでは0.5〜1.0mm のピッチで配列されている。図示
する例では、製品部Cのチップ搭載領域を囲んで配線1
2が形成され、該配線12から周辺に向かって放射状に
配線端部12aが延び、領域Bにおいて一定間隔に並列
されている。領域Bの表面には多数の検査用電極15が
現用の配線検査プローブを使用できる間隔を保って形成
されており、該電極15はビア14を通じて内部配線1
2に接続している。なお、検査用電極15は互いに接触
しないように、2列に形成し、交互に内側の列と外側の
列に設けると良い。
DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail below with reference to the drawings. The illustrated embodiments are examples of the present invention and do not limit the scope of the invention. 1 and 2 are schematic plan views schematically showing a multilayer wiring board according to the present invention. FIG. 1 shows a surface layer and FIG. 2 shows a wiring layer below the surface layer. Further, FIG. 3 is a schematic sectional view thereof, showing an example of a two-layer structure. The substrate structure is not limited to two layers. In the illustrated substrate 10, an internal wiring 12 is formed between a lower layer 11 and an upper layer 13. The internal wiring 12 is electrically connected between layers by a via 14 penetrating the layers, and an electrode 15 formed on the surface of the upper layer 13, It is connected to 16 and 17. Also, the upper layer 13
A protective layer 18 made of an insulating resin or the like is provided on the surface of the. As shown in FIG. 1, the substrate 10 has a product portion C formed in the center thereof, an inspection electrode region B formed around the product portion C, and a plating electrode region outside the region B. A is provided. As shown in FIG. 2, the internal wiring 12 of the product portion C is a high-density wiring with a space of about 0.1 to 0.15 mm, and is connected to the terminals of a semiconductor chip (not shown) mounted on the surface thereof. An electrode 17 is formed, and the electrode 17 is connected to the internal wiring 12 by a via 14. The outer ends 12a of the internal wirings 12 gradually extend in the wiring space and extend to the surrounding inspection electrode region B, and in the region B, they are arranged at a pitch of 0.5 to 1.0 mm. In the illustrated example, the wiring 1 is provided so as to surround the chip mounting area of the product section C.
2 are formed, the wiring end portions 12a extend radially from the wiring 12 toward the periphery, and are arranged in the region B at regular intervals. A large number of inspection electrodes 15 are formed on the surface of the region B at intervals so that a current wiring inspection probe can be used.
Connected to 2. The inspection electrodes 15 may be formed in two rows so that they do not contact each other, and they may be alternately provided in the inner row and the outer row.

【0009】基板上の配線は、主にAg、Ag−Pdな
どの導体によって形成されるが、半導体チップを搭載す
る際の耐ハンダ性を高め、また通電時のAgのマイグレ
ーションを防止するために、一般的に配線上にNiメッ
キが施される。また必要に応じてさらにAuメッキが施
される。このメッキ処理のためにメッキ用電極が形成さ
れる。図示する例では、検査用電極領域Bの外側にメッ
キ用電極を設ける領域Aが形成されており、該領域Aに
メッキ用電極16が形成されている。なお、上記検査用
電極15は個々の配線12およびビア14の導通を検査
するために配線ごとに電極15が必要となるが、メッキ
処理の際には配線全体に一時に通電されれば良いので、
配線ごとに独立した電極を設ける必要はない。そこで本
例では、電流密度が均一となるように複数の配線端部1
2aを回線13によって結合し、その端子が領域Aにお
いて複数のメッキ用電極16を形成している。
The wiring on the substrate is mainly formed of a conductor such as Ag or Ag-Pd. However, in order to improve solder resistance when mounting a semiconductor chip and prevent Ag migration during energization. Generally, Ni plating is applied on the wiring. Further, Au plating is further applied if necessary. Electrodes for plating are formed for this plating process. In the illustrated example, a region A where the plating electrode is provided is formed outside the inspection electrode region B, and the plating electrode 16 is formed in the region A. The inspection electrode 15 needs an electrode 15 for each wiring in order to inspect the continuity of the individual wiring 12 and the via 14. However, it is sufficient to energize the entire wiring at one time during the plating process. ,
It is not necessary to provide an independent electrode for each wiring. Therefore, in this example, the plurality of wiring end portions 1 are arranged so that the current density becomes uniform.
2a are connected by a line 13 whose terminals form a plurality of plating electrodes 16 in the area A.

【0010】メッキ用電極16を利用して配線12にN
i電気メッキを施した後、該基板表面に絶縁性樹脂から
なる表面層18を被せて配線層を保護し、フォトエッチ
ング後、必要に応じてAuメッキもしくはハンダメッキ
などを施す。なおメッキの良否は顕微鏡下の実態観察に
よって判定することができる。
N is formed on the wiring 12 by utilizing the plating electrode 16.
i After electroplating, the surface of the substrate is covered with a surface layer 18 made of an insulating resin to protect the wiring layer, and after photoetching, Au plating or solder plating is applied if necessary. The quality of the plating can be determined by observing the actual condition under a microscope.

【0011】表面の保護層を設けた後、メッキ用電極領
域Aを切除してメッキ用電極16および配線端部12a
を結ぶ回線19を取り除く。これにより各配線12は独
立した状態となる。この状態で、各配線の端部に形成さ
れている検査用電極15を利用して各配線の断線や短絡
を検査する。具体的には、例えば、配線検査用プローブ
を電極15に接触し、個々の配線の通電状態を検査す
る。配線検査の後に検査用電極領域Bを切除して製品基
板とする。
After providing the protective layer on the surface, the plating electrode region A is cut off to plate the plating electrode 16 and the wiring end 12a.
Remove the line 19 connecting As a result, each wiring 12 becomes independent. In this state, the inspection electrode 15 formed at the end of each wiring is used to inspect each wiring for disconnection or short circuit. Specifically, for example, a wiring inspection probe is brought into contact with the electrode 15 to inspect the energization state of each wiring. After the wiring inspection, the inspection electrode region B is cut off to obtain a product substrate.

【0012】本例では、半導体の搭載部分を中央に設け
た例を示したが、複数の半導体チップを搭載する基板に
おいては、半導体の搭載部分を中央に限らず適宜の位置
に設け、各々の半導体チップに対応した内部配線12を
多層構造の各層に形成し、各層の内部配線を検査用する
検査用電極を基板表面の領域Bに形成しても良い。な
お、メッキ用電極16を設けずに検査用電極15を利用
し、メッキ時に複数の検査用電極15を結ぶ補助導体を
該電極15に当てがって通電しても良い。
In this example, the semiconductor mounting portion is provided at the center. However, in a substrate on which a plurality of semiconductor chips are mounted, the semiconductor mounting portion is not limited to the center but is provided at an appropriate position. The internal wiring 12 corresponding to the semiconductor chip may be formed in each layer of the multilayer structure, and the inspection electrode for inspecting the internal wiring of each layer may be formed in the region B on the substrate surface. Alternatively, the inspection electrode 15 may be used without providing the plating electrode 16, and an auxiliary conductor that connects a plurality of inspection electrodes 15 may be applied to the electrode 15 during plating to conduct electricity.

【0013】上記配線基板10は、低温焼成基板材料な
どの常用される基板材料を用いて製造することができ
る。また上記配線検査用電極やメッキ用電極の部分を除
き通常の製造工程に従って製造できる。
The wiring board 10 can be manufactured using a commonly used substrate material such as a low temperature firing substrate material. Further, it can be manufactured according to a normal manufacturing process except for the wiring inspection electrode and the plating electrode.

【0014】[0014]

【発明の効果】本発明の配線基板は、配線の間隔が0.1
〜0.15mm程度のファインピッチでも、検査用電極を用
い、現用の接触型検査機によって配線を検査できるの
で、従来の多層基板製造技術によって高密度配線を有す
る多層配線基板を容易に製造することができる。また、
本発明の基板に形成される検査用電極は使用後に切除す
るので、製品上の問題を生じない。
The wiring board of the present invention has a wiring interval of 0.1.
Even with a fine pitch of ~ 0.15mm, the wiring can be inspected by the current contact type inspecting machine using the inspection electrodes, so it is possible to easily manufacture the multi-layer wiring board with high-density wiring by the conventional multi-layer board manufacturing technology. it can. Also,
Since the inspection electrode formed on the substrate of the present invention is cut off after use, there is no problem with the product.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明に係る多層配線基板の概略を示す模式
平面図。
FIG. 1 is a schematic plan view showing an outline of a multilayer wiring board according to the present invention.

【図2】 上記基板の配線層を示す模式平面図。FIG. 2 is a schematic plan view showing a wiring layer of the substrate.

【図3】 上記基板の多層構造を模式的に示す断面図。FIG. 3 is a sectional view schematically showing a multilayer structure of the substrate.

【符号の説明】 10−多層基板、 11−下層、 12−内部配線、
13−上層、14−ビア、 15−検査用電極、 16
−メッキ用電極、17−製品部電極、 18−表面層 A−メッキ用電極領域、 B−検査用電極領域、 C
−製品部
[Explanation of reference numerals] 10-multilayer substrate, 11-lower layer, 12-internal wiring,
13-upper layer, 14-via, 15-inspection electrode, 16
-Plating electrode, 17-Product part electrode, 18-Surface layer A-Plating electrode region, B-Inspection electrode region, C
-Product Department

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 配線基板製品部の外側に検査用電極領域
が設けられ、基板に形成した高密度配線の端子が該検査
用電極領域に導かれ、該領域で配線間隔を広げた検査用
電極が形成されていることを特徴とする高密度配線基
板。
1. An inspection electrode region, in which an inspection electrode region is provided outside a wiring board product part, terminals of high-density wiring formed on a substrate are guided to the inspection electrode region, and a wiring interval is widened in the region. A high-density wiring board characterized by being formed.
【請求項2】 配線基板の上記検査用電極領域の外側に
メッキ用電極領域が形成され、上記検査用電極を形成す
る配線端子が該メッキ用電極領域に導かれてメッキ用電
極が形成されていることを特徴とする請求項1の高密度
配線基板。
2. A plating electrode region is formed outside the inspection electrode region of the wiring board, and wiring terminals forming the inspection electrode are guided to the plating electrode region to form the plating electrode. The high-density wiring board according to claim 1, wherein:
【請求項3】 配線基板製品部の外側に検査用電極領域
を設け、基板に形成した高密度配線の端子を該検査用電
極領域に導くと共に該端子を検査用電極領域の外側に形
成したメッキ用電極領域に導いてメッキ用電極を形成
し、該メッキ用電極を用いて配線をメッキ処理した後に
メッキ用電極領域を切除し、その後、検査用電極を用い
て配線検査を行い、検査後、検査用電極領域を切除して
製品基板とする高密度配線基板の製造方法。
3. A plating method in which an inspection electrode region is provided outside the wiring board product portion, terminals of high-density wiring formed on the substrate are guided to the inspection electrode region, and the terminals are formed outside the inspection electrode region. Forming an electrode for plating by leading to the electrode area for plating, after cutting the wiring using the electrode for plating, the electrode area for plating is cut off, after that, the wiring is inspected using the electrode for inspection, and after the inspection, A method for manufacturing a high-density wiring board in which the inspection electrode area is cut off to form a product board.
JP15634093A 1993-06-03 1993-06-03 High-density wiring board and manufacturing method thereof Pending JPH06349976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15634093A JPH06349976A (en) 1993-06-03 1993-06-03 High-density wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15634093A JPH06349976A (en) 1993-06-03 1993-06-03 High-density wiring board and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH06349976A true JPH06349976A (en) 1994-12-22

Family

ID=15625635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15634093A Pending JPH06349976A (en) 1993-06-03 1993-06-03 High-density wiring board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH06349976A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317866A (en) * 2004-04-30 2005-11-10 Sony Corp Semiconductor device and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0290552A (en) * 1988-09-27 1990-03-30 Matsushita Electric Works Ltd Substrate for pga
JPH02133943A (en) * 1988-07-22 1990-05-23 Contraves Ag High integrated circuit and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02133943A (en) * 1988-07-22 1990-05-23 Contraves Ag High integrated circuit and manufacture thereof
JPH0290552A (en) * 1988-09-27 1990-03-30 Matsushita Electric Works Ltd Substrate for pga

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317866A (en) * 2004-04-30 2005-11-10 Sony Corp Semiconductor device and manufacturing method thereof

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