JPH06350413A - Mos voltage comparator - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a MOS voltage comparator which operates at high speed and has a small input offset voltage. [Structure] A Tr. Which has a gate as a differential input terminal and which is differentially connected to each other. M1 and M2, Tr. A first differential amplifier stage having M3 and M4, and two analog voltages that are differentially connected to each other and are compared with the gate are input and the drain is Tr. It is connected to the gates of M1 and M2 and Tr. Tr. Having a larger element size than M1 and M2. M5 and M6 are diode-connected and T
r. T for load with larger element size than M3 and M4
r. It is characterized by comprising a second differential amplifier stage having M7 and M8, and an output stage outputting high or low depending on the magnitude of two analog voltages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of characteristics of a MOS voltage comparator.

[0002]

2. Description of the Related Art A voltage comparator compares the magnitudes of two analog input voltages and outputs the determination result as high or low.

FIG. 3 is a circuit diagram of a conventional MOS voltage comparator formed on the same semiconductor substrate as an integrated circuit.
All the transistors used are enhancement type MOS transistors. In FIG. 3, M
The OS voltage comparator includes a first differential amplifier stage 10 and an output stage 30.

P-channel type transistors M10 and M1
The power supply voltage V is applied to the sources of 1 and M12. _DDIs supplied
Transistor M12 whose drain and drain are connected to each other
Is the constant current I_biasIs being supplied.

The transistors M10 and M11 are connected to the transistor M12 by a current mirror connection,
The transistors M10 and M11 include the transistor M1.
A constant current that is proportional to the constant current I _bias corresponding to the ratio of the gate length and the gate width of 0, M11, and M12 is supplied.

The P-channel type transistor M
1, M2 are differentially connected, the sources connected to each other are connected to the drain of the transistor M11, and two voltages V ⁻ and V ⁺ to be compared are input to the gates, respectively.

The drains of the transistors M1 and M2 are connected to the reference voltage V _SS through the transistors M3 and M4, which are N-channel type active loads and are connected to each other as a current mirror. Thus, the transistors M1 to M4 and M11 form the first differential amplification stage 10.

The output stage 30 is composed of a transistor M9 and a transistor M10 whose drains are connected to each other, an output terminal V _OUT is connected to a common connection point of the drains thereof, and a gate of the transistor M9 is a transistor M9.
2 and the drain of the transistor M4 are connected together, and the source is connected to the reference voltage V _SS .

Next, the operation of the MOS voltage comparator shown in FIG. 3 will be described. V ^-> In the event of a V ^+, transistor M
The gate-source voltage of 2 becomes larger than that of the transistor M1, and the drain current of the transistor M2 increases. Therefore, the source-drain voltage of the transistor M4, that is, the gate-source voltage of the transistor M9 increases, and the drain current of the transistor M9 increases, so that the output voltage becomes close to the reference voltage V _SS (low).

[0010] ^V - <In the event of a V ^+, transistor M
The gate-source voltage of transistor 2 becomes smaller than that of transistor M1, and the drain current of transistor M2 decreases. Therefore, the source-drain voltage of the transistor M4, that is, the gate-source voltage of the transistor M9 decreases, and the drain current of the transistor M9 decreases, so that the output voltage becomes close to the power supply voltage V _DD (high).

Then, the transistors M1 to M4 and M9 to
And as shown the element size of M12 in FIG. 4, for example, I _bias
= 25 μA, the input offset voltage of the MOS voltage comparator is about 3 mV, and the propagation delay time is about 0.4 μse.
It was c.

[0012]

SUMMARY OF THE INVENTION Such conventional MO
In the S voltage comparator, the input offset voltage is low,
It is desirable that the propagation delay time is short. Then, the input offset voltage is improved by improving the accuracy of finishing the device dimensions of the transistors M1 to M4, that is, by increasing the gate length and the gate width of these transistors.
However, since the propagation delay time is improved by reducing the gate length and the gate width of the transistors M1 to M4, there is a trade-off relationship between the input offset voltage and the propagation delay time. For example, when the device dimensions of the transistors M1 to M4 shown in FIG. 4 are quadrupled in the gate length and the gate width, respectively, the input offset voltage is about 2 m.
Although it is improved to V, the propagation delay time increases to about 2 μsec. Thus, there is a problem that it is difficult to realize a MOS voltage comparator that operates at high speed and has a small input offset voltage.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to operate at a high speed and to provide a small input offset voltage.
It is to provide an OS voltage comparator.

[0014]

In order to achieve the above object, the present invention relates to MOS transistors M1 and M2 which are differentially connected to each other and whose sources are supplied with a constant current and whose gates are differential input terminals. A first differential amplifier stage having load MOS transistors M3 and M4, which are connected in a current mirror configuration, each source is connected to a common potential, and drains are connected to the drains of the MOS transistors M1 and M2, respectively. A MOS transistor having a larger element size than the MOS transistors M1 and M2, connected to a mold, a constant current is supplied to the source, two analog voltages to be compared with the gate are input, and a drain is connected to the gates of the MOS transistors M1 and M2. M5, M6,
The diode-connected drains are connected to the drains of the MOS transistors M5 and M6, respectively, and are composed of load MOS transistors M7 and M8 each having a larger element size than the MOS transistors M3 and M4. A transistor M9 having two differential amplification stages, a drain to which a constant current is supplied, an output terminal connected, a gate connected to the drain common point of the transistors M2 and M4, and a source connected to a common potential.
And an output stage that outputs high or low in accordance with the magnitude of the two analog voltages, and is a MOS voltage comparator.

[0015]

According to the present invention as described above, the second differential amplifier stage reduces the input offset voltage generated in the first differential amplifier stage in terms of input, and makes the input to the first differential amplifier stage steep. The propagation delay time of the entire MOS voltage comparator is not increased.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. In the following drawings, the same parts as those in FIG.

FIG. 1 is a circuit diagram of a MOS voltage comparator showing an embodiment of the present invention. In FIG. 1, the MOS voltage comparator is configured by providing a second differential amplification stage 20 including transistors M5 to M8 and M13 in front of the first differential amplification stage 10 of the MOS voltage comparator shown in FIG. ing.

The power supply voltage V _DD is supplied to the source of the P-channel type transistor M13 and is connected to the transistor M12 in a current mirror. Therefore, a constant current proportional to the constant current I _bias corresponding to the ratio of the gate length and the gate width of the transistor M13 is supplied to the transistor M13.

The P-channel type transistor M
Reference numerals 5 and M6 are differentially connected, the sources connected to each other are connected to the drain of the transistor M13, and the gates thereof have two analog voltages V ⁻ and V ⁺ to be compared.
Is entered.

The P-channel type transistor M
The gates and drains of the transistors M7 and M8 are diode-connected and are connected to the reference voltage V _SS , and the drains thereof are connected to the drains of the transistors M5 and M6, respectively, and function as loads to the transistors M5 and M6.

The drain of the transistor M5 is connected to the gate of the transistor M2, and the transistor M6
Is connected to the gate of the transistor M1, and the output of the second differential amplification stage 20 serves as the differential input of the first differential amplification stage 10.

Next, the operation of the MOS voltage comparator shown in FIG. 1 will be described. V ^-> In the event of a V ^+, transistor M
Since the gate-source voltage of transistor 6 becomes higher than that of transistor M5 and the drain current of transistor M6 increases, the gate input of transistor M1 goes high and the gate input of transistor M2 goes low. The following operation is the same as that of the conventional example, and the output voltage is near the reference voltage V _SS (low).

[0023] ^V - <In the event of a V ^+, transistor M
Since the gate-source voltage of transistor 6 becomes lower than that of transistor M5 and the drain current of transistor M6 decreases, the gate input of transistor M1 becomes low and the gate input of transistor M2 becomes high. The subsequent operation is the same as that of the conventional example, and the output voltage is near the power supply voltage V _DD (high).

Then, the device dimensions of the transistors M1 to M4 are made equal to those of, for example, the MOS voltage comparator shown in FIG.
When the device dimensions of the transistors M5 to M8 are larger than those of the transistors M1 to M4 as shown in FIG. 2, for example, the input offset voltage in the second differential amplification stage 20 is smaller than that in the first differential amplification stage 10. Become.

In this case, the voltage gain A _V of the second differential amplifier stage 20 is calculated by the following equation (1), and A _V = 5. _{AV =} {(W / L) ₅ / (W / L) ₇ } ^1/2 (1) (W / L) ₅ : Gate width / gate length of transistor M5 (W / L) ₇ : Gate of transistor M7 Width / gate length

In such a MOS voltage comparator, I _bias =
When it is set to 25 μA, a propagation delay of about 0.1 μsec occurs in the second differential amplification stage 20 provided in front of the first differential amplification stage 10, but the second differential amplification stage 20 has a five-fold voltage gain. Since the input to the first differential amplifier 10 becomes steeper due to the provision of the value .about.
The propagation delay of μsec is absorbed, and the propagation delay time of the entire MOS voltage comparator becomes about 0.4 μsec, which is the same as the conventional one.

Further, 2 input to the second differential amplification stage 20.
The two analog voltages V ⁻ and V ⁺ are 5 in the second differential amplifier 20.
Since it is amplified twice and input to the first differential amplification stage 10,
If the offset voltage generated in the first differential amplification stage 10 is converted with reference to the input voltage to the second differential amplification stage 20, the magnitude thereof will be considered to be ⅕ of that of the conventional one.
Input offset voltage of the entire voltage comparator is about 2m
V is smaller than the conventional one.

As described above, by providing the second differential amplifier stage 20 having a small input offset voltage in front of the first differential amplifier stage 10, the propagation delay time of the entire MOS voltage comparator is not increased, and The reduction of the offset voltage can be realized together.

In such a MOS voltage comparator, the diode-connected transistors M7 and M8 can also be realized by Nch transistors.

In the present invention, the MOS voltage comparator using the CMOS transistor has been described.
The MOS voltage comparator according to the present invention can be realized by using a MOS transistor or a PMOS transistor.

[0031]

As described above, according to the present invention, a MOS transistor having a larger element size than the MOS transistor forming the first differential amplification stage is provided before the first differential amplification stage forming the MOS voltage comparator. Since the second differential amplifier stage having the desired voltage gain is provided, it is possible to provide a MOS voltage comparator that operates at high speed and has a small input offset voltage as a whole.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a MOS voltage comparator showing an embodiment of the present invention.

FIG. 2 is a diagram showing the element dimensions of a transistor forming the MOS voltage comparator shown in FIG.

FIG. 3 is a circuit diagram of a conventional MOS voltage comparator.

FIG. 4 is a diagram showing the element size of a transistor forming the MOS voltage comparator shown in FIG.

[Explanation of symbols]

10 first differential amplification stage 20 second differential amplification stage 30 output stage M1 to M13 MOS transistor Vss reference voltage V _DD power supply voltage I _bias constant current

Claims (1)

[Claims] 1. MOS transistors M1 and M2 which are differentially connected to each other and whose sources are supplied with a constant current and whose gates are differential input terminals, are connected to each other in a current mirror, and their respective sources are connected to a common potential and their drains are said. A first differential amplifier stage having load MOS transistors M3 and M4 respectively connected to the drains of the MOS transistors M1 and M2, and differentially connected to each other, a constant current is supplied to the source, and the gate is compared. Two analog voltages are input, the drains are connected to the gates of the MOS transistors M1 and M2, and the MOS transistors M5 and M6 are larger in element size than the MOS transistors M1 and M2. The diode-connected drains are the MOS transistors M5 and M5, respectively.
A load MOS which is connected to the drain of M6 and has a larger element size than the MOS transistors M3 and M4.
A second differential amplifier stage including transistors M7 and M8, having a desired voltage gain, a constant current is supplied to the drain, an output terminal is connected, and a gate is connected to a common point of the drains of the transistors M2 and M4. A MOS voltage comparator having a transistor M9 whose source is connected to a common potential, and which outputs a high or a low in accordance with the magnitude of the two analog voltages.