JPH063680B2 - Differential amplification latch circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplification latch circuit, and more particularly to a differential amplification latch circuit used in a semiconductor memory device manufactured of a compound semiconductor.

[Conventional technology]

Conventionally, this type of differential amplification latch circuit is configured by coupling a differential circuit 50 and a level shift circuit 60 as shown in FIG. The differential circuit 50 includes resistors R201, R202, R20.
3 and a driving field effect transistor (hereinafter abbreviated as driving FET) Q201 and Q202. The resistor is, for example, a conductor layer formed by adding impurities to the semiconductor substrate. Drive F
The drain electrodes of ETQ201 and Q202 are resistors R20, respectively.
1, R202 is connected to the power supply V _DD , the gate electrodes are connected to the complementary input signal terminals IN and ▲ ▼, respectively, and the source electrodes are commonly connected to each other to form a resistor R20.
It is connected to the ground terminal GND via 3.

The level shift circuit 60 includes a first level shift circuit and a second level shift circuit.
The first level shift circuit includes a drive FET Q203, a level shift diode D201, a constant current source field effect transistor (hereinafter abbreviated as constant current source FET) Q204, and a second level shift circuit. Similarly, the level shift circuit is also composed of a drive FET Q205, a level shift diode D202 and a constant current source Q206. Drive
In the FETQ203, the drain electrode is connected to the power supply V _DD , the gate electrode is connected to the differential circuit output terminal 201, the source electrode is connected to the anode electrode of the level shift diode D201, and the constant current source FETQ204 has the drain electrode connected. Connected to the cathode electrode of a level shift diode D201 which is an output terminal OUT having the same phase as the input signal IN of the dynamic amplification circuit,
The gate electrode and the source electrode are connected to the ground terminal GND. In the drive FET Q205, the drain electrode is connected to the power supply V _DD , the gate electrode is connected to the differential circuit output terminal 202,
The source electrode is connected to the anode electrode of the level shift diode D202, and the drain electrode of the constant current source FET Q206 is connected to the cathode electrode of the level shift diode D202, which is the output terminal OUT of the opposite phase to the input signal IN of the differential amplifier circuit. , The gate electrode and the source electrode are connected to the ground terminal GND. These first and second level shift circuits match the output level of the differential amplifier circuit and the logical threshold level of the circuit provided in the next stage.

Next, the operation of the differential amplifier circuit of FIG. 5 will be described with reference to the operation waveform diagram of FIG. Input signal IN level is Hi
When gh changes to Low, the level of the differential circuit output terminal 201 becomes Hi
From gh to Low, the level of the output terminal OUT in phase with the input signal IN of the differential amplifier circuit changes from High to Low.
At the same time, the level of the differential circuit output terminal 202 changes from Low to Hig.
The level of the output terminal OUT having a phase opposite to that of the input signal IN of the differential amplifier circuit changes from Low to High and the inverter amplifying operation is performed.

Conventional static random access memory (below
As shown in FIG. 7, the SRAM (abbreviated as SRAM) uses a differential amplifier circuit (FIG. 5), and one memory cell is selected by the address input signals A _X and A _Y , and the differential amplifier circuit is used for reading. It is configured to output data through the circuit.

[Problems to be solved by the invention]

When the above-described conventional differential amplifier circuit is used in the data OUT detection section of a compound semiconductor memory device (hereinafter referred to as compound semiconductor memory) that operates at high speed, the address access time (hereinafter referred to as TAA) of the compound semiconductor memory is extremely low. Since it is short, there is a drawback in that it is difficult to match the timing of the data latch circuit composed of other external elements.

[Means for solving problems]

The differential amplification latch circuit of the present invention comprises (a) first and second resistors connected to a first power supply, drain electrodes respectively connected to the first and second resistors, and a first input signal. First and second field effect transistors each having a gate electrode connected to a terminal and a second input signal terminal complementary to the first input signal, and a source electrode commonly connected to each other; Drain electrodes respectively connected to the two resistors, an output terminal in phase with the first input signal and an output signal terminal in phase with the first input signal, and a gate electrode respectively connected to the output signal terminals in reverse phase to the first input signal, and sources commonly connected to each other. Electrodes having third and fourth field effect transistors, drain electrodes connected to the source electrodes of the first and second field effect transistors, a gate electrode connected to a control signal terminal, and a source electrode. And a drain electrode connected to the source electrodes of the third and fourth field effect transistors, a gate electrode connected to a control signal terminal complementary to the control signal, and the fifth field effect transistor having A sixth field effect transistor having a source electrode commonly connected to the source electrode of the field effect transistor, and further connected to the source electrodes of the fifth and sixth field effect transistors and connected to a second power supply Done third
And (b) output signals of the drain electrodes of the first and third field effect transistors and the drain electrodes of the second and fourth field effect transistors of the differential latch circuit, respectively. And a level shift circuit connected so as to feed back the output signal to the gate electrodes of the third and fourth field effect transistors of the differential latch circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. In FIG. 1, the differential latch circuit of the present invention is composed of a differential latch circuit 10 and a level shift circuit 20 for level shifting, and is used in a data detection section of a compound semiconductor memory. The differential latch circuit 10 includes first and second resistors R101 and R102 connected to a first power source V _DD , a train electrode connected to the resistors R101 and R102, and an output terminal 102, and a first input signal. A gate electrode connected to the terminal IN and a second input signal terminal complementary to the first input signal ▲
▼ First and second field effect transistors (hereinafter abbreviated as FETs) Q101 and Q102 having gate electrodes respectively connected to and and source electrodes commonly connected to each other, and first and second resistors R101 and R102. Via a drain electrode serving as an output terminal 101, an output signal OUT having the same phase as the first input signal, an opposite phase to the first input signal, and an output terminal ▲ ▼. To the control signal terminal CLK, the third and fourth FETs Q103 and Q104 having a common gate electrode and a source electrode commonly connected to each other, and the drain electrodes connected to the source electrodes of the first and second FETs Q101 and Q102. A fifth FET Q103 having a source electrode connected to the second power supply GNO via a connected gate electrode and a third resistor R103, and connected to the source electrodes of the third and fourth FETs Q103, Q104. Drain electrode, a gate electrode connected to a control signal terminal () complementary to the control signal, and a source electrode of the fifth FET Q105 are commonly connected to each other, and further connected to a second power source through a third resistor R103. A sixth electrode having a source electrode
It has FETQ106.

The first and second FETs Q101 and Q102 are driving FETs,
The third and fourth FETs Q103 and Q104 are latch driving FETs
And the fifth and sixth FETs Q105 and Q106 are selection FETs.
Is. The resistors R101, R102, R102 are, for example, conductor layers formed by adding impurities to the semiconductor substrate.

The level shift circuit 20 includes a drain electrode connected to the first power source V _DD , a second field effect transistor Q10 and a fourth field effect transistor Q10.
Second field effect transistor Q having gate electrodes connected to the drain electrodes of Q104 and source electrodes connected to the anode electrodes of the first diodes D101 and D102
107, an eighth field effect transistor Q108 having a drain electrode connected to the cathode electrode of the first diode, which is the output signal terminal OUT, and a gate electrode connected to the second power supply GND, and the first power supply V Drain electrode connected to _DD , first and third field effect transistor Q10
Ninth field effect transistor Q109 having gate electrodes connected to the drain electrodes of Q1 and Q103 and a source electrode connected to the anode electrode of the second diode D102.
And a second output signal OUT having a phase opposite to that of the first input signal
The diode D102 has a drain electrode connected to the cathode electrode thereof, a gate electrode connected to the second power supply, and a tenth field effect transistor Q110 having a source electrode.

Next, the operation of this embodiment will be described with reference to the operation waveform chart shown in FIG. The level of the control signal terminal CLK is Hig
h, the level of the signal terminal ▲ ▼ opposite to the control signal is Low
At this time, when the FET Q105 is in the ON state, the FET Q106 is in the OFF state, and the level of the input signal IN changes from High to Low, the level of the output terminal 101 of the differential latch circuit 10 changes from High to Low, and the differential amplifier latch circuit The level of the output terminal OUT having the same phase as the input signal IN changes from High to Low, and at the same time, the level of the output terminal 102 of the differential latch circuit 10 changes from Low to High.
Then, the level of the output terminal ▲ ▼ having a phase opposite to that of the input signal IN of the differential amplification latch circuit changes from Low to High, and the normal inverter amplification operation is performed. Next, control signal terminal
CLK signal level is Low, signal terminal in opposite phase to control signal ▲
When the level of ▼ becomes High, FETQ105 is OFF, FE
The TQ106 is turned on, and the low level of the output terminal OUT in phase with the input signal IN of the differential amplifier latch circuit causes the FETQ103 to become OF.
Further, the high level of the output terminal (1) having a phase opposite to the input signal IN of the differential amplification latch circuit turns on the FET Q104. That is, the data at this point is held by feeding back the output signal to the input. After that, unless the levels of the complementary control signal terminals CLK and ▲ ▼ change, the output terminal OU of the differential amplification latch circuit
The levels of T and ▲ ▼ will not change, and the data will be latched.

FIG. 3 shows a configuration using the differential amplifier latch circuit according to the first embodiment of the present invention. In FIG. 3, since the levels of the complementary control signal terminals CLK and ▲ ▼ are High and Low, respectively, the differential amplification latch circuit operates and the complementary control signal terminals CLK and ▲
The differential amplifier latch circuit holds the current data because the levels of ▼ are Low and High, respectively.

FIG. 4 shows a second embodiment of the present invention. In FIG. 4, the level shift circuit of the second embodiment is the same circuit as the conventional circuit of the first embodiment or FIG.
The Q701 and Q702, the latch drive FETs Q703 and Q704, and the selection FETs Q705 and Q706 are the same as those in the first embodiment.
In the second embodiment, the resistor R10 in the first embodiment is used.
When 1, R102, R103 are replaced with active loads Q711, Q712, Q713, the active loads Q711, Q712, Q713 are used in the non-saturated operation region and are equivalent to resistors. As described above, the operation of the second embodiment is the same as that of the first embodiment, but since it can be manufactured in the same process as that of the other circuit component elements, the yield is reduced due to manufacturing variations. There is an advantage that can be suppressed.

〔The invention's effect〕

As described above, according to the present invention, output data can be latched by feeding back the output of the differential amplification latch circuit to the input of the differential amplification latch circuit. Can also be used. Further, according to the present invention, when a system is constructed using a compound semiconductor memory, it is not necessary to configure a data latch circuit with other external elements, and further, the output data of the compound semiconductor memory is a complementary control signal.
Since it is synchronized with CLK and {circle around (▼)}, the apparent TAA can be reduced to about 1/2 of the TAA of the conventional compound semiconductor memory when reading the data of the previous read cycle.

[Brief description of drawings]

FIG. 1 is a diagram showing a differential amplification latch circuit according to a first embodiment of the present invention, and FIG. 2 shows operation waveforms of the differential amplification latch circuit according to the first and second embodiments of the present invention. FIG. 3 is a diagram showing the configuration of an SRAM using the differential amplifier latch circuit of this embodiment, and FIG. 4 is a circuit diagram showing the differential amplifier latch circuit of the second embodiment of the present invention. FIG. 5 is a circuit diagram showing a conventional differential amplifier circuit, FIG. 6 is a diagram showing operation waveforms of the conventional differential amplifier circuit, and FIG. 7 is a diagram showing an SRAM configuration using the conventional differential amplifier circuit. Is. 10 ... Differential latch circuit, 20 ... Level shift circuit,
IN, ▲ …… Complementary input signal terminal, OUT, ▲ ▼
... Complementary output signal terminals, 102, 101, 201, 202 ... Differential circuit output terminals, R101, R102, R103, R201, R20
2, R203 ... Resistance, Q101, Q102, Q103, Q104, Q10
7, Q109, Q201, Q202, Q203, Q205, Q701, Q70
2, Q703, Q704, Q707, Q709 ... Driving FET, Q10
5, Q106, Q705, Q706 ... Selection FET, D101, D1
02, D201, D202, D701, D702 ... Level shift diode, Q108, Q110, Q204, Q206, Q708, Q710 ...
... Constant current source FET, Q711, Q712, Q713 ... Active load, CLK, ▲ ▼ ... Complementary control signal, V _DD ... Power supply,
GND: ground terminal, A _x , A _Y: address input signal,
Dout …… Data out.

Claims (2)

[Claims] 1. (a) First and second resistors connected to a first power source, drain electrodes respectively connected to the first and second resistors, a first input signal terminal and the first resistor. The first and second field effect transistors each having a gate electrode connected to the second input signal terminal complementary to the first input signal and a source electrode commonly connected to each other, and the first and second resistors. A drain electrode connected to each of them, an output terminal of the same phase as the first input signal, a gate electrode connected to the output signal terminal of the opposite phase of the first input signal, and a source electrode commonly connected to each other A fifth field effect transistor having third and fourth field effect transistors, a drain electrode connected to the source electrodes of the first and second field effect transistors, a gate electrode connected to a control signal terminal, and a source electrode. Field effect transistor, drain electrodes connected to the source electrodes of the third and fourth field effect transistors, a gate electrode connected to a control signal terminal complementary to the control signal, and a source of the fifth field effect transistor A sixth field effect transistor having a source electrode commonly connected to the electrode, and a third field effect transistor further connected to the source electrodes of the fifth and sixth field effect transistors and connected to a second power supply. A differential latch circuit having a resistance; and (b) output signals of the drain electrodes of the first and third field effect transistors and the drain electrodes of the second and fourth field effect transistors of the differential latch circuit, respectively. So that the output signal is fed back to the gate electrodes of the third and fourth field effect transistors of the differential latch circuit. Differential amplifier latch circuit; and a level shift circuit connected to. 2. The differential amplifier latch circuit according to claim 1, wherein the first, second and third resistors are replaced by active loads such as field effect transistors.