JPH0637228A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0637228A
JPH0637228A JP4213288A JP21328892A JPH0637228A JP H0637228 A JPH0637228 A JP H0637228A JP 4213288 A JP4213288 A JP 4213288A JP 21328892 A JP21328892 A JP 21328892A JP H0637228 A JPH0637228 A JP H0637228A
Authority
JP
Japan
Prior art keywords
solder
lead
semiconductor device
tip
predetermined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4213288A
Other languages
Japanese (ja)
Inventor
Shoji Takishima
昭二 滝島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP4213288A priority Critical patent/JPH0637228A/en
Publication of JPH0637228A publication Critical patent/JPH0637228A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 (修正有) 【目的】 半導体装置のリード先端部のハンダ量の制御
を可能にして実装性を改善することである。 【構成】 樹脂部2内の半導体装置からのリード3の先
端部4が、基板1上の導体配線5にハンダ付けされる。
この場合、先端部4に予めIn系ハンダ4aとPb/S
n系ハンダ4bが設けてあり、低い温度から加熱して順
次ハンダ4a,4bがとけて接合される。
(57) [Summary] (Modified) [Purpose] To improve the mountability by making it possible to control the amount of solder at the tip of the lead of a semiconductor device. A tip 4 of a lead 3 from a semiconductor device in a resin portion 2 is soldered to a conductor wiring 5 on a substrate 1.
In this case, the In-based solder 4a and Pb / S are previously attached to the tip portion 4.
An n-based solder 4b is provided, and the solders 4a and 4b are sequentially melted and joined by heating from a low temperature.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は狭ピッチ化されたリード
を有する半導体パッケージに実装するのに好適なように
改善された半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved semiconductor device suitable for mounting on a semiconductor package having leads with a narrow pitch.

【0002】[0002]

【従来の技術】LSIパッケージの小型化、薄型化、多
ピン化に伴い、リードピッチも0.3mmピッチのQFP
(Quucl Flat Package)の出現をもたらしている。この
場合、最大の問題は、リード狭ピッチ化に伴うハンダブ
リッジ、リードの浮きなどによる不具合の改善方法にあ
る。現在検討されている方法としては、プリント基板上
へのクリームハンダの印刷法の改良(例えば、ハンダ粉
末の形状最適化、スクリーンマスクの高精度化)を行な
うことにより、ハンダブリッジの原因であるハンダ量の
バラツキをコントロールするものである。
2. Description of the Related Art A QFP with a lead pitch of 0.3 mm has been developed in line with the miniaturization, thinning, and increased pin count of LSI packages
(Quucl Flat Package) has emerged. In this case, the biggest problem lies in a method of improving a defect due to a solder bridge, lead floating, etc., which accompanies a narrow lead pitch. The method currently being studied is to improve the method of printing cream solder on a printed circuit board (for example, optimizing the shape of the solder powder and improving the accuracy of the screen mask), which causes the solder bridge that causes solder bridges. It controls the variation of the quantity.

【0003】[0003]

【発明が解決しようとする課題】しかしいずれの方法で
もコントロール上不十分といえる。また、もう一つの問
題としては、狭ピッチ化に伴ってリード幅も狭くなって
おり、リード曲がりの防止も必要となっていることであ
る。現状では、リード成形以降にもハンダメッキ工程な
どで曲がりを生じる場合も多い。
However, it can be said that either method is insufficient for control. Another problem is that the lead width is becoming narrower as the pitch becomes narrower, and it is necessary to prevent lead bending. At present, the lead is often bent after the lead plating in the solder plating process.

【0004】本発明の目的は、リードのハンダ部を改良
することにより、実装時の不具合を改善可能な半導体装
置を提供することにある。
An object of the present invention is to provide a semiconductor device capable of improving a problem at the time of mounting by improving a solder portion of a lead.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体装置は、所定融点温度の第1の種類
のハンダを所定の方法で塗布された先端領域と、前記先
端領域と隣接して設けられた、前記所定融点温度より高
い融点温度の第2の種類のハンダが前記所定の方法で塗
布された領域と、から成るリードを有していることを要
旨とする。この場合、前記所定の方法は、クラッド法で
あってもよく、また前記第1の種類のハンダが、In系
とBi系から成るグループから選択されるハンダであ
り、前記第2の種類のハンダがPb/Sn系のハンダで
あってもよい。更に、より具体的には、In系とBi系
から成るグループから選択されるハンダがクラッド法に
よって塗布されている先端領域と、Pb/Sn系のハン
ダがクラッド法によって塗布されている前記先端領域に
隣接している領域と、から成るリードを用いることもで
きる。
In order to achieve the above object, a semiconductor device of the present invention is provided with a tip region to which a first type solder having a predetermined melting point temperature is applied by a predetermined method, and adjacent to the tip region. The gist of the present invention is that it has a lead formed of a region formed by applying a second type solder having a melting point temperature higher than the predetermined melting point temperature by the predetermined method. In this case, the predetermined method may be a clad method, and the first type of solder is a solder selected from the group consisting of In-based and Bi-based, and the second type of solder. May be Pb / Sn based solder. Furthermore, more specifically, the tip region in which solder selected from the group consisting of In-based and Bi-based is applied by the cladding method, and the tip region in which Pb / Sn-based solder is applied by the cladding method. It is also possible to use a lead consisting of a region adjacent to.

【0006】[0006]

【作用】上述した本発明の半導体装置では、ハンダ量の
制御が可能になり、かつ組成の異なるハンダを複数変え
ているので、実装性に優れている。
In the semiconductor device of the present invention described above, the amount of solder can be controlled, and a plurality of solders having different compositions are changed, so that the mountability is excellent.

【0007】[0007]

【実施例】以下図面を参照して本発明の実施例を説明す
る。一般にPC基板上の配線部とLSIパッケージの接
合は、LSIパッケージのリードに付けられたハンダメ
ッキ層とPC基板上に印刷されたクリーム状ハンダもし
くはPC基板上の配線部にプリコートされたハンダ層を
もって接合が行なわれる。また、LSIパッケージの位
置ずれ防止のために、パッケージ本体とPC基板との間
に固定用の接着もハンダ付け前に行なわれる。
Embodiments of the present invention will be described below with reference to the drawings. In general, the wiring part on the PC board and the LSI package are joined by a solder plating layer attached to the leads of the LSI package and a cream solder printed on the PC board or a solder layer pre-coated on the wiring part on the PC board. Joining is performed. Further, in order to prevent the displacement of the LSI package, a fixing adhesive is also applied between the package body and the PC board before soldering.

【0008】本発明は、リードフレーム材料の素材加工
時において、リードの先端部にのみ、ハンダ帯板を、例
えばクラッド法によって、圧接しておくものである。厚
みの制御が精度よくできるためハンダ量が他の方法に比
べコントロール可能になる。また、必要な部分のみに限
定しておくことも可能である。素材のリードフレーム加
工は周知の方法で行なわれる。本発明はこうした利点を
利用し、異なった組成のハンダを特定の部分に付けてお
くことを特徴としている。
According to the present invention, a solder strip plate is press-contacted only to the tip portions of the leads by, for example, the clad method during the processing of the lead frame material. Since the thickness can be controlled with high accuracy, the amount of solder can be controlled compared to other methods. It is also possible to limit it to only necessary parts. The lead frame processing of the material is performed by a known method. The present invention takes advantage of these advantages and is characterized in that different compositions of solder are attached to specific portions.

【0009】図1は本発明の実施例の断面図である。同
図において、PC基板1に接続する樹脂部2に内蔵され
た半導体装置から導出されたリード3の先端部4は、図
2に示す如く2種類のハンダ組成で導体配線に接続され
る。まず、先端部4の平坦部はIn系もしくはBi系の
低融点ハンダ4aとし、曲がりの部分は、Pb/Sn系
4bとする。リフローソルダーリングの温度プロファイ
ルは、急速な加熱による不具合(ツームストーン現象な
ど)を避けるために低い温度から緩やかに昇温させてい
る。
FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, the tip 4 of the lead 3 derived from the semiconductor device built in the resin portion 2 connected to the PC board 1 is connected to the conductor wiring with two kinds of solder compositions as shown in FIG. First, the flat portion of the tip portion 4 is made of In-based or Bi-based low melting point solder 4a, and the bent portion is made of Pb / Sn system 4b. In the temperature profile of reflow soldering, the temperature is gradually raised from a low temperature to avoid problems due to rapid heating (such as the tombstone phenomenon).

【0010】そこで本発明では、まず、低い温度域でリ
ード3の平坦部4aにある低融点ハンダが融けて接合す
るハンダ量は、コントロールされ、かつクリームハンダ
のような余分なはみ出しもないので、位置ずれがおきな
い。次に緩やかに昇温し、高温域で曲がり部分4bのP
b/Sn系のハンダが融けて接合する。図3に示すよう
にリード3の接合部の曲がり部分のフィレット形状が強
度を左右するため、強度の強いPb/Sn系のハンダを
使っている。このように特徴の異なるハンダを製造条件
やリード構造に合わせて用いることにより、高性能な接
続が可能になっている。なお、本発明で使用するハンダ
及びその塗布方法は上記実施例で示したハンダ組成及び
クラッド法に限定するものではない。
Therefore, in the present invention, first, the amount of solder that the low melting point solder on the flat portion 4a of the lead 3 melts and joins in a low temperature range is controlled, and there is no extra protrusion such as cream solder. There is no misalignment. Next, the temperature is gently raised, and P of the bent portion 4b is increased in the high temperature range.
The b / Sn solder melts and joins. As shown in FIG. 3, since the fillet shape of the bent portion of the joint of the lead 3 influences the strength, a Pb / Sn-based solder having high strength is used. By using solders having different characteristics according to the manufacturing conditions and the lead structure, high-performance connection is possible. The solder used in the present invention and the coating method thereof are not limited to the solder composition and the clad method shown in the above embodiments.

【0011】[0011]

【発明の効果】以上説明したように本発明によれば、多
ピンで狭ピッチ化リードを有する半導体装置の基板への
実装性が格段に向上する。
As described above, according to the present invention, the mountability of a semiconductor device having a multi-pin and narrow-pitch lead on a substrate is remarkably improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す概略図である。FIG. 1 is a schematic view showing an embodiment of the present invention.

【図2】上記実施例におけるハンダクラッド法によるリ
ード先端の断面図である。
FIG. 2 is a cross-sectional view of a tip of a lead obtained by a solder clad method in the above embodiment.

【図3】上記実施例におけるリード接合後のリードの断
面図である。
FIG. 3 is a cross-sectional view of a lead after lead bonding in the above embodiment.

【符号の説明】[Explanation of symbols]

1 基板 2 樹脂部 3 リード 4 リード先端部 4a 低融点ハンダ 4b 高融点ハンダ 1 substrate 2 resin part 3 lead 4 lead tip part 4a low melting point solder 4b high melting point solder

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 所定融点温度の第1の種類のハンダを所
定の方法で塗布された先端領域と、 前記先端領域と隣接して設けられた、前記所定融点温度
より高い融点温度の第2の種類のハンダが前記所定の方
法で塗布された領域と、から成るリードを有しているこ
とを特徴とする半導体装置。
1. A tip region coated with a predetermined type of solder having a predetermined melting point temperature by a predetermined method, and a second region provided adjacent to the tip region and having a melting point temperature higher than the predetermined melting point temperature. A semiconductor device having a lead consisting of a region to which a type of solder is applied by the predetermined method.
【請求項2】 前記所定の方法は、クラッド法であるこ
とを特徴とする請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the predetermined method is a clad method.
【請求項3】 前記第1の種類のハンダが、In系とB
i系から成るグループから選択されるハンダであり、前
記第2の種類のハンダがPb/Sn系のハンダであるこ
とを特徴とする請求項1に記載の半導体装置。
3. The first type of solder is In-based and B-based.
The semiconductor device according to claim 1, wherein the solder is selected from the group consisting of i-based solder, and the second type of solder is Pb / Sn-based solder.
【請求項4】 In系とBi系から成るグループから選
択されるハンダがクラッド法によって塗布されている先
端領域と、 Pb/Sn系のハンダがクラッド法によって塗布されて
いる前記先端領域に隣接している領域と、から成るリー
ドを有していることを特徴とする半導体装置。
4. A tip region to which a solder selected from the group consisting of In-based and Bi-based is applied by a cladding method, and a tip region to which Pb / Sn-based solder is applied by a cladding method are adjacent to each other. A semiconductor device having a lead composed of a region having
JP4213288A 1992-07-17 1992-07-17 Semiconductor device Pending JPH0637228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4213288A JPH0637228A (en) 1992-07-17 1992-07-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4213288A JPH0637228A (en) 1992-07-17 1992-07-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0637228A true JPH0637228A (en) 1994-02-10

Family

ID=16636637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4213288A Pending JPH0637228A (en) 1992-07-17 1992-07-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0637228A (en)

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