JPH0637270A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a structure and a method for forming a capacitor of a memory cell of a DRAM, in which the capacitance of the capacitor is increased without increasing the cell area. It is an object of the present invention to obtain a structure for securing the capacitor and further to obtain a method for manufacturing a capacitor which does not increase the number of steps as compared with the conventional composite type. [Structure] A trench 8a formed adjacent to the FET,
The source / drain layer 8c formed of the impurity diffusion layer formed in the semiconductor substrate 1 including the trench 8a and the FE on both sides connected to the source / drain layer 8c via the insulating film 7
The conductive film 8b formed on T is used as the lower electrode 8, and the upper electrode 10 made of a conductive film is formed on the lower electrode 8 via the dielectric film 9.
The capacitor is configured so that

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure and a forming method of a capacitor of a DRAM memory cell.

DRAM is composed of one MOSFET and one capacitor, but the cell is miniaturized with the high integration of semiconductor devices, but the capacity of the capacitor should be maximized. Is desired.

Under the above circumstances, a semiconductor device capable of forming a large-capacity capacitor in a fine region,
And, the manufacturing method thereof is demanded.

[0004]

2. Description of the Related Art FIG. 5 is an explanatory view of a conventional example. In the figure, 51 is a Si substrate, 52 is a field SiO ₂ film, and 53 is a gate Si.
O ₂ film, 54 gate electrode, 55 source layer, 56 drain layer, 57 SiO ₂ film, 58 lower electrode layer made of CVD poly-Si film, 58a trench, 59 dielectric film, 60 upper part It is an electrode layer.

Conventionally, a capacitor cell of a semiconductor device is of a stacked type as shown in FIG. 5A in order to form a large-capacity capacitor in a region as fine as possible, or
A trench type as shown in FIG. 5B, and further, FIG.
As shown in Fig. 2, it was formed of a composite type of both, which is an improved type.

As shown in FIG. 5 (a) or (b)
In a conventional capacitor cell represented by a stacked type or a trench type as shown in (1), as the memory cells of DRAM are highly integrated at 16 MB and 64 MB, the area where the memory cells are formed becomes smaller and smaller. As a result, the area where the capacitor is formed becomes smaller accordingly, the area of the opposing electrode becomes smaller, the capacity of the capacitor becomes insufficient, and the reliability of the memory operation deteriorates.

Therefore, as shown in FIG. 5 (c), a capacitor cell in which both a stacked type and a trench type are combined has been proposed as a solution to the above problem.

[0008]

However, in this method, since the poly-Si film of the upper electrode layer is formed also in the trench, the inner wall area of the trench is reduced, and thus the capacitance of the capacitor is reduced. . On the other hand, increasing the diameter of the trench to secure the capacity causes an increase in cell area, which is contrary to high integration.

The present invention provides a structure for ensuring a large capacitance of a capacitor without causing an increase in cell area, and further a method for manufacturing a capacitor which does not increase the number of steps as compared with the conventional composite type. It is provided for the purpose.

[0010]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, 1 is a Si substrate, 2 is a field
SiO ₂ film, 3 is a gate SiO ₂ film, 4 is a gate electrode, 5 is a source layer, 6 is a drain layer, 7 is a SiO ₂ film, 8a is a trench, 8b
Is a lower electrode layer made of a CVD poly-Si film, 8c is a lower electrode layer made of an impurity diffusion layer, 9 is a dielectric film, and 10 is an upper electrode layer.

An object of the present invention is to include a trench 8a formed adjacent to an FET and a trench 8a, as shown in a schematic sectional view of FIG. 1 (a) and a perspective plan view of FIG. 1 (b). A source / drain layer 8c formed of an impurity diffusion layer formed in the semiconductor substrate 1, and a conductive film connected to the source / drain layer 8c and formed on the FETs on both sides via the insulating film 7.
8b and the lower electrode 8 is used as a lower electrode 8 and a capacitor is formed by forming an upper electrode 10 made of a conductive film on the lower electrode 8 via a dielectric film 9.

Further, by simultaneously patterning the poly-Si film for forming the lower electrode and forming the trench in the semiconductor substrate, the number of steps can be reduced. Furthermore, the gate electrode is made of poly-Si
By using the laminated structure of the film and the buffer SiO ₂ film, Si
The opening of the contact hole of the O ₂ film can be self-aligned by anisotropic etching.

[0013]

In the present invention, the lower electrode of the poly-Si film is diffused into the inner wall of the trench itself as a lower electrode without filling the lower electrode of the poly-Si film with the lower electrode of the poly-Si film on the upper side of the substrate. Contact us again and source
Since the drain layer is also connected, the area of the dielectric film can be increased and the capacitance can be increased even with the same trench width and depth.

[0014]

2 to 5 are schematic sectional views in order of steps or plan explanatory views of an embodiment of the present invention. In the figure, the numbers at the end conform to the numbers in FIG. 1, respectively.

A first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2A, a field SiO ₂ film 12 having a thickness of 5,000 Å is formed on the semiconductor substrate 11 by the LOCOS method to define the FET formation region.

A gate SiO ₂ film 13 is formed by a thermal oxidation method, and then a poly Si film is deposited by a CVD method, using a mask,
The gate electrode 14 made of a poly-Si film is formed by etching. Then, the source / drain layers 5 and 6 are formed by ion implantation by self-alignment using the gate electrode 14 as a mask. Then, the CVD SiO ₂ film 17 is coated to a thickness of 1,000Å.

As shown in FIG. 2B, a contact hole 17a is formed in the SiO ₂ film 17 on the source / drain layer 16 between the FETs.
To open. Then, a poly-Si film is deposited on the entire surface by a CVD method to a thickness of 2,000 Å and patterned to a width reaching both FET regions to form a lower electrode layer (storage electrode) 8b.
To form.

As shown in FIG. 2C, a contact portion between the source / drain layer 16 and the lower electrode layer 18b is secured, and a trench 18a having a width of 0.8 μm is formed in the region of the source / drain 16 to a depth of 1 μm. It is formed by isotropic etching. Then, the same impurities as the source / drain layer 16 are ion-implanted at a high concentration into the inner wall of the trench 18a to form the lower electrode layer 18c.

As shown in FIG. 2D, a dielectric film covering the lower electrode layer 18 is formed by coating the entire surface of the semiconductor substrate 11 with a Si ₃ N ₄ film to a thickness of 100 Å by the CVD method and patterning. 19
To form. Subsequently, a poly-Si film having a thickness of 2,000 Å is coated on the dielectric film by the CVD method and patterned to form an upper electrode layer 20 to complete the capacitor.

In the second embodiment, as shown in FIG. 3B, the patterning of the lower electrode layer 28b and the etching of the trench 28a are carried out at the same time to shorten the process. It is similar to the first embodiment.

The third embodiment is the first embodiment shown in FIG. 4A, in which contact holes are formed in the source / drain layer 36.
Fig. 4 shows that 37a and trench 38a intersect each other.
As shown in (b), the formation of the trench 38a is laterally offset. In either method, in the source / drain layer 36, the upper lower electrode layer 18b made of a poly-Si film is formed.
The required contact area of the lower electrode layer 18c composed of the impurity diffusion layer is secured.

In the fourth embodiment, when the gate electrode 44 is formed, the gate electrode 44 made of a poly-Si layer is formed by the CVD method.
And a buffer SiO ₂ film layer 44 ′ are stacked to form a contact hole 47 with this buffer SiO ₂ film layer 44 ′ as a mask.
Since a is formed by self-alignment (self-alignment), there is no possibility that the contact hole 47a will protrude from the source / drain layer 46 and short-circuit with the Si substrate 41, and the distance between the gate electrode 44 and the field SiO ₂ film 42 can be further increased. It can be shortened.

[0023]

As described above, according to the present invention, MO
When the S-DRAM memory is manufactured, the capacitance of the capacitor can be increased even if the FET formation region is miniaturized and the memory element is miniaturized. Therefore, performance of the semiconductor device such as high speed and high reliability. Has the advantage of contributing to improvement,
It is possible to provide a semiconductor device and a manufacturing method thereof, which can be expected to achieve remarkable economic and reliability improvement effects.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

2A to 2C are schematic cross-sectional views in order of the processes of the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view in order of the steps of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a third embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view in order of the steps of a fourth embodiment of the present invention.

FIG. 6 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1,11,21,41,51 Semiconductor substrate, Si substrate 2,12,22,42,52 Field SiO ₂ film, thermal
SiO ₂ film 3,13,23,43,53 Gate SiO ₂ film, thermal SiO ₂ film
Film 4,14,24,34,44,54 Gate electrode, CVD poly Si film 44 'buffer SiO ₂ film, C
VDSiO ₂ film 5,15,25,35,45,55 Transfer gate transistor source 6,16,26,36,46,56 Transfer gate transistor drain 7,17,27,37,47,57,57 Insulation film CVD SiO ₂ film 7a, 17a, 27a, 37a, 47a, 57a Lower electrode layer and contact hole of semiconductor substrate 8,18,28,38,48,58, Lower electrode layer, CVD poly Si film and impurity diffusion Layer 8a, 18a, 28a, 38a, 48a, 58a Trench 8b, 18b, 28b, 38b, 48b, 58b Lower electrode layer dug in the semiconductor substrate together with lower electrode layer CVD poly Si film 8c, 18c, 28c, 38c , 48c, 58c lower electrode layer, impurity diffusion layer 9,19,29,49,59 dielectric film, CVD Si ₃
N ₄ film 10,20,30,50,60 Upper electrode layer, CVD poly-Si film

Claims (4)

[Claims] 1. A trench (8) formed adjacent to a FET.
a) and a source / drain layer (8c) comprising an impurity diffusion layer formed in the semiconductor substrate (1) including the trench (8a)
And an insulating film connected to the source / drain layer (8c)
The conductive film (8b) formed on the FETs on both sides via (7) is used as the lower electrode (8), and the lower electrode is connected via the dielectric film (9).
(8) A semiconductor device having a capacitor having an upper electrode (10) made of a conductive film formed thereon. 2. A step of forming and patterning a gate electrode (4) through a gate insulating film (3) in a FET formation region on a semiconductor substrate (1) separated and defined by a field insulating film (2), Between the step of forming the source / drain layers (5, 6) through the gate electrode (4) and covering the insulating film (7) on the semiconductor substrate, and between the adjacent FET regions of the insulating film (7). A step of forming a contact hole (7a) on the source / drain layers (5, 6) of the same, forming a conductive film on the semiconductor substrate (1), and patterning to form a lower electrode (8b); A step of forming a trench (8a) in the formation region of the source / drain layer (5,6) while leaving a part of the contact region of the lower electrode (8b) and the source / drain layer (5,6); Impurities are diffused in the trench (8a), and the inner wall of the trench (8a) is
Connected to the source / drain layers (5,6), the lower electrode (8
c), a step of forming a dielectric film (9) so as to cover the lower electrode (8b) made of the conductive film and the lower electrode (8c) made of an impurity diffusion layer, and the dielectric film (9). And 9) via which the upper electrode (10) made of a conductive film is deposited on the lower electrode (8) and patterned. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the patterning of the lower electrode (8a) made of the conductive film and the formation of the trench (8a) are performed at the same time. 4. In the formation of the gate electrode (4),
The gate electrode (4) is covered with an insulating film (4 '), and the insulating film (4')
Masked and self-aligned to contact holes (7a)
4. The method for manufacturing a semiconductor device according to claim 2, wherein the opening is formed.