JPH0637471Y2 - Memory backup device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory backup circuit for protecting the contents of a memory unit in a device when a battery is replaced.

[Prior art]

An example of a conventional memory backup device is shown in FIG.
In the figure, a main circuit 1 including a CPU and the like, and the main circuit 1
The RAM 2 to which data is read and written based on the instruction is normally driven by a voltage supplied from the battery 3 of 1.5 V, for example. On the other hand, a backup capacitor 4 is connected in parallel to RAM2,
A diode 5 for preventing backflow is connected between the capacitor 4 and the battery 3. The capacitor 4 normally remains charged by the battery 3, but when the battery 3 is replaced, a discharge voltage is supplied to the RAM 2 so that the contents of the RAM 2 can be prevented from being erased for a certain period of time. Has become.

In addition, as another example, there is one in which, for example, a 3V battery is used, and the battery voltage is stepped down to about 1.5V and supplied to the main circuit and RAM. The capacitor is charged in advance, and the capacitor is discharged at the time of battery replacement to compensate.

[Problems of conventional technology]

In the above conventional backup method, the battery voltage is greatly reduced, so that the charging voltage of the capacitor is extremely low in any of the above cases (for example, about 1.2V). Therefore, when the battery is replaced, the time that can be compensated by the charging voltage of the capacitor becomes extremely short, and if the compensation time is increased, a large capacity capacitor must be used.

Further, in the above-mentioned conventional method, even though the battery voltage is lowered, the battery continues to be used, so that there is a drawback that the power consumption further progresses. In such cases,
In the past, it was informed that the battery voltage was low by a display etc., and prompted to replace the battery.However, from the user's recognition that the battery voltage was low, it was recognized that the battery replacement was still in progress. In many cases, the result was that the battery was not replaced until it reached a voltage at which the contents of the memory could not be protected.

Therefore, in such a conventional method, the contents of the memory may be erroneous, and the user may use the data with the erroneous contents.

[Purpose of device]

The present invention has been made in view of the above circumstances, and provides a memory backup device that prevents a user from using erroneous data when using the contents of a backed up memory after replacing a battery. To aim.

[Key points of device]

In order to achieve the above object, the present invention focuses on providing a means for checking whether or not the contents of the backed up memory are erroneous after battery replacement.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an overall circuit diagram of an electronic wrist watch with a data bank function to which an embodiment of the present invention is applied.

First, the configuration and operation of this embodiment will be schematically described with reference to FIG.

In FIG. 1, as a power supply unit, a replaceable 3V battery (for example, lithium battery) 11, a step-down circuit (for example, voltage harbor) 12 that steps down this battery voltage by half, and a constant voltage below this voltage is received. A constant voltage circuit 13 that outputs a voltage (here, −1.25 V), a voltage detection circuit 14 that detects a decrease in battery voltage, and the like are provided. The positive side of the battery 11 is grounded, and this ground level is V ₀ (= 0), and the voltage level on the negative side (that is, battery voltage) is V ₂ (= −3V). Further, the constant output voltage level of the constant voltage circuit 13 is V ₁ (= -1.25V).

The main circuit portion 15 is driven by the above voltage V ₁ . The main circuit unit 15 is a clock circuit that internally includes a ROM, a small-capacity RAM, and the like, and has a clock function of counting and displaying time,
It has an alarm function and a stopwatch function.
It also has a function of reading out and displaying various data (for example, telephone number data) stored in the memory unit 16 described later. A small-capacity capacitor C ₀ is connected in parallel to the main circuit section 15, and if there is a momentary fluctuation or interruption of the power supply due to vibration or the like, the operation of the main circuit section 15 is performed with the discharge voltage of the capacitor C _0. Can be compensated. The specific circuit configuration and operation of the main circuit section 15 will be described later in detail with reference to FIG.

The memory unit 16 has a large capacity RA for storing various data.
It is M, and its schematic configuration is shown in FIG. As shown in the figure, the memory unit 16 can store, for example, an item data storage area Xa that can store 6 characters of item data such as names and characters and 12 characters of numeric data such as a telephone number corresponding to the item data storage area Xa. , Which includes, for example, 50 registers X (X ₀ , X ₁ , X ₂ ...) Consisting of various numerical data storage areas Xb, and which is transferred from the main circuit unit 15 when the battery is replaced (for example, register X
Register Y for temporarily storing the number of
(Y ₀ , Y ₁ , Y ₂ ...). Returning to FIG. 1, the memory section
A backup capacitor C ₁ for battery replacement is connected in parallel to 16 and the above capacitor C ₁ is used for battery replacement.
The contents of the memory unit 16 can be compensated by the discharge voltage of.

The voltage control unit 17 is a control circuit for controlling the voltage Vx supplied to the memory unit 16 to protect the contents of the memory unit 16 together with the capacitor C ₁ . That is, the voltage controller 17
Switches the voltages V ₁ and V ₂ to each other in accordance with opening / closing of a switch S ₁ described later and signals a, AC and the like output from the main circuit unit 15, and supplies this to the memory unit 16 as Vx. In addition, a chip enable signal CE ₂ that enables the memory unit 16 and
A read / write signal R ₂ given to the memory section 16 at the time of reading and writing data is controlled and given to the memory section 16 as signals CET and RT, respectively. The specific configuration and operation of the voltage controller 17 will be described later with reference to FIGS. 5 and 6.

Further, in FIG. ₁ , a switch S ₁ that is turned on when the battery is replaced,
AC switch S ₂ for initializing each part (for example, clearing the memory part 16) or starting operation of the main circuit part 15 after battery replacement, and inputting data of various functions to the main circuit part 15 , Or an operation switch group S ₃ for giving a control command is shown. Among these, especially the switch S ₁
The specific configuration of S ₂ and S ₂ will be described below with reference to FIGS. 10 and 11. Here, FIG. 10 is an enlarged sectional view of an electronic wrist watch to which this embodiment is applied, and FIGS. 11 (a) and 11 (b) are
FIG. 11 is an enlarged sectional view of an essential part of a switch S ₁ in FIG.

First, in FIG. 10, a watch glass 22 is attached to the upper surface of a wristwatch case 21, and a watch module 23 is provided inside.
Is stored, and the back cover 24 is attached to the lower part. The clock module 23 is provided between the upper housing 25 and the lower portion 26.
The circuit board 27 is provided with an LSI (not shown) having the circuits shown in FIG.
Liquid crystal display panel 2 above the interconnector 28a
It is arranged so that the display drive signal is supplied to 8. The upper and lower housings 25, 26 described above are fixed to each other via a circuit board 27 by a base plate 29 made of a thin metal plate, and inside the watch case 21 via a retaining ring 30 separate from the back cover 24. It is installed. Although not shown in FIG. 10, the battery 11 shown in FIG. 1 is housed in the lower housing 26 of the timepiece module 23, and the plus side thereof is connected to the main plate 29. That is, the voltage level of the ground plane 29 is V ₀ (ground level).

Now, the switch S ₁ shown in FIG. 1 of this embodiment is provided at the lower right corner of the timepiece module 23 as shown in FIG.
As shown in FIGS. (A) and (b), it is configured to turn on and off in response to opening and closing of the retaining ring 30 during battery replacement. That is, as shown in FIG. 11, first, a stepped through-hole pressure 26a is formed in the lower housing 26, and a conductive coil spring 31 is arranged therein. The free end 31a of the coil spring 31 is fixed to the fixed end 3a.
It is formed in a spiral shape larger than 1b, the free end 31a is arranged on the large diameter side of the through hole 26a, and the fixed end 31b is formed in the through hole 26a.
The fixed end 31b is disposed on the small diameter side of the electrode terminal of the circuit board 27 (input terminal to the voltage control unit 17 in FIG. 1).
It is connected to the. A terminal plate 32 made of a thin conductive metal plate having a substantially disk shape is attached to the free end 31a of the coil spring 31, and the terminal plate 32 receives the biasing force of the coil spring 31. The large diameter side of the through hole 26a can be moved up and down. A contact portion 32a is formed on the peripheral edge of the terminal plate 32 so as to slightly project downward, and the contact portion 32a is formed when the terminal plate 32 moves downward.
Is in contact with the main plate 29. In addition, the terminal board 32
On the peripheral edge on the side opposite to the contact portion 32a, it extends relatively long upward from there, and is folded back outward in a hook shape so that its tip is located above the stepped portion 26b in the lower housing 26. The position regulating portion 32b is formed, and the main plate 2
When the 9 is removed, the position restricting portion 32 is locked to the step portion 26b so that the terminal plate 32 and the coil spring 31 can be prevented from jumping out. A circular hole 29a corresponding to the coil spring 31 is formed in the base plate 29, and a pressing portion 30a is provided on the inner side surface of the retaining ring 30 so as to project into the hole 29a. ing.

The switch S ₁ having the above-described structure is used in a normal state in which the battery 11 is housed in the lower housing 26 and the retaining ring 30 is mounted, and as shown in FIG.
Since a protrudes inward through the hole 29a of the base plate 29 and presses the terminal plate 32 against the coil spring 31, the contact portion 32 of the terminal plate 32 is abutted.
a (corresponding to terminal S ₁ b in FIG. ₁ ) is a main plate 29 (terminal S in FIG. 1)
₍ Corresponding to 1a), so that it is turned off. On the other hand, if you remove the retaining ring 30 to replace the battery,
As shown in FIG. 11 (b), the coil spring 31 is used to
Since 32 is urged downward, the contact portion 32a comes into contact with the base plate 29, and thus is turned on.

Another switch S ₂ is also provided on the lower housing 26 as shown in FIG. That is, a through hole 26c is formed in a part of the lower housing 26, and the main circuit portion 15 shown in FIG.
An electrode terminal 27a which is an input terminal to is provided,
A small-diameter hole 29b is formed in the base plate 29 at a position corresponding to the through hole 26c. Further, a hole 30b is also formed at a position corresponding to the through hole 26c of the retaining ring 30. The AC switch S ₂ thus configured has an electrode 27a (corresponding to the terminal S ₂ b in FIG. 1) and a main plate 29 (corresponding to the terminal S ₂ a in FIG. 1).
Is turned on by conducting it with a jig or the like (not shown), and is turned off otherwise.

Next, a specific circuit configuration and operation of the main circuit section 15 will be described with reference to FIG.

The ROM 41 is a fixed memory containing a microprogram and data for controlling each function, and specifies an address signal A to each memory, various data D, an instruction signal I for specifying an attached program, and the next address. The next address signal N is output. The ROM control unit 42 controls the ROM 41 based on the next address signal N from the ROMI, the output of the arithmetic circuit 45, the output of the instruction decoder 44, the output of the voltage detection circuit 14 (FIG. 1) and the like. The RAM 43 has a smaller capacity than the memory section 16 shown in FIG. 1, and is read / written based on the address signal A of the ROM 41.
It is a memory that stores data that is frequently accessed for writing. The RAM 43 is, for example, as shown in FIG. 4, a display register D that stores display data, a time register T that stores time data, an alarm time register A that stores alarm time data, and a stopwatch register that stores stopwatch data. S, various other registers n, i, P ₀ , P ₁ and various flags M, F ₀ , F ₁ , F _{2 and the} like. Here, the register P ₀ stores the number of data stored in the memory unit 16 (that is, the number of used registers X shown in FIG. 2), and the register P ₁ stores the currently designated data among them. Remember the address.

The instruction decoder 44 is a block that decodes the instruction signal I of the ROM 41 and sends a control signal to each block. The arithmetic circuit (ALU) 45 is a ROM
41, the RAM 43, the arithmetic logic operation of the data sent from the memory unit 16 and the like, and the arithmetic result is the memory unit 16, the RAM 4
3, send to the ROM control unit 42 and the like.

The oscillator 46 creates a clock signal having a constant cycle and outputs it to the timing generator 47 and the frequency dividing circuit 48. The timing generator 47 divides the clock signal to a predetermined frequency and outputs a timing signal for controlling each block and the voltage detection circuit 14 in time series. Especially RAM43
Output the chip enable signal CE ₁ and read / write signal R ₁ to the voltage control unit 17 and the memory unit 16 to the voltage control unit 17.
Output a chip enable signal CE ₂ and a read / write signal R _{2 and} a signal a for voltage switching described later. The frequency dividing circuit 48 is a counter that divides the clock signal from the oscillator 46, and creates a clock signal of a constant cycle used for clock processing and the like. The key input unit 49 includes the switches S _{1 to} S ₃ shown in FIG. ₁ , and various functions are executed based on these key operations. Of these many keys, when the AC switch S ₂ (see FIG. 10) is operated, a signal AC is output, and the signal AC causes the oscillator 46 to start oscillating or initialize each part. It is done.
The signal AC is also sent to the voltage controller 17.

The liquid crystal display device 50 is configured to include the liquid crystal display panel 28 shown in FIG. 10, and the data stored in the display register D of the RAM 43 (for example, normal time data, stopwatch data, or sent from the memory unit 16). Telephone number data, etc.) is displayed under the control of the display control unit 51. A specific display example will be described later with reference to FIG.

Next, regarding the specific configuration and operation of the voltage control unit 17,
A description will be given based on FIGS. 5 and 6. In FIG. 5, in addition to the voltage control section 17 surrounded by the alternate long and short dash line, the memory section 16 including a large-capacity RAM, the backup capacitor C ₁ thereof, and FIGS. 1 and 11 are shown. Switch S ₁ identical to
It is shown. FIG. 6 shows the signal and voltage waveform of each part in FIG.

First, in the normal state (when the battery is not replaced), the switch S ₁ is in the off state as shown in FIG. 11 (a). In this case, one input of the NOR circuit 61a in the latch circuit 61 becomes low level (= V ₀ ). The output of the other latch circuit 62 is normally low level (= V ₁ > V ₂ ),
Since this V ₁ is surely switched to the low level V ₂ by the level shifter 63, the other input of the NOR circuit 61a also becomes low level (= V ₂ ). Therefore, the output of the NOR circuit 61a becomes high level, and accordingly, the output of the NOR circuit 61b (signal c) becomes low level. The level shifter 63 and the level shifters 64, 68, 69, 71 described later are
Both are composed of CMOS inverters, for example, when the input signal is high level = OV), the high level signal is output as it is, while when the input signal is low level (= V ₁ or Vx), it is more reliable Low level (=
This is a circuit that level-shifts to V ₂ ) and outputs.

When the signal c is low level, an inverter circuit
The output (signal d) of 61c becomes high level, and the output (signal e) of the level shifter 64 becomes low level (= V ₂ ). Therefore, since the transistor 65 is on and the transistor 66 is off (the transistor 67 is also off at this point), the voltage Vx supplied to the memory section 16 is shown in FIG. The output voltage V _{1 of the} constant voltage circuit 13 is selected and output. Further, in this case, one of the input signals c of the NOR circuit 61d in the latch circuit 61 has the same low level, and the other input has the main circuit portion 15d.
The chip enable signal CE ₂ (= V ₀ or V ₁ ) from is obtained through the level shifter 68 and the level (= V ₀ or V ₀
V ₂ ). Therefore, a signal obtained by inverting the chip enable signal CE ₂ is output from the NOR circuit 61d, and this signal is given to the memory section 16 as the actual chip enable signal CET. The memory unit 16 can operate only when the chip enable signal is given. In addition, the main circuit section 15
A signal (= V ₀ or V ₂ ) obtained from the read / write signal R ₂ from the memory cell via the level shifter 69 is given to the memory section 16 as an actual read / write signal RT. When the read / write signal RT is at high level, the main circuit section 15
It becomes possible to read the data output signals O (O _{0 to} O ₃ ) based on the address signals A (A _{0 to} A ₁₁ ) from the other side. On the other hand, at the low level, the data input signals I (I _{0 to} I ₃ I ₄ ) can be written.

Next, the time of battery replacement will be described with reference to FIG. First, when removing the battery, the back lid 24 shown in FIG. 10 is opened, and the retaining ring 30 inside thereof is removed. Then, as shown in FIG. 11 (b), the switch S ₁ is turned on (FIG. 6 (a)). When the switch S ₁ is turned on, in the main circuit unit 15, data which is difficult to be erased among the data stored in the RAM 43, that is, the contents of the register P ₀ shown in FIG. 4 (stored in the memory unit 16). The number of data), the contents of the register P ₁ (address of the currently designated data among the data stored in the memory unit 16), etc. are shown in the register Y ₀ , Transfer to Y ₁ etc.

When the switch S ₁ is turned on, one input of the NOR circuit 61a becomes high level (= V ₀ ), and its output switches to low level, but the signal b remains low until the above transfer is completed. Since the output is the level and the output of the NOR circuit 61e remains at the high level, the output (signal c) of the NOR circuit 61b also remains at the low level. That is, as the voltage Vx supplied to the memory unit 16, V ₁ remains selected.

When the above-mentioned data transfer is completed, the main circuit section 15 sets the input signal to the latch circuit 62 (that is, the input signal I ₂ to the memory section 16) to the high level and sends it out, and at the same time, the signal a is set to the latch time level. Therefore, the transistor 65
Turns off and gives on road 62. As a result, the latch circuit 62 takes in the signal I ₂ and the output becomes high level.
Switches to a high level as shown in FIG. 6 (b). Then, since the output of the NOR circuit 61e becomes low level, both inputs of the NOR circuit 61b become low level,
Therefore, its output (signal c) is switched to the high level as shown in FIG. 6 (c).

When the signal c becomes high level, regardless of the chip enable signal CE ₂ from the main circuit section 15, the NOR circuit 6
Since the output of 1d (actual chip enable signal CET) becomes low level as shown in FIG. 6 (d), the memory unit 16
Becomes impossible. Further, in this case, the signal d which is the output of the inverter circuit 61c becomes the low level as shown in FIG. 6 (e), and the signal e which is the output of the level shifter 64 is as shown in FIG. 6 (f). Because of the high level, the transistor 65 turns off and the transistor 66 turns on. As a result, the battery voltage V ₂ is selected as the voltage Vx supplied to the memory unit 16. At this time, Vx is
As shown in FIG. 6 (h), it changes from V ₁ to V ₂ along the charging curve of the capacitor C ₁ . At this time, by connecting the diode 70 between the capacitor C ₁ and the battery 11,
Backflow of current is prevented. The signal c is sent to the main circuit unit 15 via the level shifter 71 in order to reliably switch the low level (= Vx) to the low level (= V ₂ ).

From the above, when replacing the battery, the switch S ₁ is turned on (when the holding ring 30 is opened) before the battery 11 is removed, and then the battery voltage V ₂ is supplied to the memory unit 16 and the battery voltage V ₂ charges capacitor C ₁ . If the AC switch S ₂ shown in FIG. 10 is turned on before removing the battery 11, even if the transistor 66 has not been switched on, the parallel connection is made to this. Since the other transistor 67 that has been turned on can be turned on, the battery voltage V ₂ can be reliably supplied to the memory section 16 and the capacitor C ₁ .

After that, when the battery 11 is removed from the lower housing 26 shown in FIG. 10, the voltages V ₁ and V ₂ become zero as shown in FIG. During this period, the discharge voltage of the capacitor C ₁ is supplied to the memory section 16 as shown in FIG. 6 (h). At this time, the voltage charged initially in the capacitor C _1, because it is at least twice near the high voltage V ₂ voltage V _1, the time that can compensate for the memory unit 16 is very long in its charging voltage. When the battery 11 is removed, the output of the voltage V ₁ is lost, so that the operation of each part of the main circuit part 15 is stopped and the oscillator 46 shown in FIG. 3 also stops oscillating.

When a new battery is installed in the lower housing 26, the battery voltage V ₂ is supplied to the memory unit 16 and the capacitor C ₁ ,
Electricity Vx rises to V ₂ along the charging curve of the capacitor C ₁ as shown in Fig. 6 (h). At this point, the main circuit section
Each part of 15 is still stopped. Then, next, when the AC switch S ₂ is turned on as shown in FIG. 6 (g), the oscillator 46 shown in FIG. 3 starts oscillating, and accordingly, each process (for example, as shown in FIG. Processing) starts.

Then, when the new battery is covered and the retaining ring 30 is attached, the switch S ₁ is switched to the off state as shown in FIG. 11 (a). When the switch S ₁ is turned off, after a certain rise time, the input signal from the main circuit unit 15 to the latch circuit 62 (that is, the input signal I ₂ to the memory unit 16) is set to the low level, and at the same time, the signal a serves as a trigger. It is applied to the latch circuit 62. As a result, the output of the latch circuit 62 becomes low level (= V ₁ ), so that the output of the level shifter 63 (signal b) is also surely low level (= V ₁ ), as shown in FIG. 6 (b).
V ₂ ). Then, since the two inputs of the NOR circuit 61a are both at the low level, the output thereof is switched to the high level, and the output of the NOR circuit 61b (signal c) is accordingly changed to the sixth level.
As shown in FIG. 7C, the level is switched to the low level.

Since the signal c becomes low level, the output of the inverter circuit 61c (signal d) becomes high level as shown in FIG. 6 (e), and the output of the level shifter 64 (signal e).
Becomes low level as shown in FIG. 6 (f). Therefore, since the transistor 65 is turned on and the transistor 66 is turned off (the transistor 67 is also in an off state unless there is a signal AC), the voltage Vx supplied to the memory unit 16 is the sixth.
As shown in the figure (h), it switches from V ₂ to V ₁ . In addition, an inverted level of the chip enable signal CE ₂ from the main circuit unit 15 appears in the output (signal CET) of the NOR circuit 61d, and if the chip enable signal CE ₂ is low level, the signal CET
Becomes high level as shown in FIG. 6 (d), and the memory section 16 becomes operable.

Then, from the RAM43 to the memory unit 1 before removing the battery described above.
The data transferred to the register Y of 6 (see FIG. 2) is returned to the original register of the RAM 43. Then, after an error check or the like is performed on those data, the normal operation is started. Details of the error check will be described later with reference to FIG. In the normal state, when the AC switch S ₂ is turned on, all the data stored in the memory unit 16 and the RAM 43 are cleared, and each unit is initialized.

Next, the overall processing operation by the main circuit section 15 shown in FIG. 3 will be described with reference to FIG. The flags F ₀ , F ₁ and F ₂ used in FIG. 7 are the same as those shown in FIG. 4, and F ₀ is a flag that is set to “1” when the battery voltage drops, and F ₁ "1" when the flag switch S ₁ when the battery is replaced, which is said to have been turned off (i.e. presser ring 30 is opened) during "1", F ₂ is the key was a no function
Is a flag. These flags are AC switch S ₂
Are turned on, all become "0".

First, in step T ₁ , normal timekeeping processing and key processing are performed for various functions such as a clock function, an alarm function, a stopwatch function, and a data bank function. However, if the flag F ₂ is 1, the above process is not performed.
After that, in step T ₂ , it is determined whether the battery voltage (V ₂ ) is lower than a predetermined level, and if it is lower, the process proceeds to step T ₃ where, for example, a display etc. informs the battery voltage drop. , And at the same time, put 1 in the flag F ₀ .
The battery voltage is determined by the voltage detection circuit shown in FIG.
Based on 14 outputs.

Then, in step T ₄ , whether or not step S ₁ is in the ON state (that is, whether or not the retaining ring 30 shown in FIG. 10 is opened) is checked, and if switch S ₁ is in the ON state, See if F ₁ = 0 at T ₅ . switch
If S ₁ is on and F ₁ = 0, it means that the pressing ring 30 has just been opened for battery replacement, so at step T ₆ , whether the flag F ₂ is 1 (that is, the key Is not functioning), see F ₂ = 1
If not, the key is made non-functioning by entering 1 in F ₂ in step T ₇ . When F ₂ = 1 is set, the process of step T ₁ is not performed as described above. Proceeding to step T _6, the memory unit 16 from the RAM43 the aforementioned
Transfers data to send after its completion, the signal e to the voltage control unit 17 as a backup process in step T ₉ (5
See Fig. And Fig. 6 (b)). By this signal e, the voltage Vx supplied to the memory section 16 is switched from V ₁ to V ₂ (see FIG. 6 (g)), and backup by the capacitor C ₁ becomes possible.

On the other hand, when the switch S ₁ is in the off state in the step T ₄ , it is checked in step T ₁₀ whether the flag F ₁ = 0. Since the switch S ₁ is off, and in the case of F ₁ = 0 is the state immediately after the battery replacement ring 30 restrained ends closed, at step T _11, the memory unit 16 described above
Transfer data (processing to restore the data transferred in Step T ₈₎ to RAM43 from. Then, in step T ₁₂ , error detection is performed on the transferred data and the data in the memory section 16. This processing will be described later with reference to FIG. If an error is found,
Clear all data in step T _15, and by performing the initialization of each part (initialization), to allow for normal processing thereafter.

If F ₁ = 0 is not satisfied in step T ₁₀ , the battery replacement has already been completed (or the battery has not been replaced), and normal processing is continuing,
After setting ₁ to flag F ₁ in step T ₁₃ , in step T ₁₄
Check if AC switch S ₂ is operated. When the AC switch S ₂ is operated, clear all data in step T ₁₅ .
And various initialization is performed.

Will now be described with reference to FIG. 8 error detection process in step T _12.

First, in step U ₁ , the number data transferred in step T ₁₁ is a predetermined number (that is, the maximum number that can be stored in the register X of the memory unit 16 shown in FIG.
For example, check whether it is within the range of 50 lines, and if it is not within this range, determine "Error". If the number data is within the predetermined number range, 1 is set in register n in step U _2.
Put in.

Then, next, in step U ₃ , it is checked whether the content of n is less than the above-mentioned number data, and if it is less than the number data, the process proceeds to step U ₄ to put 1 in the register i. Then, in step U ₅ , the i-th character of the item data included in the n-th data stored in the memory unit 16 is any one of the letters “A” to “Z” and “-” (hyphen). See if there is, and if it is not within this range, it will be an "error". If the above i-th character is in the above range, step
U ₆ adds 1 to register i. Then, in step U ₇ , whether the content of i is 6 or less, which is the maximum number of characters of the item data, is checked. If i is still 6 or less, the process returns to step U ₅ . That is, unless there is an error, the above step U ₅ is checked for all the characters of the item data.

If i> 6 in step U ₇ , the process proceeds to step U ₈ and 1 is added to i. Then, in step U ₉ , it is checked whether the i-th number of the numerical data included in the n-th data is “0” to “9” or “to” (hyphen), and this range is set. If not, an "error" is returned. If the i-th number is within the above range, 1 is added to i in step U ₁₀ . Then, in step U ₁₁ , it is checked whether the content of i is 12 or less, which is the maximum number of characters in the numerical data,
If i is still 12 or less, return to step U ₉ . That is,
Unless an error, for all the digit in the data checking in step U _9.

If i> 12 in step U ₁₁ above, step U ₁₂
After adding 1 to n, return to step U ₃ to see if n is less than or equal to the number data. If n is less than or equal to the number of data, the above step is newly performed for the nth data.
By performing the processing of the U ₄ ~U _12, the error check. In this way, when the error check is completed for all data including the number data, that is, step U ₃
When n exceeds the number data, the error detection process is terminated.

However, the processing shown in FIGS. 7 and 8 is not started unless the AC switch S ₂ is turned on after the battery is inserted. When the AC switch S ₂ is turned on, 0 is put in the above-mentioned flags F ₀ , F ₁ , F ₂ and registers n, i.

Although not shown in FIG. 7, a display process is performed at the end of the flow. In this process, the display control unit 51 controls the display register D (see FIG. 4) of the RAM 43 in FIG. It is a process to be displayed on. An example of the display is shown in FIG. A ninth display example is shown. The figure (a) is an example of a normal time display. In this example, the current time is "12
It is 10:58:50 pm on Monday, the 29th of the month. " FIG. 2B is an example of a data bank display, in which the item data (contents of the register Xa in FIG. 2) for 6 characters including names and characters is displayed in the upper display area.
In the lower display area, 12-character numeric data (contents of register Xb in FIG. 2) consisting of a telephone number or the like corresponding to the above item data is displayed. In the example of the figure, "CASI
It indicates that the telephone number of "O" is "0425-55-7211". Further, when a drop in the battery voltage is detected during the normal time display as shown in FIG. 9A (that is, when F _{0 is set} to 1 in step T ₃ above), for example, As shown in FIG. 9 (c), “Bat.” Is displayed, which allows the user to know that the battery voltage has dropped.
When the back cover 24 is opened to replace the battery and the retaining ring 30 is further opened (that is, when the switch S ₁ is in the ON state)
For example, "OPEN" is displayed as shown in FIG. 9 (d), thereby notifying that it is no function even if the key is operated. Immediately after the replacement of the batteries and the closing of the retaining ring 30 and the back lid 24, the above step T ₁₂ (U
An error detection is performed by ₁ ~U _12), during this error detection is displayed "CHECK" As shown in example FIG. 9 (e).

As described above, in the present embodiment, it is checked whether or not the data in the memory unit 16 backed up after the battery replacement is correct, and only when the data is correct, the data remains so that it is erroneous. You will no longer use the wrong data.

As described above, when it is determined that the data is correct, if the data is the name and telephone number data, the seventh
After the error detection step T _{12 in} the figure, an edit step may be provided in which data A, B, and C are rearranged in order based on the name data and sequentially stored in the memory unit 16. Further, for example, the data is date, time, and In the case of schedule data consisting of a schedule at that time, it will be extremely convenient to provide processing of an editing means for rearranging the data in a predetermined order, that is, in the order of date and time after step T ₁₂ .

Although the above embodiment is applied to an electronic wrist watch with a data bank function, the present invention is not limited to such an electronic timepiece, and various electronic devices having various memory units that need to be backed up when the battery is replaced. For example, it can be applied to a small electronic calculator, an electronic notebook, an electronic schedule, an electronic camera, a word processor, and the like.

[Effect of device]

As described above, according to the present invention, by providing the means for checking the contents of the backed-up memory unit after the battery is replaced, the erroneous data is not used as it is, so that the malfunction can be prevented.

[Brief description of drawings]

FIG. 1 is an overall circuit diagram of an electronic wrist watch with a data bank function to which an embodiment of the present invention is applied, FIG. 2 is a schematic configuration diagram of a memory unit 16 in FIG. 1, and FIG. A detailed circuit diagram of the main circuit unit 15, FIG. 4 is a schematic configuration diagram of the RAM 43 in FIG. 3, and FIG. 5 is a detailed circuit diagram of the voltage control unit 17 in FIG. 1 and its vicinity, and FIG. FIG. 7 is a timing chart for explaining the main operation of the voltage control unit 17, FIG. 7 is a flowchart showing the overall processing operation by the main circuit unit 15, and FIG. 8 is the process of step T _{12 in} FIG. FIG. 9 (a) to FIG. 9 (e) are diagrams showing a display example by the liquid crystal display device in FIG. 3, and FIG. 10 is a diagram showing an example of applying the present invention. enlarged sectional view of the electronic wrist watch, FIG. 11 (a) and (b) are turned off and on of the switch S ₁ in FIG. 10 Enlarged sectional view of state, FIG. 12 is a circuit diagram showing an example of a conventional battery backup circuit. 11 ... battery, 12 ... step-down circuit, 13 ... constant voltage circuit, 14 ... voltage detection circuit, 15 ... main circuit unit, 16 ... memory, 17 ... voltage control unit, C ₁ ... capacitor for backup, S ₁ ... switch ,
S ₂ … AC switch

Claims (1)

[Scope of utility model registration request] 1. A battery power source, a step-down means for stepping down an output voltage of the battery power source to output a step-down voltage, and a first data storage memory which operates based on the step-down voltage output from the step-down means. Voltage detection means for detecting a voltage drop of the battery power supply, notification means for notifying a voltage drop detected by the voltage detection means, and switch means for turning on the battery power supply prior to battery replacement and turning off after battery replacement ,
A second data storage memory to which the data stored in the first data storage memory is transferred when the switch means is turned on, and the second data storage memory to be charged by the step-down voltage output from the step-down means. A capacitor connected to the second data storage memory for protecting the data stored in the data storage memory; and a step-down voltage output from the step-down means for charging the capacitor when the data transfer is completed. To the output voltage of the battery power source from the voltage switching means for returning to the step-down voltage when the switch means is turned off, and the data transferred to the second data storage memory when the switch means is turned off. Transfer means for returning to the first data storage memory, and storing in the first and second data storage memories after data is returned by the transfer means Memory backup device comprising; and a checking means for checking the data being.