JPH0638231B2 - Micro program controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in efficiency of a microprogram memory among microprogram controllers.

2. Description of the Related Art In a conventional horizontal type micro program control device, an instruction length is lengthened and an operation is executed in parallel, and accordingly, a structure of a micro program memory and an instruction length for one address are lengthened. . Therefore, when operations cannot be performed in parallel, a part of the instruction group is effective, and most of the remaining parts are non-operations (NOP instructions),
Memory is not used effectively.

An example of the above-described conventional micro program control device will be described below with reference to the drawings.

FIG. 4 shows the structure of a conventional micro program controller. As shown in FIG. 4, 1 is an address register, 2 is a microprogram memory, 3 is a register for fetching the instruction output of the microprogram memory 2, and 4 is an adder circuit for adding “1” to the output of the address register 1. is there.

In the conventional micro program control device configured as described above, first, the output of the micro program memory 2 is fetched into the register 3 and sent to each arithmetic unit by using the value of the address register 1 as an address signal. At the same time as this register 3 is fetched, the value obtained by adding "1" to the address signal is latched in the address register 1 by the adder circuit 4, and the next address signal is generated. Moreover, the operation speed is increased by increasing the length of the register 3 and independently providing an instruction field such as a multiplication unit addition / subtraction unit and operating these arithmetic units in parallel.

Problems to be Solved by the Invention However, in the above-described configuration, even if the arithmetic units are not operated in parallel, it is necessary to have a field of the arithmetic units that do not operate, and the efficiency of the microprogram memory is poor. Had. That is, as shown in FIG. 5, most fields of the instruction group are NOPs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a micro program control device capable of improving the efficiency of a micro program memory with a simple structure.

Means for Solving the Problems A microprogram control device of the present invention includes a microprogram memory for storing a microprogram including tag bits, an address register for holding an address signal given to the microprogram memory, and the address register. A first adder circuit for adding "1" to the output, a multiplexer for periodically switching the output of the address register and the output of the first adder circuit to supply an address signal to the microprogram memory, and the multiplexer. A first register for fetching the microinstruction group output of the microprogram memory when the output of the address register is used as an address signal,
A second register for fetching the microinstruction group output of the microprogram memory when the output of the first register and the output of the first adder circuit by the multiplexer are used as address signals; and the first register output The addition of the output signal of the multiplexer is controlled by the tag bit signal of 1., and the second addition circuit for supplying the output to the address register is provided.

Operation According to this configuration, whether the micro program memory is accessed twice within the machine cycle and two types of micro instruction groups, which are outputs thereof, have execution instructions, or whether one micro instruction group is all NOP instructions. Is indicated by the tag bit and the instruction group for one micro is all NOP instructions, the value of the address register is the value obtained by adding “1” to the previous value, and the two types of micro. If there is an execution instruction in both of the instruction groups, the value obtained by adding "2" to the previous value is set, and the number of NOP instructions in the microprogram memory is reduced to improve efficiency.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 is a block diagram of a microprogram controller of the present invention. 5 is an address register, 7 is a first adder circuit for adding "1" to the output of the address register 5,
The output of the address register 5 to T ₁ interval, also supplies an address signal to the microprogram memory 6 the output of the first adder circuit 7 time-share by the multiplexer 8 on the T ₂ period. Time sharing T above
The microinstruction group when the output of the address register 5 is used as the address signal of the microprogram memory 6 in _one section is fetched into the first register 9 when T ₁ changes to T ₂ .

Further, the output of the first register 9, the output of the first adder circuit 7 at T ₂ interval with micro instructions output when the address signal of the microprogram memory 6, from T ₂ in the second register 10 Fetched on transition to T ₁ . The output of the first register 9 includes a tag bit indicating whether or not all the microinstructions that fetch the output of the microprogram memory 6 directly into the second register 10 are NOP instructions. It is determined whether "1" is added to the output of the multiplexer 8 in the adder circuit 11 of. The output of the second adder circuit 11 indicates the address of the next microinstruction group and is latched in the address register 5.

The operation of the microprogram controller having the above structure will be described with reference to FIGS. 2 and 3.

FIG. 2 shows a timing chart in the configuration of FIG. FIG. 3 is a memory map of the microprogram memory 6, in which tag bits consisting of p bits (p = 1 in this embodiment) are provided at predetermined positions (most significant bit in this embodiment). In this configuration, the machine cycle is T = T ₁ + T ₂ . Now, assuming that the content of the address register 5 is "n", the multiplexer 8 is controlled to output "n" in the T ₁ section and output "n + 1" in the T ₂ section. And T ₁
The output of the microprogram memory 6 on the transition from T to T ₂ is fetched into the first register 9. This content is a microinstruction group at the address "n" in the memory map of FIG. 3, and the most significant bit includes the tag bit. This tag bit is the next T ₂ to T ₁
At the time of the change to, the microinstruction group (n + 1) whose address is the output “n + 1” of the multiplexer 8 fetched into the second register 10 together with the microinstruction group (n) which is the output of the first register 9 is the NOP instruction. It is shown whether or not it is constituted by only the micro instruction group (n + 1) is an invalid instruction group which is meaningless when set to the low bit side of the second register 10. Here, in FIG. 2, this tag bit is "0". At the same time, since the tag bit is "0" in the second adder circuit 11, "n +" is added without adding "1".
1 "is set in the address register 5 when T ₂ changes to T _1. Next, the content of the address register 5 is" n ".
In the case of +1 ”, the output of the microprogram memory 6 by the address signal“ n + 1 ”output from the multiplexer 8 in the T ₁ section changes the output of the microprogram memory 6 from T ₁ to T ₂ by the address signal“ n ”. the output of is fetched into the first register 9. When the tag bits in the contents is "1", is fetched to the low-bit side of the second register 10 from the next T ₂ when the change in the T ₁ Means that there is an instruction that is not a NOP in at least one of the microinstruction groups.
In 11, "n + 2" to "1" is added, the _{T 2} T
_When changing to ₁ , the address register 5 is set to "n + 3". From this fact, in FIG. 3, the memory configuration is as follows: address n, address n and (n + 1),
Each address (n + 3) constitutes one instruction group. Here, whether the instruction group on the low bit side of the second register is all NOP instructions or at least one instruction (for example, adder instruction) is an execution instruction is determined by the mask bit on the arithmetic unit side. You can easily judge if you decorate.

Furthermore, in a configuration that allows a jump instruction, a branch instruction, etc., it is only necessary to add a new multiplexer that inputs the output of the address register and the jump destination.

EFFECTS OF THE INVENTION As described above, according to the present invention, a tag bit is provided in a microprogram memory, and an access to the microprogram memory is executed twice within a machine cycle to execute various arithmetic units in parallel. It is possible to enhance the utilization effect of the microprogram memory by controlling the contents of the address register with this tag bit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the microprogram controller of the present invention, FIG. 2 is a timing chart diagram of FIG.
FIG. 3 is a memory map diagram of the microprogram memory of FIG. 1, FIG. 4 is a configuration diagram of a conventional microprogram controller, and FIG. 5 is a memory map diagram of FIG. 5 ... Address register, 6 ... Micro program memory, 7 ... First adding circuit, 8 ... Multiplexer,
9 …… First register, 10 …… Second register, 11 ……
Second adder circuit.

Claims (1)

[Claims] 1. A microprogram memory for storing a microprogram containing a tag bit, an address register for holding an address signal given to the microprogram memory, and a first for adding "1" to the output of the address register. An adder circuit, a multiplexer for switching the output of the address register and the output of the first adder circuit periodically to supply an address signal to the microprogram memory, and the output of the address register by the multiplexer as an address signal A first register for fetching the output of the microinstruction group of the microprogram memory, and the output of the first register and the multiplexer of the microprogram memory when the output of the first adder circuit is used as an address signal. micro A second register for fetching a group output and a second adder circuit for controlling the addition of the output signal of the multiplexer by the tag bit signal of the first register output and supplying the output to the address register. Program controller.