JPH0638470B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, which is related to an improvement of a semiconductor integrated circuit device including at least a part of a static induction transistor (SIT).

Integrated circuits including SITs are in the spotlight because they have high speed operation, low energy consumption, low noise and high integration density.

FIG. 1 shows a structural example of a conventional I ² L type logic integrated circuit including SIT. 1A is a sectional view, FIG. 1B is a plan view, and FIG. 1B is a sectional view taken along the line AA 'in FIG. 1B. Arrogant pnp bipolar transistor (B
PT) T ₁ and inverted n-channel SIT T ₂ are mixed to form an IIL type structure. Input signal is SI
It is put into the gate terminal 4 of T T ₂ and accordingly pnp
BPT T ₂ emitter (injector) p ⁺ region 15
Holes are injected into the gate p ⁺ region 14 of the SIT T ₂ to operate as a load transistor in the previous stage. The height and / or the width of the valley of the potential barrier formed in the SIT T ₂ channel n ⁻ region (or the intrinsic region) 13 is changed according to the input signal voltage to change the source terminal 2 and the source n.
⁺ Region 12, drain output terminal 1, drain n ⁺ region 1
The resistance between 1 is changed to perform a logical operation. 1
The product of power consumption per gate and delay time p × τ is S
Total volume of IT T _2, in particular because they are affecting the gate capacitance n ^- by approximately 10μ thick impurity density regions of the 13 lower is desirable, for example, when the 1 × 10 ¹³ cm ^-3, the gate area When 1000μ ² , p × τ is about 0.01p
J / gate can be obtained. However, at this time, since a forward voltage is applied to the gate p ⁺ region 14 of the SIT, holes are injected into the n ⁻ region 13 although the amount is small, causing a carrier accumulation effect and slowing the speed. This is remarkable because the life of minority carriers is longer as the impurity density is lower. Further, the width Wc of the n ⁻ region 13 surrounded by the gate p ⁺ region 14 of the SIT T ₂ is such that when in the off state, the channel is entirely depleted to form a potential barrier, and when in the on state, no charge is applied to the channel. Since it often operates by forming a neutral approximate region, it is necessary to increase the value of Wc when the impurity density of the n region 13 is low. That is, in this case, the value of Wc is often less than or equal to twice the thickness of the depletion layer in which the gate 4 spreads at 0 bias, so that n ⁻
It increases in proportion to the reciprocal of the square root of the impurity density in the region 13. Of course, this value is not limited to this I ² L type, but is selected according to the gate voltage and the drain voltage in the off state in other integrated circuits and semiconductor devices as well, but is widely selected as the impurity density is lower. In addition, I ² L shown in FIG.
In the case of the mold, since it is formed by the base n ⁻ region 13 of the BPT T ₁ for injector, the base width W _b is usually widely selected so as not to punch through so as to have a good saturation characteristic, and also the n ⁻ region 13 is formed. The lower the impurity density of, the wider the selection. Further, as shown in FIG. 1 (b), I
^{In the 2} L type, for example, when the drain terminal 1 of the SIT is connected to the gate terminal 4B of the adjacent SIT, the SIT of the next stage is turned on when the first SIT is turned off. A potential difference close to the logical amplitude is generated between the p ⁺ regions 14 and 14B, and when the spacing Wi between the SITs is narrow, each gate acts as a lateral pnp BPT, and the gate of the on SIT is the gate of the off SIT from the p ⁺ region. p ⁺
Holes are injected into the region and the gate potential of the off SIT increases. Therefore, the distance W between the gates of each SIT
In many cases, i is wider than the base width W _b of the injector BPT. Of course, it is possible to form a so-called separation layer in which each gate is surrounded by an n ⁺ region, but the number of steps increases and the capacity increases more than necessary. As described above, by lowering the impurity density of the n ⁻ region,
The high speed and low power consumption of SIT are improved, but the integration density is reduced. This is not limited to the I ² L type SITL shown as an example in FIG. 1, but an integrated circuit incorporating another SIT, such as an ECL type, an NTL type, a TTL type, or an EFL.
Type, DCTL type, memory device, analog integrated circuit, and gate structure are not limited to junction type, Schottky type, insulated gate type, and not only n channel but also p type.
The same applies to channels.

This problem is not limited to the inverted type shown in FIG. 1 but also in the so-called upright type (see FIG. 2) in which the source electrode 2 is formed on the same surface as the gate electrode 4, and W _c is n. ⁻
The lower the impurity density of the region 13, the wider the selection. FIG. 2 shows an example in which the drain electrode 1 is formed on the same surface as the gate electrode 4 and the substrate 104 is a p ⁻ region. The n ⁺ buried region 111 is an example provided to reduce the drain resistance.

The present invention provides an integrated circuit with the above drawbacks improved, and it is possible to have a high integration density without significantly impairing the conventional low capacitance. The gist of the present invention is
The low impurity density in which the gate is formed has a stepwise or gentle impurity density distribution, the impurity density on the main surface side where the gate is formed is made relatively high, and the gate interval is narrowed. By forming a layer having a lower impurity density or an intrinsic semiconductor layer, the capacitance around the gate is reduced. Further, in manufacturing, a large amount of epitaxial type is introduced to facilitate manufacturing.

The present invention will be described in detail below with reference to the drawings.

FIG. 3 shows an example of a structure in which the present invention is applied to SIT, and shows a state of being included in a part of a semiconductor device, particularly an integrated circuit. (A) and (b) are examples of SIT which has a planar gate structure, 1 and 2, 4 are a drain electrode, a source electrode, and a gate electrode terminal, respectively, and n-type high impurity density regions 11 and 12, respectively. And is in contact with the p-type high impurity density region 14. The n-type low impurity density region in which the channel is formed includes an n-type layer 13 having a relatively high impurity density disposed on the main surface side and an n-type layer or an intrinsic semiconductor layer having a relatively low impurity density below the n-type layer 13. It consists of 113 and. In the figure, an insulating film such as an oxide film or a nitride film for protecting the surface is omitted. (A) and (b)
Is an example to which the SIT present invention having a step-cut structure is applied. The n-type low impurity density region in which a channel is formed is a region 13 having a higher impurity density and a region 113 having a relatively low impurity density. It is divided into (A)
Is an example of a upright of the gate p ⁺ region 14 is formed in the recess bottom surface, (b) a gate electrode 4 formed gate p ⁺ region 14 in the recess side walls through the bottom surface of the recess and the insulator 20 insulating It is an example of the inverted type. These examples are also upright,
The main electrodes 1 and 2 can be reversed regardless of the inverted type. In the case of (b), the bottom surface of the recess may reach the n ⁺ region 12. The boundary between the n ⁻ layer 13 and the n ⁻ (or i) layer 113 may be in contact with the gate p ⁺ region. The point is that the potential barrier is n ⁻
It is an object of the present invention to be formed inside the region 13.

(C) is an example of an SIT having a buried gate structure, in which the gate p ⁺ region 14 is formed inside the n ⁻ layer 13. Although some examples of applying the present invention to the junction type n-channel SIT have been shown above, the present invention can be applied to the p-channel as well, and can be applied to all other SIT structures proposed by the present inventor. Further, the second main power supply can be taken out not only from the back surface but also from the main surface side by the structure of FIG. 2 and etching from the main surface side. The low impurity density region 13 having a relatively high impurity density is 1
It has an impurity density of 0 ¹⁷ cm ^-3 or less, and its thickness is appropriately selected depending on the purpose. The impurity density of the low density low impurity density region 113 is preferably 10 ¹⁵ cm ^-3 or less. Channel width W
_c , thickness of gate p ⁺ region 14 and n ⁻ region 13, n ⁻
(Or i) The impurity density and thickness of the region 113 are appropriately selected according to the purpose. For example, in a normally-off type SIT using a state where no voltage is applied to the gate 4 (0 bias or open) as an off state, diffusion of the gate junction is performed. As the potential barrier forms a potential barrier in the channel, in other words, the depletion layer closes the channel region, n ^- 1
It is desirable to select an impurity density of 3 and a channel width W _c, and it is further desirable that the n ⁻ (or i) layer 113 is entirely depleted in order to reduce the effect of accumulating minority carriers and to reduce the capacity. . On the contrary, in the normally-on type, it is often desirable that a charge neutral approximation region is formed in the channel when the gate voltage is 0 V, and the impurity density and size of each region are selected. According to the present invention, due to the presence of the n ⁻ layer 13, the channel width W _c can be narrowed and the integration density can be improved when integrated into a circuit. For example, in the I ² L type shown in FIG.
^- 1000Gate layer at ^{1~3 × 10 13 cm -3 / mm} 2
^However , it was 2 by ^changing to 1 × 10 ¹⁴ cm ^-3.
It is possible to double or more. Further, in the normally-off type SIT, since the diffusion potentials of the gate p ⁺ region 14 and the channel n ⁻ region 13 become higher, the injection of minority carriers into the channel can be further reduced, which is advantageous for high speed operation.

FIG. 4 shows another embodiment of the present invention.
A sectional view of a unit is shown. (A) and (b) are examples in which the present invention is applied to an SIT having a Schottky gate 4,
A channel region is formed from the n ⁻ layer 13 having a relatively high impurity density and the n ⁻ (or i) layer 113 having a relatively low impurity density.
In (a), the embedded n ⁺ layer 111 is provided in the p-type substrate 104, and the other main electrode 1 is provided on the same main surface as the gate electrode 4. (B) is an example of a step cut type, in which the gate electrode 4 forms a Schottky junction on the concave side.
(C) is an example in which the present invention is applied to an SIT having an insulated gate type structure, and the channel region has a relatively high impurity density layer 13 and a low impurity density (or intrinsic semiconductor) layer 11.
3, both p-type and n-type can be used.
The insulated gate structure has a gate electrode 4 and an insulating film 2 on the sidewall of the recess.
0, semiconductors 13, 113. Gate electrode 4
May reach the n ⁺ regions 11 and 12 in contact with the main electrodes 1 and 2. Of course, the conductivity type can be reversed, and the invention can be applied to other Schottky and MIS type SIT.

A manufacturing example for realizing the structure of the present invention will be described below.
FIG. 5 is an example of a manufacturing process for realizing the SIT structure shown in FIG. 3A, and in FIG. 5A, S is formed on the n ⁺ Si substrate 11.
n ⁻ (or i) layer 11 by i epitaxial growth
3 is grown, and the n ⁻ layer 13 having a relatively high impurity density is continuously grown.

FIG. 5 shows a part of the process for realizing the structure of FIG. 3 (c). Two n ⁻ layers 113, 1 having different impurity densities
3 is continuously epitaxially grown to selectively diffuse p-type impurities (a), and then the n ⁻ layer 13 ′ is epitaxially grown again to fill the p − type region in the n ⁻ region (b). After that, an oxide film is formed by thermal oxidation. Next, a window is opened in the oxide film at the required size and position by photolinography, and n
Type impurities (P, Sb, As, etc.) are diffused, windows for electrode extraction are opened in the oxide film, metal (for example, Al) is vapor-deposited, and unnecessary portions of the metal are etched to achieve the required wiring and completed. To do. Of course, the impurity addition can also be performed by ion implantation or selective growth.

As described above, the semiconductor device according to the present invention can be easily manufactured by introducing multiple epitaxial growth. Of course, the manufacturing example is not limited to the above, and the selective growth method, ion implantation, molecular beam deposition, etc. can be introduced. Further, the semiconductor material is not limited to Si, but may be Ge or Ga.
It is possible to use III-V group compound semiconductors such as As and mixed crystals thereof. Further, the drain electrode of the SIT according to the present invention can be formed into a Schottky junction to enable high speed logic operation.

Further, it goes without saying that the present invention can be applied not only to the vertical structure but also to the horizontal structure.

The SIT according to the present invention is I ² L type, ECL type, NTL type,
It can be used for logic circuits of EFL type, DCTL type, TTL type, RTL type and the like, and can also be used for storage circuits such as RAM and ROM.

According to the present invention, the main current region is formed by the first channel region having a low impurity density and the second channel region having a higher impurity density than the first channel, and the gate region is the second channel region.
Since it is formed so as to sandwich the inside of the channel region or the second channel region, the gate interval W _c can be made small without significantly impairing the gate low capacitance, so that high integration is easy. According to the present invention, since the diffusion potential between the gate region and the second channel region becomes higher, the injection of minority carriers into the second channel region can be reduced, so that high speed operation and low power consumption operation are easy. Is.

[Brief description of drawings]

FIGS. 1A and 1B are structural examples of a conventional I ² L type SITL, and FIG. 1A is a sectional view taken along line AA ′ of FIG.
FIG. 3 is a structural example of a conventional upright SIT, FIGS. 3A to 3C are structural cross-sectional views showing one unit of the SIT according to the present invention, and FIGS. 4A to 4C are the present invention. 5A and 5B are diagrams for explaining an example of a manufacturing process of a part of the semiconductor integrated circuit device according to the present invention.

Claims (7)

[Claims] 1. A first main electrode region (11, 12) having a first conductivity type high impurity density, and a first main conductivity type low impurity density first electrode formed on the first main electrode region. A channel region (113), a second channel region (13) formed on the first channel region and having a first conductivity type and a higher impurity density than the first channel region, and the second channel region (13). A second conductivity type high impurity density gate region (14) formed inside the channel region, and a first conductivity type high impurity density second main region formed in a part of an upper portion of the second channel region. A semiconductor integrated circuit device comprising a static induction transistor composed of an electrode region (12, 11). 2. A first main electrode region (11, 12) having a first conductivity type and a high impurity density, and a first main conductivity type low impurity density formed on the first main electrode region. A channel region (113), a second channel region (13) formed on the first channel region and having a first conductivity type and a higher impurity density than the first channel region, and the second channel region (13). At least a pair of recesses formed in a part of the channel region, and a second conductivity type high impurity density gate region (14) formed in a part of the bottom surface and a part of the side wall of the recesses.
And a second main electrode region (12, 11) of the first conductivity type and high impurity density formed on the second channel region between the at least one pair of recesses. A semiconductor integrated circuit device comprising an inductive transistor. 3. A first main electrode region (11, 12) having a first conductivity type high impurity density, and a first main conductivity type low impurity density first electrode formed on the first main electrode region. A channel region (113), a second channel region (13) formed on the first channel region and having a first conductivity type and a higher impurity density than the first channel region, and the second channel region (13). At least one pair of recesses formed so as to reach the first channel region from a part of the surface of the channel region, and a second recess formed in a part of the second channel region on the side wall of the recess. A second region between the conductivity type high impurity density gate region (14) and the at least one pair of recesses;
And a second main electrode region (12, 11) having a first conductivity type and a high impurity density formed on the channel region of the semiconductor integrated circuit device. 4. A first main electrode region (11, 12) having a first conductivity type and a high impurity density, and a first main conductivity region and a low impurity density first main electrode region formed on the first main electrode region. A channel region (113), a second channel region (13) formed on the first channel region and having a first conductivity type and a higher impurity density than the first channel region, and the second channel region (13). At least a pair of recesses formed so as to reach the first channel region from a part of the surface of the channel region and a part of the second channel region of the side wall of the recess are formed. A Schottky gate electrode (4) and a second main electrode region (12, 11) of the first conductivity type and high impurity density formed on the second channel region between the at least one pair of recesses. ) And an electrostatic induction transformer The semiconductor integrated circuit device which comprises a register. 5. A first main electrode region (11, 12) of the first conductivity type having a high impurity density and a first main electrode region of the first conductivity type having a low impurity density formed on the first main electrode region. A channel region (113), a second channel region (13) formed on the first channel region and having a higher impurity density than the first channel region, and a surface of the second channel region. At least a pair of recesses formed so as to reach a part of the first channel region, and a gate insulating film (20) formed on the bottom and side surfaces of the recesses.
And a gate electrode (4) formed on the gate insulating film.
And a second main electrode region (12, 11) of the first conductivity type and high impurity density formed on the second channel region between the at least one pair of recesses. A semiconductor integrated circuit device comprising an inductive transistor. 6. A semiconductor substrate (104), a first conductivity type high impurity density buried region (111) formed on the semiconductor substrate, and a first conductivity type low region formed on the buried region. Impurity density first channel region (1
13) and a second channel region (13) formed on the first channel region (113) and having a first conductivity type and a higher impurity density than the first channel region (13),
A first conductivity type high impurity density first main electrode region (11) formed on the second channel region and at least a pair of Schottky gate electrodes (4); A second main electrode region (1 formed above the second channel region between Schottky gate electrodes).
2) A semiconductor integrated circuit device including a static induction transistor composed of 1) and 2), wherein the semiconductor substrate is a second conductivity type which is a conductivity type opposite to the first conductivity type. 7. A semiconductor substrate (1) of the first conductivity type having a high impurity density.
A second epitaxial growth layer (13) having a first conductivity type and a low impurity density and a second epitaxial growth layer (13) having a higher impurity density than the first epitaxial growth layer are continuously and epitaxially grown on top of the second conductivity type. And the second epitaxial growth layer (13)
A second step of selectively diffusing a pair of gate regions (14) of a second conductivity type with a low high impurity concentration on the upper surface of the second conductive type;
A third step of forming a third epitaxial growth layer (13 ') of the first conductivity type and having an impurity density substantially equal to that of the second epitaxial growth layer on the upper part of the epitaxial growth layer (13). A method of manufacturing a semiconductor integrated circuit device including a static induction transistor.