JPH0638475B2 - Complementary field effect transistor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a complementary field effect transistor device (hereinafter, CM).
The present invention relates to a structure of a CMOS transistor for preventing the current latch-up of a parasitic thyristor which is inevitably formed due to the structure of a CMOS transistor.

[Conventional technology]

FIG. 4 is a sectional view showing the structure of the COMS transistor, in which the P-type wells 2 and 3 are formed in the n-type substrate 1. In the wells 2 and 3, P ⁺ regions 4 and 5 for ohmic contact with wiring and n ⁺ regions 6 and 7 to be source / drain regions.
(However, only one of the source region and the drain region is shown, and the same applies hereinafter), the P ⁺ region 4 and the n ⁺ region are at the ground potential, and the P ⁺ region 5 and the n ⁺ region 7 are at the ground potential. It is connected to the negative potential Vss. On the other hand, a P ⁺ region 8 to the n-type substrate 1 serving as the source and drain regions and ohmic contact for n ⁺ regions 9 are formed, these P ⁺
Region 8 and n ⁺ region 9 are connected to positive potential Vcc.

Therefore, the n ⁺ region 7, P well 3, n type substrate 1 and P
^A parasitic thyristor is formed with the ⁺ region 8.

In the CMOS transistor having such a configuration, when the ground potential, the negative potential Vss, and the positive potential Vcc are fixed in this order when the power is turned on, a parasitic thyristor latch-up phenomenon occurs. That is, when the negative potential Vss is fixed after the ground potential is supplied to the well 2 by fixing the ground potential, the n-type substrate 1 in the floating state has a voltage close to the negative potential Vss due to the junction capacitance between the substrate 1 and the well 3. Is reduced. As a result, the n-type substrate 1 and the well 2 are forward biased, and a large amount of holes flow from the well 2 into the substrate. This hole further flows into the well 3 and the negative potential V
Reach the P ⁺ region 5 connected to ss. As a result, P
The potential in the vicinity of the ⁺ region 5 rises, this time the well 3 and the n-type substrate 1 are forward biased, and excess electrons are accumulated in the substrate 1. When the positive potential Vcc is fixed in this state, excess electrons flow into the P ⁺ region 8 and P
Holes flow from the ⁺ region 8 into the n-type substrate 1 to ignite the parasitic thyristor.

In this way, when the parasitic thyristor fires and a latch-up phenomenon occurs, a large current flows and the wiring etc. is melted.
Conventionally, the distance between the wells 2 and 3 and the distance between the well 3 and the P ⁺ region 8 are set large, and the substrate resistance between them is increased to prevent the movement of electrons and holes.

[Problems to be solved by the invention]

However, in the above-mentioned conventional CMOS transistor device, since the distance between the wells is set large in order to prevent the latch-up phenomenon, the area occupied by each CMOS transistor on the substrate becomes large, and high integration is achieved. There was a problem that it could not be achieved.

Therefore, the present invention is excellent in latch-up resistance, and
It is an object of the present invention to provide a CMOS transistor device which uses a positive and negative dual power supplies and can be highly integrated.

[Means for solving problems]

A first conductive type semiconductor substrate to which a first reference potential is supplied;
A first well region of the second conductivity type formed on the surface of the semiconductor substrate and supplied with a second reference potential different from the first reference potential, and a surface region of the semiconductor substrate separated from the first well region. In a complementary field effect transistor device having a second well region of a second conductivity type supplied with an intermediate potential between a first reference potential and a second reference potential, a first well region facing the second well region is provided. The gist is that a high concentration second conductivity type region is formed in the boundary region and a second reference potential is supplied to the second conductivity type region.

[Action and effect]

In the complementary field effect transistor device having the above structure, after the second well region is fixed to the intermediate potential, the first well region is fixed to the second reference potential while the semiconductor substrate is in the floating state. Carriers of the first conductivity type are injected from the semiconductor substrate into the second well region, and carriers of the second conductivity type injected into the substrate from the second well region are the first.
Flow into the well region. However, the carrier of the second conductivity type is absorbed by the second conductivity type region connected to the second reference potential, and does not change the potential of the first well region.
The well region and the semiconductor substrate are not forward biased, and the parasitic thyristor is not fired. As described above, the present invention is premised on the inflow of carriers of the second conductivity type from the second well region to the first well region, so that the interval between these well regions can be narrowed and the degree of integration can be improved. it can.

〔Example〕

1 and 2 are views showing an embodiment of the present invention,
In the figure, the same components as those of the conventional example are denoted by the same reference numerals and the description thereof will be omitted. In the figure, 10 indicates a high-concentration P-type impurity region, and these P ⁺ regions 10 are provided in the boundary region of the well 3 facing the P well 2 and separated from each other by about 50 μm. These P ⁺ regions 10 are made up of aluminum wiring 11
It is connected to the negative potential together with the ⁺ region 7 and the P ⁺ region 5.

Therefore, after the P well 2 is fixed to the ground potential,
The well 3 is fixed to the applied potential, and electrons are injected into the P well 2 from the semiconductor substrate 1 in the floating state,
Even if holes from the P well 2 flow into the well 3 through the substrate 1, the holes are absorbed by the P ⁺ region 10. As a result, the potential of P well 3 does not rise, and P well 3 and substrate 1
And are never forward biased. Therefore, the parasitic thyristor is not fired and the latch-up phenomenon does not occur.

FIG. 3 shows a modification of the embodiment, in which the P ⁺ region 10 is formed elongated along the boundary of the well 3. As a result, the number of contacts with the aluminum wiring 11 can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of the present invention, and FIG.
FIG. 4 is a plan view, FIG. 3 is a plan view of a modified example of the embodiment, and FIG.
FIG. 5 is a schematic sectional view of a conventional example, and FIG. 5 is a sectional view for explaining a latch-up phenomenon. 1 ... Semiconductor substrate, 2 ... Second well, 3 ... Third well, 10 ... Second conductivity type region, Vcc ... First reference potential,
Vss-second reference potential, GND-intermediate potential.

Claims (1)

[Claims] 1. A first conductivity type semiconductor substrate to which a first reference potential is supplied, and a second conductivity type which is formed on the surface of the semiconductor substrate and to which a second reference potential different from the first reference potential is supplied. Of the first well region and a second well region of the second conductivity type formed on the surface of the semiconductor substrate separated from the first well region and supplied with an intermediate potential between the first reference potential and the second reference potential. In a complementary field effect transistor device having
A high-concentration second conductivity type region is formed in a boundary region of the first well region facing the second well region, and a second reference potential is supplied to the second conductivity type region. Transistor device.