JPH063868B2 - Differential type comparator circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a differential comparator circuit having a hysteresis characteristic.

[Technical Background of the Invention] In order to accurately compare two analog voltages containing a small amount of noise, a differential type comparator circuit having a hysteresis characteristic is used. In this type of comparator circuit, the output state is not inverted unless the input voltage changes by a certain value or more, so that it is extremely robust against noise.

FIG. 2 is a circuit diagram of a conventional differential comparator circuit having hysteresis characteristics, which is configured by using bipolar transistors. This comparator circuit is basically composed of a differential amplifier section 10, an output section 30, and a hysteresis control section 40.

The differential amplifying section 10 is a differential amplifying pair 1 composed of Darlington-connected pnp type transistors 11, 12 and 13, 14.
5, a current mirror circuit 18 composed of npn-type transistors 16 and 17 serving as a load circuit of the differential amplification pair 15, constant current sources 19 and 20 for supplying a constant emitter bias current to the transistors 11 and 13, respectively, and the transistor It is composed of a constant current source 21 for supplying a constant common emitter bias current to 12 and 14, and the voltage V1 supplied to one input terminal 22 is applied to the base of the transistor 11 and the base of the transistor 13 is applied to the other. The voltage V2 supplied to the input terminal 22 is applied.

The output unit 30 is an npn type transistor 31, 32, a constant current source.
33 and the load resistance 34 of the transistor 32, etc., and the output terminal 35 is provided at the collector of the transistor 32.

Further, the hysteresis control unit 40 is the transistor
A resistor 41 inserted between the base of 13 and the other input terminal 23, a resistor 42 having one end connected to the base of the transistor 13, the other end of the resistor 42 and the reference voltage V _SS.
The collector and the emitter are inserted between the application point (ground potential point) and the base is composed of an npn-type transistor 44 and the like connected to the output terminal 35 through a resistor 43.

In the comparator circuit having such a configuration, when one input voltage V1 is higher than the other input voltage V2, the transistor 11 is turned off and the transistor 13 is turned on. Greater current flows. As a result, the transistor 31 in the output section 30 is turned on and the transistor 32 is turned off. Therefore, at this time the output terminal
The output signal from 35 is brought to a high potential on the _VCC side. When the output signal is at a high potential, the transistor 44 in the hysteresis control unit 40 is turned on, so that the input voltage V2 supplied to the other input terminal 23 is divided by the resistors 41 and 42 to form a transistor. Applied to 13 bases.

On the contrary to the above, one input voltage V1
Transistor 11 is turned on and transistor 13 is turned off,
A smaller current flows on the 14 side than on the transistor 12 side.
As a result, the transistor 31 in the output section 30 is turned off and the transistor 32 is turned on. Therefore, at this time, the output signal from the output terminal 35 is set to the low potential on the _VSS side. When the output signal is at the low potential, the transistor 44 in the hysteresis control unit 40 is turned off, so that the input voltage V2 supplied to the other input terminal 23 is
Is directly applied to the base of the transistor 13.

Therefore, when the magnitude relationship between the input voltages V1 and V2 is opposite,
The threshold voltage with respect to the input voltage V2 of this comparator circuit is substantially different, and exhibits a predetermined hysteresis characteristic.

[Problems of Background Art] By the way, in the above-mentioned conventional differential comparator circuit, the hysteresis control unit 40 is provided in the base circuit of the transistor 13. Therefore, there is a drawback that the input impedance on the input terminal 23 side becomes low. Therefore, a voltage drop is likely to occur at the input terminal 23, which causes an inconvenience that the threshold voltage becomes inaccurate. This is particularly remarkable when the voltage V2 is supplied to a plurality of comparator circuits in parallel.

Therefore, as a countermeasure against this inconvenience, it is possible to prepare a buffer amplifier and supply the voltage V2 to the input terminal 23 via this buffer amplifier. However, in this case, the number of elements becomes large, resulting in an increase in chip size when integrated into an integrated circuit.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object thereof is to obtain a hysteresis characteristic without lowering the input impedance and to provide a differential circuit with a relatively small number of elements. Type comparator circuit.

[Summary of the Invention] In order to achieve the above object, in a differential comparator circuit of the present invention, a differential amplifier pair is configured by first and second Darlington transistors, each of which is a first-stage transistor and a second-stage transistor. The amplifying pair and the load means constitute a differential amplifying means, and the value of the emitter bias current of one of the first stage transistors of the first and second Darlington transistors is changed according to the output signal of the differential amplifying means. As a result, the base and emitter voltages of this transistor are made to differ depending on the input state, thereby obtaining a hysteresis characteristic.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit diagram showing the configuration of an embodiment of a differential comparator circuit according to the present invention, and the portions corresponding to those of the conventional circuit are designated by the same reference numerals.

The pnp type transistors 11 and 12 compose one of the differential amplification pair 15, and the emitter of the transistor 11 and the high potential V
_A constant current source 19 is inserted between the _CC application point.
Similarly, the pnp type transistors 13 and 14 are a differential amplifier pair 15
The constant current source 20 is inserted between the emitter of the transistor 13 and the application point of the high potential V _CC . The emitter of the transistor 11 is connected to the base of the transistor 12, and the emitter of the transistor 13 is connected to the base of the transistor 14. The emitters of the transistors 12 and 14 are commonly connected, and a constant current source 21 is inserted between the common emitter and the application point of the high potential V _CC . The transistor 11,
Each of the 13 collectors is connected to the V _SS application point.
Also, one input terminal 22 is provided on the base of the transistor 11.
And the other input terminal 23 is provided at the base of the transistor 13.

18 is a transistor 16 or 17 which is a load of the differential amplifier pair 15
In the current mirror circuit, the bases of the transistors 16 and 17 are commonly connected, each emitter is connected to the _VSS application point, and the collector of the transistor 16 is connected to the common base. The collector of the transistor 12 is connected to the collector of the transistor 16, and the collector of the transistor 14 is connected to the collector of the transistor 17.

The base of the transistor 31 is connected to the collector of the transistor 17. The emitter of the transistor 17 is connected to the V _SS application point, and the constant current source 33 is connected between the collector and the V _CC application point. The base of the transistor 32 is connected to the collector of the transistor 31. The emitter of the transistor 32 is connected to the V _SS application point, and the load resistor 34 is connected between the collector and the V _CC application point. An output terminal 35 is provided on the collector of the transistor 32.

One end of a resistor 51 is connected to the collector of the transistor 32. The base of an npn-type transistor 52 is connected to the other end of the resistor 51. The emitter of the transistor 52 is connected to the V _SS application point, and the collector is connected to the V _CC application point via the constant current source 53. Further, the collector of the transistor 52 is connected to the anode of the diode 54, and the cathode of the diode 54 is connected to the emitter of the transistor 13.
The resistor 51, the transistor 52, the constant current source 53, and the diode 54 form a bias current control circuit 50 that changes the value of the emitter bias current of the transistor 13 according to the output signal of the output terminal 35.

The value of the output current of the constant current sources 19 and 20 is set to I, and the constant current source 53 in the bias current control circuit 50 is
The value of the output current is set to a value that is n times as large, that is, nI (n is a positive real number).

Next, the operation of the circuit configured as described above will be described. First,
When one input voltage V1 is higher than the other input voltage V2, that is, when V1> V2, the transistor 11 is turned off, the transistor 13 is turned on, and the transistor 14 side is closer to the transistor 12 side than the transistor 12 side. A large current flows. As a result, the transistor 31 in the output section 30 is turned on and the transistor 32 is turned off. Therefore, at this time, the output signal from the output terminal 35 is set to the high potential on the _VCC side. Transistor 52 in bias current control circuit 50 when output signal is at high potential
Is turned on, the output current from the constant current source 53 does not flow through the diode 54 and is bypassed to the _VSS application point via the transistor 52. Therefore, at this time, the current flowing into the emitter of the transistor 13 is only the output current I of the constant current source 20.

Contrary to the above, one input voltage V1 is the other input voltage V2
Smaller than that, that is, when V1 <V2, the transistor 11 is turned on and the transistor 13 is turned off, so that a smaller current flows through the transistor 14 side than the transistor 12 side. As a result, the transistor 31 in the output section 30 is turned off and the transistor 32 is turned on. Therefore, at this time, the output signal from the output terminal 35 is set to the low potential on the _VSS side. When the output signal is at a low potential, the transistor 52 in the bias current control circuit 50 is turned off, so that the output current from the constant current source 53 flows into the emitter of the transistor 13 via the diode 54. At this time, the current flowing into the emitter of the transistor 13 becomes the current (1 + n) I which is the sum of the output current I of the constant current source 20 and the output current nI of the constant current source 53.

As described above, in this circuit, the value of the emitter current of the transistor 13 is made different depending on the magnitude relationship between the input voltages V1 and V2. Therefore, assuming that the voltage between the base and the emitter of the transistor 13 when V1> V2 is V _BE 1, and the voltage between the base and the emitter when V1 <V2 is V _BE 2, the difference voltage between the two voltages is obtained. ΔV _BE is given by the following equation.

ΔV _BE = V _BE 2 −V _BE 1 = (kT / e) × In (n + 1) ... 1 where (kT / e) is the temperature voltage of the transistor,
The value is about 25 mV at room temperature.

Therefore, in the circuit of the above embodiment, the constant current source 53
If the value of the magnification n with respect to 20 is determined, the value of ΔV _BE given by the first expression is determined, and the hysteresis characteristic according to the value of ΔV _BE can be obtained. Moreover, since the input voltage V2 supplied to the terminal 23 is directly applied to the base of the transistor 13, the input impedance with respect to this input voltage V2 can be made sufficiently high. Further, in the circuit of this embodiment, a bias current control circuit 50 is provided instead of the hysteresis control unit 40 of the conventional circuit, and the bias current control circuit 50 includes a resistor 51, a transistor 52, a constant current source 53 and a diode 54. Since the configuration is adopted, the number of elements can be significantly reduced as compared with the conventional case where the voltage V2 is supplied to the input terminal 23 via the buffer amplifier. Therefore, it is possible to reduce the chip size when integrated into an integrated circuit.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the circuit of the above embodiment, the case where the transistors 11, 12, 13, and 14 configuring the differential amplifier pair 15 are pnp type transistors has been described. However, this is configured by using npn type transistors. Of course, it is also good.

[Effects of the Invention] As described above, according to the present invention, a hysteresis characteristic can be obtained without lowering the input impedance, and a differential comparator circuit having a relatively small number of elements can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a differential type comparator circuit according to the present invention, and FIG. 2 is a circuit diagram of a conventional differential type comparator circuit. 10 ... Differential amplifier section, 15 ... Differential amplifier pair, 18, 63 ... Current mirror circuit, 20, 53, 64 ... Constant current source, 30 ... Output section, 50 ... Bias current control circuit, 54 ... Diode.

Claims (1)

[Claims] 1. A differential amplifier pair composed of first and second Darlington transistors, each consisting of a first-stage transistor and a second-stage transistor, respectively, and connected to the emitters of the first-stage transistors of the first and second Darlington transistors, respectively. A differential amplifier section comprising first and second constant current sources and a load circuit connected to the differential amplifier pair, and a base connected to a connection point between the differential amplifier pair of the differential amplifier section and the load circuit. A first transistor having an emitter connected to the reference potential, a third constant current source connected to the collector of the first transistor, a base connected to the collector of the first transistor, and an emitter connected to the reference potential. And a load element connected to the collector of the second transistor, which amplifies the output of the differential amplifier section. A third transistor whose base is connected to the collector of the second transistor and whose emitter is connected to the reference potential; a fourth constant current source connected to the collector of the third transistor; An anode is connected to the collector of the third transistor, and a diode whose cathode is connected to the emitter of the first stage transistor of either one of the first and second Darlington transistors,
And a bias current control circuit for changing the value of the emitter bias current of the first stage transistor of the first and second Darlington transistors.