JPH063897B2 - Clock reproduction method - Google Patents

Description

The present invention relates to a wireless communication system, and more particularly to a digital land mobile communication system.

(2) Conventional Technique When a GMSK (Gaussian filtered Minimum Shift Keying) modulated signal is synchronously detected, a carrier wave is generally reproduced by a Costas loop. At this time, the clock reproduction is performed by the signal after the carrier wave reproduction, and the reproduced clock is used during the carrier wave reproduction to form a loop.

FIG. 1 shows the configuration of the clock recovery unit in the conventional system. The clock component extraction unit 1 calculates a squared difference signal C ₁ (S _i ² −S _q ² ) from the signals S _i + S _q of the I + Q channels after the carrier wave is reproduced. This signal 4 contains a clock component, and in particular, the transmitted signal is MS
In the case of K, it completely matches the clock.

Then, the phase error detector 3 averages the phase error E _r between the phase of the difference signal C ₁ of the square of the I and Q signals and the clock CLK generated by the VCO 2 by the loop filter 4,
The clock CLK is generated by generating the control voltage V _{c of} 2
To play.

In the conventional method, the synchronization pull-in time of the clock phase reproduction is determined by the equivalent noise bandwidth B of the loop filter 4,
The larger is, the faster the pull-in time is. However, when B is increased, the phase noise of the reproduced clock also increases due to the influence of noise and the like, and the error rate characteristic deteriorates. Therefore, the optimum B is set by the trade-off between the pull-in characteristic and the phase noise characteristic of the clock.

(3) Problems to be Solved by the Invention The conventional method has a drawback in that in order to reduce the phase noise of the clock, it is necessary to reduce the equivalent noise bandwidth and sacrifice the synchronization pull-in characteristic to some extent.

However, when the synchronization pull-in time of the phase reproduction is limited like the TDMA (Time Division Multiple Access) method, it is desirable that the convergence is fast and the phase noise of the reproduction clock is small. In this case, in the conventional method,
At the initial pull-in, it is necessary to widen the equivalent noise bandwidth of the loop filter to speed up the pull-in, and after the pull-in, narrow the equivalent noise bandwidth to reduce the phase error. Therefore, there is a drawback that the scale of hardware increases and the control of the equivalent noise bandwidth becomes complicated.

An object of the present invention is to perform clock recovery with fast phase synchronization pull-in and low phase noise.

(4) Means for Solving the Problem In the present invention, when the clock frequency at the time of transmission is known on the receiving side, two reference clocks having the same frequency and orthogonal to each other are generated, The correlation value between the extracted clock component and each reference clock is calculated, and the phase of the clock is sequentially determined by the ratio of both correlation values to reproduce the clock.

When the frequency of the reference clock generated on the receiving side has a slight error with respect to the clock frequency at the time of transmission, the clock can be regenerated by following the change in the phase of the clock that is sequentially calculated.

(5) Function An embodiment of the present invention is shown in FIG. Here, the operation will be described using this embodiment.

First, in the clock component extraction unit 1, a squared difference signal C ₁ (S _i ² −S _q ² ) of the I + Q signals S _i + S _q after the carrier wave is reproduced is calculated.

On the other hand, the reference clock generator 11 outputs two orthogonal reference clocks C ₂ + C ₃ at a known clock frequency.

At this time, when the phase of the reference clock is P ₁ , the reference clock C ₂ is cos (P ₁ ) and the reference clock C ₃ is si.
It is represented by n (P ₁ ).

The correlator 15 uses the clock component C ₁ and the two reference clocks C 1.
The correlation value C ₄ + C ₅ with ₂ + C ₃ is calculated. At this time, C ₄ = <C ₁ , cos (P ₁ )> (1) C ₅ = <C ₁ , sin (P ₁ )> (2) Here, <+> represents a correlation operation.

The ratio of the magnitudes of the correlation values C ₄ and C ₅ is the clock component C
_{It is} a value related to the difference P ₂ between the clock phase P _{3 in 1} and the phase P _{1 of the} reference clock. That is, when the clock frequency is ω, it can be set that P ₁ = ωt (3-a) P ₃ = ωt + P ₂ (3-b). At this time, equations (1) and (2) are logically expressed by the following integral.

C ₄ = 1 / T) ▲ ∫ ^T ₀ ▼ cos (ω + P ₂ ) cos (ωt) dt ＝ cos (P ₂ ) / 2 (3-c) C ₅ ＝ (1 / T) ▲ ∫ ^T ₀ ▼ cos (ωt + P ₂ ) sin (ωt) dt = sin (P ₂ ) / 2 (3-d) where T is a clock period. This shows that P ₂ is given by P ₂ = -tan ^-1 (C ₅ / C ₄ ) (4).

Actually, GMSK is different from MSK in that the clock component C ₁ is not an accurate sinusoidal function, and the amplitude and the phase are slightly changed depending on the transmitted data. Therefore, in order to obtain an accurate correlation value, the longer the correlation length TGA is, the better. That is, increasing the time length T corresponds to narrowing the equivalent noise bandwidth.

In this method, when performing the correlation operation in the correlation unit 15, the correlation value is sequentially updated for each reception input from the reception start point. For this reason, since the time length of correlation is short in the vicinity of the reception start point, the equivalent noise bandwidth becomes wide and the synchronization pull-in becomes fast. On the other hand, the time length of correlation increases with time, the equivalent noise bandwidth gradually decreases, and the phase error decreases. In this way, this method can automatically change the equivalent noise bandwidth.

The clock phase calculation unit 16 calculates the phase difference P ₂ by the operation of Expression (4). Next, in the clock output unit 20, the sum P ₃ of the reference clock phase P ₁ and the phase difference P ₂ is obtained and the cosine component is taken, whereby the clock CLK of the received signal can be reproduced.

In the conventional method (FIG. 1), the clock signal is controlled by the phase error between the clock signal and the clock component, so that there is a feedback loop, but in the present method, the reference clock signal and the clock component are The phase difference calculation unit 16 and the clock output unit 20 are independent of each other and have the feature of being an open loop. By this point and the automatic adjustment of the equivalent noise bandwidth described above, the synchronization pull-in can be performed quickly and the phase error after the pull-in can be reduced. Therefore, these features are the clock recovery method which is very suitable when the pull-in time of the phase recovery is limited like the TDMA method.

(6) Embodiment FIG. 3 shows the configuration of the Costas loop using this method as an embodiment of the present invention.

In the received IF band signal S, a carrier wave is reproduced in the Costas loop 21, and both I-ch and Q-ch baseband signals S _i and S _q are output.

On the other hand, in the clock component extraction unit 1, the square difference signal C ₁ of the two baseband signals S _i + _q is output, and the two orthogonal reference clocks C ₂ + C ₃ and the correlation unit 15 perform correlation. Is required.

In this embodiment, the correlation value C ₄ + C ₅ is calculated by cyclic addition using the forgetting factor. That is, assuming that the clock component at a certain time kT (T is a sampling period) is C ₁ (k) and the phase of the reference clock is P ₁ (k), the respective correlation values C ₄ (k) and C ₅
(k) is C ₄ (k) = C ₄ (k-1) * β + cos (P ₁ (k)) * C ₁ (k) (5) C ₅ (k) = C ₅ (k-1) * β + sin (P ₁ (k)) * C ₁ (k) (6) However, β is a forgetting coefficient, and is a constant that satisfies 0 <β <1.0 (7).

From the correlation value C ₄ + C ₅ , the phase difference P ₂ is calculated by the equation (4) in the clock phase calculation unit 16, and the sum of the reference value and the reference clock phase P ₁ is used to reproduce the clock phase P ₃ of the received signal. To be done.

The reproduced clock CLK is used in the Costa loop 21. In the synchronous detection unit, data is demodulated from the reproduction clock CLK and the signal S _i + S _q after carrier reproduction.

FIG. 4 and FIG. 5 show the error rate characteristics of the synchronous detection circuit of this embodiment when the static characteristics are obtained. Here, in order to discuss the synchronization pull-in characteristic of the clock recovery circuit, the error rate was measured by transmitting 1000 bursts of 384-bit data with a header by computer simulation.

The transmission rate is 256kbps and the number of samples per bit is 1.
Simulation was performed as 6. The equivalent noise bandwidth of the carrier recovery loop filter was set to 16 kHz. Further, the simulation was carried out in the case where the equivalent noise band width of the loop filter of the conventional clock recovery circuit was 3 kinds of 2k, 4k, and 8kHz, and the forgetting factor of the clock recovery circuit of the present invention was β = 0.995. .

FIG. 4 shows the error rate characteristics when the header is 106 bits. In the conventional method, the case where the equivalent noise bandwidth is 4 kHz has the best characteristics. That is, when the equivalent noise bandwidth is 2 kHz, the synchronization pull-in is slow, and when it is 8 kHz, deterioration due to noise occurs. On the other hand, the method of the present invention has a better characteristic of about 0.5 dB than the case where the equivalent noise bandwidth is 4 kHz in the conventional method.

FIG. 5 shows the error rate when the header is further shortened to 61 bits. In the conventional method, synchronization pull-in cannot be done in time for all three types, and errors that are difficult to reduce occur. On the other hand, although the method of the present invention has a deterioration of about 0.5 dB as compared with the case where the header is 106 bits, the characteristics which are almost the same as the logical value are obtained, and the error which is difficult to reduce unlike the conventional method is not seen.

As described above, it can be seen that the method of the present invention is a reproducing method which is superior to the conventional method in the sync pull-in characteristic and is also strong against the influence of noise.

(7) Effects of the Invention According to the present invention, at the time of GMSK synchronous detection, it is possible to carry out clock phase synchronous pull-in in a short time and realize clock recovery with small phase noise after pull-in.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional system, FIG. 2 is a block diagram of a system of the present invention, FIG. 3 is an embodiment of the present invention, and FIGS. 4 and 5 are error rate characteristics during static characteristics in this embodiment. Is. 1 ... Clock component extraction unit 2 ... VOC 3 ... Phase error detection unit 4 ... Loop filter 11 ... Reference clock generation unit 12 ... Reference clock phase generation unit 13 ... Cosine operation unit 14 ... Sine operation unit 15 ... Correlation unit 16 ... Clock phase difference calculation unit 17 ... Adder 18 ... Cosine operation unit 19 ... Limiter 20 ... Clock output unit 21 ... Costas loop 22 ... π / 2 phase shifter 23 ... Multiplier 24 ... VOC 25 ... LPF 26 ... Loop filter 27 ... Synchronous detection unit 28 ... π / 2 phase shifter 29 ... Multiplier 30 ... Multiplier

Claims (1)

[Claims] 1. When a GMSK-modulated signal is received and a clock is reproduced at the time of synchronous detection using a Costas loop, the clock frequency at the time of transmission is known on the receiving side, and only the phase of the clock is tracked. In the case of regenerating a clock by means of, the means for outputting two reference clocks orthogonal to each other with respect to the clock component extracted from the received signal and the two reference clocks of the clock component obtained from the received signal, Means for sequentially calculating the correlation value of each received input from the start of reception, and means for calculating the phase difference between the clock component and the reference clock from the ratio of the correlation value of And a means for regenerating the clock, and a clock regenerating method characterized in that the synchronization pull-in time of the clock phase regeneration is fast. .