JPH0368231A - Clock regeneration system - Google Patents

Abstract

PURPOSE:To regenerate a clock whose phase synchronism is quickly pulled in and phase noise is small by providing a clock component extracting part, a reference clock generating part, a correlation part, a clock phase difference calculating part, and a clock output. CONSTITUTION:A clock component extracting part 1 calculates a difference signal C1 between squares of I and Q signals Si and Sq after regenerating a carrier wave, and a reference clock generating part 12 outputs two orthogonal reference clocks C2 and C3 by a known clock frequency. Each correlation part 15 calculates correlation values C4 and C5 between the clock component C1 and two reference clocks C2 and C3. A clock phase difference calculating part 16 calculates a phase difference P2 by the operation of a prescribed formula and outputs it to a clock output part 20, and the output part 20 obtains a sum P3 of a reference clock phase P1 and the phase difference P2 to take a cosine component, and thereby, a clock CLK of the reception signal is reproduced and outputted. Thus, the clock phase synchronism is quickly pulled in, and the clock is reproduced with a small phase noise after pulling-in.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Industrial Application Field The present invention relates to wireless communication systems, particularly digital land mobile communication systems.

(2) Conventional Gaussian fi 1tere GMSK (Gaussian fi 1tere)
d Minimurn Shiftkeying) When detecting a modulated signal by the same amount, the ocular transmission is generally reproduced by a Costas loop. At this time, a loop is formed in which clock regeneration is performed by the signal after the sequential liquid feeding section, and the recovered clock is used during sequential wave regeneration.

FIG. 1 shows the configuration of a clock recovery section in a conventional system. After the decoy transmission wave is regenerated, the clock component extraction unit 1 extracts the
・Q From the signals S and ・S of each channel, calculate the square difference signal CI (Sl'-9, 2)9 between both signals. This signal 4
contains a clock component, especially when the transmitted signal is MS'
If it matches the clock exactly.

After that, the phase error detection unit 3 averages the phase of the difference signal C1 of the square of the two Q signals and the phase error E of the clock CLK generated by the VCO 2 in the loop filter 4, and
By generating the control voltage Ve of 2, the clock CL
)(play.

In the conventional method, the synchronization pull-in time for clock phase recovery is determined by the equivalent noise bandwidth B of the loop filter 4;
The larger the value, the faster the pull-in time. However, when B is increased, the phase noise of the reproduced clock also increases due to the influence of noise, etc., and the error rate characteristics deteriorate. Therefore, the optimum setting is made by making a trade-off between the pull-in characteristic and the phase noise characteristic of the clock.

(3) Problems to be Solved by the Invention The conventional system has the disadvantage that in order to reduce the phase noise of the clock, the equivalent noise bandwidth must be reduced and the synchronization pull-in characteristic must be sacrificed to some extent.

However, TDMA (Time Division M
When the synchronization pull-in time for phase recovery is limited as in the case of the multiple access (multiple access) method, it is desirable that the convergence is fast and the phase noise of the recovered clock is small.

In this case, in the conventional method, it is necessary to widen the equivalent noise bandwidth of the loop filter during initial pull-in to speed up pull-in, and after pull-in, it is necessary to narrow the equivalent noise bandwidth to reduce the phase error. Therefore, there are disadvantages in that the hardware scale increases and control of the equivalent noise bandwidth, etc. becomes complicated.

An object of the present invention is to perform clock recovery with fast phase synchronization pull-in and low phase noise.

(4) Means for solving the problem In the present invention, when the clock frequency at the time of transmission is known on the receiving side, two reference clocks having the same frequency and orthogonal are generated, and two reference clocks are generated from the received signal. The correlation value between the extracted clock component and each reference clock is calculated, the phase of the clock is sequentially determined based on the ratio of both correlation values, and the clock is regenerated.

Note that if the frequency of the reference clock generated on the receiving side has a slight error with respect to the clock frequency at the time of transmission, the clock can be recovered by following changes in the phase of the clock that are sequentially calculated.

(5) Function An embodiment of the present invention is shown in FIG. Here, the operation will be explained using this embodiment.

First, in the clock component extraction section 1, from each I-Q signal S, .S, after the transmission wave has been regenerated, the difference signal C, (S, 2-5.2) of the square of both signals is obtained. Calculated.

On the other hand, the reference clock generation H1l outputs two orthogonal reference clocks C2 and C3 using a known clock frequency.

At this time, if the phase of the reference clock is P, then the reference clock C2 is cos(Pt) and the reference clock C3 is 5i
It is represented by n(P+).

The correlation unit 15 uses a clock component C1 and two reference clocks C.
Correlation values C4 and C5 with 2 and C3 are calculated.

At this time, C4=<C4,C09(P,))
(1) C5=<C,,5in(P 1'
)> (2). Here, (·> represents a correlation operation.

The ratio of the magnitudes of the correlation values C4 and C5 is the clock component C
It is a value related to the difference P2 between the clock phase P3 in 4 and the phase P of the reference clock, and P 3"P 1"P 2
(3), P2 is P2=-jan-'(C5/C,)
It is given by (4).

The clock phase difference calculation unit 16 calculates the phase difference P2 by operating equation (4). Next, in the clock output section 20, the sum P3 of the reference clock phase P and the phase difference P2 is
By finding the cosine component, the clock CLK of the received signal can be recovered.

According to this method, the equivalent noise bandwidth is determined by the time length of the data for which the correlation value of equation (IO2) is calculated, and the longer the time length, the narrower the equivalent noise bandwidth and the smaller the phase error.

Moreover, the number of data is 0 at the time of first acquisition, and the number of data increases each time there is received data. It has the characteristics that the bandwidth decreases and the phase error decreases. Therefore, this method is a clock recovery method that is very suitable for cases where the lead-in time for phase recovery is limited, such as in the TDMA method.

(6) Embodiment FIG. 3 shows, as an embodiment of the present invention, a configuration in which this method is used in a Costas loop.

The received IF band signal S is sequentially regenerated in the Costas loop 21, and both I-ch and Q-ch baseband signals S, S9 are output.

On the other hand, the clock component extractor 1 outputs a squared difference signal C7 of the two baseband signals S, S, and the correlation is made in the correlation unit 15 with the two orthogonal reference clocks C2 and C3. Desired.

At this time, the correlation part C1 with the cosine component of the reference clock
, and ゛, the correlation with the sine component 1 straight line C5 is calculated by averaging all the data, moving element 1'-J with a limited number of data, etc.
It can be determined in various ways.

In this embodiment, the correlations fi C4 and C9 are calculated by cyclic addition using a forgetting coefficient. That is, at some point 5IJk
T (T is the sample c, (k) and the phase of the reference clock p, (k), then each correlation [direction C4(k) and C5(k) is
)=C 4(k-1)+β +cos(P+(k))*(,(k) (5)C
s(k)=C s(k-1)*β +sin(P+(k))tc,(k) (6). However, β is the forgetting coefficient, 0 and β<1, 0

This is a constant that satisfies (7).

From this correlation ftm C4 and C5, the phase difference P2 is determined by equation (4) in the clock phase calculation unit 1G, and the clock phase P of the received signal is recovered by taking the sum with the reference clock phase P1. .

The reproduced clock CLK is used in the Costas loop 21. In addition, in the same amount detection section, the reproduced clock CLK,
Signal Sl'S after the sequential liquid feeding section. The data is demodulated from.

FIGS. 4 and 5 show the error propagation properties of the synchronous detection circuit according to this embodiment under static characteristics. Here, in order to discuss the synchronization pull-in characteristics of the tarock reproducing circuit, a burst of 384-bit data with a header attached was transmitted 1,000 times using a computer simulation machine, and the J-rate was calculated.

The simulation was performed with the transmission speed set at 256 kbps and the number of samples per bit set at 16. In addition, the equivalent noise bandwidth of the lube filter for the dish liquid feeding section is 16k.
Hz. In addition, the equivalent noise bandwidth of the loop filter of the conventional clock recovery circuit is 2. 4, 8kH:f
! :), and the forgetting coefficient of the clock recovery circuit according to the present invention is calculated as follows:
, 2/7 rations in rows -] Figure 4 shows the error propagation property when the header is set to 106 pits. In the conventional system, the product and characteristics are good when the equivalent noise bandwidth is set to 4k]42. That is, the equivalent noise bandwidth is 2k
This is because if it is set to 11z, synchronization pull-in will be slow, and if it is set to 8 kHz, deterioration due to noise will occur. In contrast, the method of the present invention reduces the equivalent noise bandwidth to 4kt-1 compared to the conventional method.
Compared to the case where z is used, the characteristics are about 0.5 dB better.

FIG. 5 shows the error rate when the header is distorted and shortened to 61 bits. In all three conventional methods, synchronization cannot be achieved in time, resulting in errors that are difficult to alleviate. on the other hand,
The method of the present invention has approximately 0 bits compared to the case where the header is 106 bits.
. Although there is a 5dB deterioration.

The characteristics were obtained in accordance with the theoretical values, and there was no distortion that was difficult to reduce as in the conventional method.

As described above, it can be seen that the method of the present invention has better synchronization pull-in characteristics than the conventional method, and is also a reproduction method that is resistant to the effects of noise.

(7) Effects of the invention According to the present invention, when detecting GMS K,
Clock phase synchronization can be carried out in a short time, and after clock phase synchronization, clock regeneration with low phase noise can be realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the conventional method, Fig. 2 is a block diagram of the method of the present invention, Fig. 3 is an embodiment of the present invention, and Figs. 4 and 5 are error bearing characteristics during static characteristics in the present embodiment. It is. 1. 2. 3. 4. 11゜12゜13゜14゜15゜16゜Clock component extraction section CO Phase error detection section Loop filter Reference clock generation section Reference clock phase generation section Cosine operation section Sine operation section Correlation section Clock phase difference calculation section 17, , , addition Unit 1 B, , , Cosine operation unit 19°20°21°22°23°24°25°26°27°28°29°30° Limiter Clock output unit Costas loop π/2 phase shifter Multiplier CO PF Loop filter Synchronous detection section π/2 phase shifter multiplier multiplier

Claims (1)

[Claims] When a GMSK modulated signal is received and the clock is recovered using a Costas loop for synchronous detection, the clock frequency at the time of transmission is known on the receiving side, and only the phase of the clock is tracked. When regenerating a clock by: (1) means for calculating a difference signal between the square of the I-ch signal and the square of the Q-ch signal; and (2) two orthogonal standards at a known clock frequency. means for outputting a clock; (3) means for calculating a correlation value between the difference signal in (1) and the two reference clocks in (2); and (4) (1) from the ratio of the correlation values in (3). The difference signal between and (2)
(5) means for regenerating the clock of the received signal from the phase difference in (4) and the reference clock phase in (2); A clock regeneration method characterized by fast speed.