JPH063916B2 - Network node - Google Patents

Description

The present invention relates to a node of a network in which a plurality of terminals are accommodated via a single node, and in particular, the plurality of terminals share a transmission / reception buffer for connection with the network. Regarding network nodes.

[Conventional technology]

FIG. 5 shows the network 10 in which a plurality of terminals are accommodated via the nodes 21, 22, and 23. In the figure, a node 22 accommodates terminals 11, 12, and 13 via subscriber lines 1, 2, and 3, respectively. FIG. 12 shows a conventional example of the configuration of a node of such a network. In the node 22, terminal interface circuits 7, 8 and 9 are provided corresponding to the terminals, and each terminal interface circuit buffers the data transmitted from the terminal and, upon detecting the arrival of the data block, sends a transmission request to the arbiter circuit 35. Send out. Based on these transmission requests, the arbiter circuit 35 specifies the terminal interface circuit to be permitted to transmit, and permits transmission to the data bus 6 using the address bus 16. The terminal interface circuit that has acquired the transmission right sends the transmission data to the transmission buffer circuit 4 via the data bus 6.

Although this conventional example is a case where the bus 6 is used only for transmission to the network, an example in which it is used for transmission and reception is shown in FIG. The arbiter circuit 35 assigns and controls the transmission right including the transmission request from the reception buffer circuit 14. That is, when the reception buffer circuit 14 also receives data from the network 10, it makes a transmission request to the arbiter circuit 35 via the control line 14-1. Based on these transmission requests, the arbiter circuit 35 specifies the terminal interface circuit and the reception buffer circuit 14 that should be permitted to transmit, and permits transmission to the data bus 6 using the address bus 16. The terminal interface circuit or the reception buffer circuit 14 that has acquired the transmission right performs transmission. The terminal interface circuit and the transmission buffer circuit 4 detect the destination address of the transmitted data block on the bus 6 and receive it if it is addressed to itself.

[Problems to be solved by the invention]

In these conventional examples, the arbiter circuit 35 only prevents the contention of the access to the data bus 6, and does not participate in the overflow of the transmission buffer. For overflow of the send buffer, it is possible to prevent buffer overflow by controlling the flow between the send buffer and the terminal interface.
Flow control is generally complicated, and especially when one buffer is shared by multiple terminal interfaces as in this example, the process for flow control becomes more complicated, and the increase in processing time causes a decrease in throughput. Problems arise.

An object of the present invention is to eliminate the above-mentioned problems, to collectively perform access control of a data bus and flow control of a transmission buffer of a node, simplify processing for transmission control, and improve throughput. .

[Means for solving problems]

A network node according to the present invention includes a plurality of terminal interface circuits provided for terminals, a transmission buffer circuit for buffering transmission data from the plurality of terminal interface circuits to the network, and the plurality of terminal interfaces. A bus connecting the circuit and the transmission buffer, and a terminal interface circuit which inputs a transmission request from each of the plurality of terminal interface circuits and permits transmission to the bus, and a buffer of the transmission buffer circuit An arbiter circuit that prohibits transmission permission when the amount of data is a certain amount or more.

The network node of the present invention includes a plurality of terminal interface circuits provided for terminals, a transmission buffer circuit for buffering transmission data from the plurality of terminal interface circuits to the network, and the network to the A reception buffer circuit for buffering received data to a plurality of terminal interface circuits, a bus connecting the plurality of terminal interface circuits to the transmission buffer and the reception buffer circuit, the reception buffer circuit and the plurality of terminals A terminal interface circuit or a reception buffer circuit that inputs a transmission request from each of the interface circuits and permits transmission to the bus is specified, and if the amount of buffer data in the transmission buffer circuit is a certain amount or more, the terminal interface circuit is specified. The circuit that prohibits transmission permission to the circuit Configured to include a capacitor circuit.

Further, the network node of the present invention comprises a plurality of terminal interface circuits provided for terminals, a transmission buffer circuit for buffering transmission data from the plurality of terminal interface circuits to the network, A reception buffer circuit for buffering reception data to the terminal interface circuit, a bus connecting the plurality of terminal interface circuits to the transmission buffer and the reception buffer circuit, a transmission request of the reception buffer circuit, and the plurality of Of the terminal interface circuit from each of the terminal interface circuits and the transmission request of the inter-node communication from each of the plurality of terminal interface circuits, and the terminal interface circuit or the reception for permitting the transmission to the bus. Specifying a buffer circuit and the transmission buffer circuit If the amount of buffer data is equal to or greater than a certain configured to include a arbiter circuit for inhibiting the transmission permission to the terminal interface circuit that performs a transmission request of the communication between nodes.

According to the present invention, the arbiter circuit of the node allocates the transmission right to each terminal or the terminal interface circuit only when the transmission buffer circuit in the node does not overflow. It is to measure

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the first embodiment of the present invention. This figure shows a transmission control part from each terminal to a node, and also has a reception control part, which is not shown.
The difference from the conventional example of FIG. 12 is that the arbiter circuit 5 has a functional configuration and the transmission buffer circuit 4 has a buffer management function.

The transmission data from each terminal is temporarily stored in the buffer of the terminal interface circuit, and in the buffer 25 of the terminal interface circuit 7. The buffer 25 supplies a transmission request to the arbiter circuit 5 via the control line 7-1 when the data is stored. The terminal interface circuits 8 and 9 similarly make transmission requests via the control lines 8-1 and 9-1. The arbiter circuit 5 controls the allocation of the transmission right if the transmission buffer circuit 4 is receivable, and prohibits the allocation if it is not receivable. If receivable, the arbiter circuit 5 sends the transmission address data to the address bus 16. The decoder 24 of the terminal interface circuit 7 decodes this, and if it is its own address, activates the buffer 25 to perform transmission.
When the transmission is completed, the transmission of the transmission request to the arbiter circuit 5 is stopped. If the transmission buffer circuit 4 is ready for reception, the arbiter circuit 5 gives a transmission right to another terminal interface circuit which is making a transmission request. 2 and 3 are block diagrams showing examples of the transmission buffer circuit 4 and the arbiter circuit 5, respectively. In the transmission buffer circuit 4, the write control circuit 43 writes to the buffer memory 41 based on the transmission operation of the terminal interface circuit and increments the up / down counter 44. On the other hand, the read control circuit 42 uses the network 10
Read out from the buffer memory 41 based on the transmission permission signal and decrement the up / down counter 44. Therefore, the up / down counter 44 indicates the amount of data stored in the buffer memory 41. The detection circuit 45 detects when the output value of the up / down counter 44 becomes larger than a preset data amount, and notifies the arbiter circuit 5 of the unreceivability through the control line 4-1. The arbiter circuit 5 sends a transmission request to the control line 7-
It is composed of a read-only memory (ROM) 31, a latch circuit 32, and a gate circuit 30 which receive an address input via 1, 8-1 and 9-1. An arbiter circuit using a ROM and a latch circuit is disclosed in Japanese Patent Application Publication No. 61-308.
38 As described in "Transmission right control device", the arbiter circuit of this figure uses this. The transmission address data latched by the latch circuit 32 (address of the terminal that permits transmission) is supplied to the address input of the ROM 31 and the gate circuit 30. When the gate circuit 30 is notified by the control line 4-1 that the transmission buffer circuit 4 cannot be received, the transmission of the transmission address data to the address bus 16 is prohibited. Therefore, when the transmission buffer circuit is likely to overflow, transmission is prohibited, and the buffer memory 41 does not overflow. Although the threshold value of the detection circuit 45 is set based on the memory amount of the buffer memory 41 and the maximum data block length, the writing from each terminal interface circuit to the transmission buffer circuit 4 is the minimum of the buffer memory. When the measurement is performed in units (for example, 8 bits), the detection circuit 45
Can also control the arbiter circuit 5 based on whether or not there is an empty area in the buffer memory 41.

FIG. 4 is a block diagram of the second embodiment of the present invention. In the first embodiment, transmission control is performed on the terminal interface circuit, whereas in the present embodiment, transmission control is performed directly on the terminal. That is, the transmission control is performed without buffering the transmission data from the terminal in block units in the terminal interface circuit. The functions of the transmission buffer circuit 4 and the arbiter circuit 5 are the same as those used in the first embodiment, and the configuration of the terminal interface circuit and the logical configuration of the subscriber line are different. When the terminal 11 has a data block to be transmitted, the channel 1-1 of the subscriber line 1
To send a transmission request. This request is relayed through the terminal interface circuit 7 and supplied to the arbiter circuit 5.
Transmission requests from the terminals 12 and 13 are handled in the same manner. The decoder 24 decodes the transmission address supplied by the address bus 16 and notifies the terminal 11 of the decoding result, that is, whether transmission is possible or not, using the channel 1-2. If the transmission is possible, the terminal 11 starts transmission using channels 1-3,
The transmission data is sent directly to the data bus 6 via the driver 26. The terminal 11 stops the transmission of the transmission request by using the channel 1-1 at the same time as the end of the transmission. The subscriber line has three channels, but it may be provided with a physical line for each, or as shown in FIG. Good. The figure (a) shows the frame structure of the signal from the terminal to the node, and the figure (b) shows the frame structure of the signal from the node to the terminal. In the figure, F is a synchronization signal for giving the start of the cycle T, XR and XE respectively indicate a transmission request and a transmission permission, and XMT DATA and RCV DATA indicate fields of transmission data and reception data, respectively.

FIG. 7 is a block diagram of the third embodiment of the present invention. This is an embodiment in which each terminal also receives from the network 10 via the data bus 6. In this embodiment, the reception buffer circuit 14 is connected to the data bus 6 and
A transmission request is issued to the arbiter circuit 5 via the control line 14-1. The reception buffer circuit 14 sends the reception data to the data bus 6 when the transmission is permitted. In the terminal interface circuit, for example, the terminal interface circuit 7, the address information of the data block received by the address filter 27 is analyzed, and if it is addressed to itself, it is supplied to the receiving channel 1-4 of the subscriber line 1. FIG. 8 is a block diagram showing an example of the arbiter circuit 5 used in this embodiment. The ROM 31 includes control lines 7-1, 8-1, 9-1 for supplying a transmission request from each terminal, and a control line 4-1 for notifying reception permission from the transmission buffer circuit 4 and the reception buffer circuit 1.
A control line 14-1 which supplies the request for transmission from 4 is connected to its address input. In the ROM 31, the control line 4-
When 1 indicates that reception is not possible, only the transmission request from the control line 14-1 is accepted, and when 1 indicates that reception is possible, the control lines 7-1, 8-1, 9-1 and 14-1. Be programmed to accept all of the. In this case, the control line 4-1 supplies the signal indicating whether the signal is receivable or not in synchronization with the end point of the data block supplied to the data bus 6. That is, even if the empty area of the buffer memory 41 of the transmission buffer circuit 4 becomes equal to or less than the maximum data block length, the reception of the data block in service at that time is recognized. In this embodiment, since the transmission channel and the reception channel are connected via the data bus 6, it is possible to perform the loopback communication within the node.

FIG. 9 is a block diagram of the fourth embodiment of the present invention. In this embodiment, each terminal interface circuit is provided with a transmission buffer 25 and a reception buffer 28. The terminal interface circuit makes a transmission request when data arrives in the buffer 25.

FIG. 10 is a block diagram of the fifth embodiment of the present invention.
In this embodiment, each terminal, for example, the terminal 11, distinguishes between inter-node communication (communication via the network 10) and intra-node communication (communication returning via the data bus 6 without passing through the network 10) to make a transmission request. . In the figure,
The channel 1-1 of the subscriber line 1 reports a transmission request signal for inter-node communication, and the channel 1-1 ″ reports a transmission request signal for intra-node communication. Each terminal interface circuit 7,
8 and 9 correspond to both transmission requests and control 7-1 ', 7-1 ",
These transmission requests are notified to the arbiter circuit 5 by 8-1 ', 8-1 ", 9-1'9-1". FIG. 11 is a block diagram of an example of the arbiter circuit 5 used in this embodiment. This arbiter circuit divides an input transmission request into three groups, that is, a transmission request of the reception buffer circuit 14, a transmission request of inter-node communication and an intra-node communication request, and processes them. It is described in "Consideration of Intra-node Communication Rights Control in 400Mbps Synchronous Packet Loop" by 1978 National Institute of Electronics and Communications, Communication Division National Convention Lecture No. 189, Hasegawa et al. The ROM 34 and the latch circuit 38 perform allocation control of the transmission right between the terminals having the transmission request of the inter-node communication, and the ROM 35 and the latch circuit 39 allocate the transmission right between the terminals having the transmission request of the intra-node communication. It is in control. The address generation circuit (GEN) 54 generates the transmission address of the reception buffer circuit 14, and the address generation circuit (GEN) 55
Generates a dummy address that does not specify any terminal or receive buffer circuit. Therefore, selector 4
0 selects one of a transmission address for a transmission request for intra-node communication, a transmission address for a transmission request for inter-node communication, a transmission address of the reception buffer circuit 14, and a dummy address. This selection control is performed by the inter-group arbiter circuit including the ROM 33 and the latch circuit 37. The address input of the ROM 33 is supplied with the output of the NOR gate 51, that is, a signal indicating whether there is a transmission request for intra-node communication, the output of the AND gate 53, and the transmission request of the reception buffer circuit 14 through the control line 14-1. AND
The output of the NOR gate 52, that is, a signal indicating the presence / absence of a transmission request for inter-node communication is supplied to the gate 53. Even if a transmission request is made, it is not accepted due to the inhibition control of the AND gate 53. With this prohibition control, when the transmission buffer circuit 4 is in the receivable state, the one to which the transmission right is given is specified from all the transmission requests, but in the receivable state, the reception buffer circuit 14 and the intra-node communication are specified. The transmission request is specified from among the transmission requests of.

〔The invention's effect〕

According to the present invention, the transmission to the data bus in the node is controlled without overflow of the transmission buffer to the network, so that flow control between the node and the terminal interface circuit or the terminal is not required. Therefore, there is an effect that the transmission control is simplified and the throughput can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
1 is a block diagram showing an example of the transmission buffer circuit of FIG. 1, FIG. 3 is a block diagram showing an example of the arbiter circuit of FIG. 1, and FIG. 4 is a block diagram showing a second embodiment of the present invention. FIG. 5 is a block diagram of a network using the present invention, FIG. 6 is a frame configuration diagram showing an example of a configuration of a subscriber line, FIG. 7 is a block diagram showing a third embodiment of the present invention,
8 is a block diagram showing another example of the arbiter circuit, FIG. 9 is a block diagram showing a fourth embodiment of the present invention, and FIG.
FIG. 11 is a block diagram showing a fifth embodiment of the present invention, FIG. 11 is a block diagram showing still another example of an arbiter circuit, and FIG.
2 and 13 are block diagrams showing a conventional example. In the figure, 1, 2, 3 ... Subscriber line, 4 ... Transmission buffer circuit, 5 ... Arbiter circuit, 6, 16 ... Bus, 7, 8, 9
… Subscriber interface circuit, 10… Network, 1
1, 12, 13 ... Terminal, 14 ... Reception buffer circuit, 2
1, 22, 23 ... Node, 24 ... Decoder, 25, 2
8, 41 are buffers, 26 ... Drivers, 27 ... Address filters, 31, 33, 34, 35 ... ROM, 32, 3
7, 38, 39 ... Latch circuit, 30, 51, 52, 53
... gate, 40 ... selector, 42 ... readout control circuit,
43 ... Write control circuit, 44 ... Counter, 45 ... Detection circuit, 54, 55 ... Address generating circuit.

Claims (6)

[Claims] 1. A network node connected to a network and accommodating a plurality of terminals, comprising: a plurality of terminal interface circuits provided corresponding to the terminals; and data transmitted from the plurality of terminal interface circuits to the network. A transmission buffer circuit that outputs a reception disable signal when the up / down counter indicating the amount of stored data that has been buffered exceeds a preset value; and a bus that connects this transmission buffer circuit and the plurality of terminal interface circuits.
When a transmission request from each of the plurality of terminal interface circuits is input and a terminal interface circuit that permits transmission to the bus is specified, the transmission buffer circuit outputs to the bus when the reception disable signal is output. A network node including an arbiter circuit for prohibiting transmission permission. 2. The terminal interface circuit makes a transmission request to the arbiter circuit based on a transmission request signal from the terminal, and sends a transmission permission signal to the terminal when the transmission is permitted from the arbiter circuit. The network node according to claim 1. 3. A network node connected to a network and accommodating a plurality of terminals, comprising: a plurality of terminal interface circuits provided corresponding to the terminals; and data transmitted from the plurality of terminal interface circuits to the network. A transmission buffer circuit that outputs a reception disable signal when an up / down counter that indicates the amount of stored data and that exceeds a preset value, and a reception buffer circuit that buffers the reception data from the network to the plurality of terminal interface circuits A bus connecting the reception buffer circuit, the transmission buffer circuit and the plurality of terminal interface circuits, and a transmission request from each of the reception buffer circuit and the plurality of terminal interface circuits is input to the bus. The terminal interface circuit or reception bag that permits transmission. Network node comprising a arbitration circuit for inhibiting the transmission permission to the terminal interface circuit when the unreceivable signal from said transmission buffer circuit is outputted together with specifying the § circuit. 4. The terminal interface circuit makes a transmission request to the arbiter circuit based on a transmission request signal from the terminal and sends a transmission permission signal to the terminal when the transmission is permitted from the arbiter circuit. The network node according to claim 3. 5. A network node connected to a network and accommodating a plurality of terminals, comprising: a plurality of terminal interface circuits provided corresponding to the terminals; and data transmitted from the plurality of terminal interface circuits to the network. A transmission buffer circuit that outputs a reception disable signal when an up / down counter that indicates the amount of stored data and that exceeds a preset value, and a reception buffer circuit that buffers the reception data from the network to the plurality of terminal interface circuits A bus connecting the reception buffer circuit, the transmission buffer circuit, and the plurality of terminal interface circuits, a transmission request of the reception buffer circuit, and a transmission request of intra-node communication from each of the plurality of terminal interface circuits And from each of the plurality of terminal interface circuits. Input request for inter-node communication and specify a terminal interface circuit or a reception buffer circuit that permits transmission to the bus, and a transmission request for inter-node communication when the reception disable signal is output from the transmission buffer circuit An arbiter circuit for prohibiting transmission permission to the terminal interface circuit performing the network node. 6. The terminal interface circuit makes a transmission request for intra-node communication and inter-node communication to the arbiter circuit based on a transmission request signal for intra-node communication and a transmission request for inter-node communication from the terminal. The network node according to claim 5, wherein a transmission permission signal is sent to the terminal when the transmission is permitted.