JPH064055A - Display data transmitter - Google Patents

Abstract

(57) [Summary] [Configuration] Display data 1 after P / S conversion of the display data input from the display memory 5 in the PC main body 1.
0b and the dot clock 12 generated by the display control means 4
EC that outputs and at least as an ECL signal level signal
The liquid crystal display device 2 is provided with the L interface output means 6.
At, the EC for inputting the ECL signal level data transmitted from the personal computer body 1 and outputting it to the liquid crystal control means 8
The L interface input means 7 is provided. [Effect] By transmitting an ECL signal level signal between the personal computer body and the liquid crystal display device, good display quality can be maintained without increasing the number of transmission lines between the personal computer body and the liquid crystal display device, such as 10 m and 80 MHz. It becomes possible to transmit high-speed display data over a long distance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display data transmission device suitable for transmitting high-speed display data for personal computers, workstations and the like.

[0002]

2. Description of the Related Art Conventionally, display data has been transmitted from a personal computer body to a liquid crystal display device as a TTL signal level signal. However, in recent years, as the resolution of liquid crystal display devices has increased, the amount of display data to be transmitted from the personal computer body to the liquid crystal display device in one frame has increased. It is necessary to increase or increase the dot rate for transmitting display data.

For example, if the display color of the liquid crystal display device is 260,000, the number of transmission lines of the display data output from the personal computer to the liquid crystal display device is 18 (6 for each of R, G and B), which is the resolution. , Horizontal 1280 dots, vertical 102
In the case of a liquid crystal display device having four lines and a frame frequency of 60 Hz, the transmission rate of display data is about 80 Mbps. The transmission rate of the display data can be obtained by the following formula, and the above 80 Mbps is calculated by the blanking period being "0".

Transmission rate of display data = (resolution + X) ×
Frame frequency (X: retrace line period) Therefore, as a method of slowing down the transmission speed, the display data read from the display memory that conventionally stores the display data in the personal computer body is converted into parallel / serial data (hereafter
By transmitting what was transmitted to the liquid crystal display device through P / S conversion) to the liquid crystal display device as it is without P / S conversion, the dot rate of the display data is transmitted as a TTL signal level signal. A method of transmitting at a possible rate is possible. However, this will increase the number of transmission lines due to the low dot rate, so the diameter of the cable between the PC main body and the liquid crystal display device will be thick, and the appearance will be spoiled.
Problems such as difficult wiring will occur.

On the other hand, as a means for transmitting at a low dot rate and without increasing the number of transmission lines, for example, as disclosed in Japanese Patent Laid-Open No. 3-5790,
An apparatus has been proposed in which the display data to be displayed in frames are not all transmitted in one frame but are sequentially extracted at a fixed number of display dots and transmitted. In this device, for example, when every four dots are sequentially extracted and transmitted, the transmission rate of the display data is ¼ of that of all the display data transmitted in one frame, and the time for four frames is reduced. The display data for one frame is transmitted by calling. As a result, the dot rate of 80 Mbps can be transmitted even at the TTL signal level without increasing the number of transmission lines.
The dot rate is ps.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the conventional technique described in Japanese Patent Publication No. 0, the change in the display screen is small, or the change interval of the display screen is longer than the time in which the display data is sequentially extracted and transmitted and the display data for one frame is completed. Has no problem in display quality.

However, since the display data amount less than the display data amount to be originally transmitted is transmitted in one frame, in the case of a scrolling display in which the display screen changes at any time, the display data of adjacent dots is displayed. Has a time lag of one frame or more, and adjacent dots display different frames of data, which disturbs the display screen. For example, even in one character font, there is a problem that the data before and after the screen change coexist, which makes it difficult to distinguish characters.

Further, the transmission of the TTL signal level is not suitable for long-distance transmission because it is easily affected by the attenuation and noise in the transmission line. For example, if the personal computer main body and the liquid crystal display device are separated by 10 m or more. It cannot be used for purposes such as use.

The object of the present invention is also to achieve long-distance transmission.
It is an object of the present invention to provide a display data transmission device capable of maintaining good display quality without having to increase the number of transmission lines.

[0010]

According to the present invention, in a display data transmitting apparatus for transmitting at least display data from an information processing apparatus main body to a display apparatus, at least display data among data transmitted by the information processing apparatus main body to the display apparatus. And the dot clock are transmitted as signals at the ECL signal level.

More specifically, in a personal computer main body having at least a processing means, a display control means and a display memory, a display after P / S conversion of the display data from the display memory among the data transmitted to the liquid crystal display device. At least EC for the data and the dot clock generated by the display control means
ECL interface output means for outputting an L signal level signal is provided, and further, in a liquid crystal display device having a liquid crystal control means and a liquid crystal module, ECL signal level data transmitted from a personal computer main body is input and output to the liquid crystal control means. The ECL interface input means is provided.

[0012]

The operation of the typical structure of the present invention is as follows. The processing means writes the data to be displayed on the liquid crystal display device in the display memory according to the processing result. The display control means sequentially outputs a read control signal and the like to read the display data from the display memory, and also generates a display control signal and the like such as a display synchronization signal. The ECL interface output means P / S-converts at least the display data read from the display memory by the display control means, and further E-converts at least the P / S-converted display data and the dot clock.
The signal at the CL signal level is transmitted to the liquid crystal display device. E
The CL interface input means inputs the display data of the ECL signal level transmitted from the personal computer body and outputs it to the liquid crystal control means. The liquid crystal control means displays the input display data on the liquid crystal module.

As a result, even in long-distance transmission, it is possible to perform display data transmission which can maintain good display quality without increasing the number of transmission lines.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In the following examples, attention is paid to the fact that the ECL signal level signal is strong against power supply noise and is suitable for high-speed, long-distance transmission, and at least the transmission speed of the data output from the personal computer to the liquid crystal display device is high. The display data and the dot clock are transmitted by the ECL signal level signal.

FIG. 1 shows the configuration of a data transmission device according to the present invention. In the figure, 1 is a personal computer main body, and 2 is a liquid crystal display device. The personal computer main body 1 comprises a processing means 3, a display control means 4, a display memory 5 and an ECL interface output means 6. The liquid crystal display device 2 is composed of an ECL interface input means 7, a liquid crystal control means 8 and a liquid crystal module 9.

Next, the operation of this embodiment will be described.

First, the operation inside the personal computer body 1 will be described. The processing means 3 updates the contents (display data 10) of the display memory 5 as necessary according to the processing result.
The display control means 4 generates a display control signal 11 including a horizontal synchronization signal, a vertical synchronization signal, a display timing signal, a backlight control signal, and a dot clock 12, and outputs the dot clock 12 to the ECL interface output means 6 and the display memory 5 as well. An address of the display data 10 to be read out and a read-out control signal 13 for reading out the display data 10 are generated and sequentially output to the display memory 5.
The ECL interface output means 6 receives the display data 10 from the display memory 5 and the display control signal 11 and the dot clock 12 from the display control means 4. Of these signals and data, the display data 10 is P / S converted to reduce the number of data lines, and the P / S converted display data 10 and the dot clock 12 are converted from TTL signal level signals to ECL signal level signals. Signal of
It is transmitted to the liquid crystal display device 2.

Next, the operation of the liquid crystal display device 2 will be described. Display data 1 transmitted from the PC body 1
0b, display control signal 11, dot clock 12b are EC
It is input to the L interface input means 7. The ECL interface input means 7 receives the input display data 10
b, the display control signal 11, and the dot clock 12b,
The display data 10b and the dot clock 12b, which are ECL signal level signals, are S / P converted to reduce the speed, and are also converted to TTL signal level signals and output to the liquid crystal control means 8 for signals other than the ECL signal level. (TT
The display control signal 11 which is an L signal level signal) is directly output to the liquid crystal control means 8. The liquid crystal control means 8 drives the liquid crystal module 9 according to the input display data 10d, the display control signal 11, and the dot clock 12d.
As described above, according to the present invention, the display data 10 and the dot clock 12 having a high transmission speed are transmitted at a high speed and with an ECL signal level signal suitable for long-distance transmission. Because you can
Maintaining good display quality without increasing the number of transmission lines
It is possible to transmit a distance of 10 to 10 m from m to 20 m. Further, in the present embodiment, the display control signal 11 whose transmission speed is not high is transmitted by the signal of the TTL signal level, but the display control signal 11 may be converted into the signal of the ECL signal level and transmitted.

Next, the ECL interface output means 6
Will be described more specifically. 2 is the same as that of FIG.
It is the first embodiment of the present invention showing in detail an example of the internal configuration of the L interface output means 6. The ECL interface output means 6 is composed of a selector circuit 15, a counter circuit 16 and an ECL conversion means 17. In this embodiment, for the sake of concrete description, the display color of the liquid crystal display device 2 is about 260,000 colors (specifically, 262144 colors), and the resolution is 12 horizontal.
80 dots, 1024 vertical lines, 60 frame frequency
Assume that it is Hz. In order to display 260,000 display colors in the liquid crystal display device 2, an information amount of 18 bits is required for each dot (2 18 = 262144). That is, the brightness of each of the three pixels of red, green, and blue forming one dot is represented by 6 bits. The display memory 5 stores the display state of one screen of the display screen of the liquid crystal display device 2.

As described with reference to FIG. 1, the processing means 3
The display control means 4 updates and reads the display data 10 stored in the display memory 5. The reading of the display memory 5 performed by the display control means 4 is sequentially read so as to scan from the upper left of the display screen of the liquid crystal display device 2 to the right direction, and the display data for 8 dots is read by one reading. . As described above, since 1 dot is expressed by 18 bits, the display data 10 of 144 bits is read by one reading. The display data 10 read from the display memory 5 is input to the selector circuit 15 in the ECL interface output means 6. In addition to the process of reading the display data from the display memory 5, the display control unit 4 is synchronized with the display control signal 11 and the signal of reading the display data from the display memory 5, and has a cycle of 1/8 of the cycle of reading. The dot clock 12 that is the clock of The dot clock 12 generated by the display control means 4 is the counter circuit 1 in the ECL interface output means 6.
6 is input. The counter circuit 16 is a 3-bit counter, counts the input dot clock 12,
Count value 1 that represents the number from 0 to 7 with 3 bits
4 is output to the selector circuit 15. That is, the counter circuit 16 has the same period as the period for reading the display data,
A value of 0 to 7 is sequentially output as the count value 14. The selector circuit 15 is a selector that selects 1 dot data from the input 8 dot data, and 1 dot from the input 144-bit display data 10 according to the value of the count value 14 input from the counter circuit 16. 18-bit minute data is selected, and ECL conversion means 17 is selected.
Output to. That is, using the selector circuit 15 and the counter circuit 16, the 8-dot width display data 10 is P / S converted into the 1-dot width display data 10a. Then, the ECL conversion means 17 inputs the display data 10a and the dot clock 12 output by the display control means 4, converts the signal levels of these signals from the TTL signal level to the ECL signal level, and outputs them to the liquid crystal display device 2. .

Next, the operation of the ECL interface output means 6 characteristic of the present invention will be described with reference to the timing chart of FIG. In order to make the explanation easy to understand, of the 144-bit-width display data 10 read out from the display memory 5 in one read operation, only the 8-bit width is shown. The operation of the ECL interface output means 6 will be described below with reference to FIG. 3 while referring to FIG.

In FIG. 3, 100, 101, 102, 10
Reference numerals 3, 104, 105, 106, and 107 are display data for 8 bits in the display data 10 having 144 bits in width read from the display memory 5. The display data 100 at the first reading is 1 of the display screen of the liquid crystal display device 2.
It is the least significant bit data of the 6-bit width data expressing the brightness of the red pixel of the upper left dot. Similarly to the display data 100, the display data 101 to the display data 107 represent the least significant bit of the 6-bit width data representing the brightness of one pixel, and the display position is the display data 101. Display data 1 is data of the red pixel of the dot on the right of the data 100.
02 is the data of the red pixel of the dot on the right of the display data 100, and the display data 103 and the display data 10
4, the display data 105, the display data 106, and the display data 107 are data of 3 dots, 4 dots, 5 dots, 6 dots, and 7 dots right of the display data 100, respectively. Further, each display data in the second and subsequent readings is the data of the dot 8 dots to the right of the previous reading position. However, when this read position reaches the right end, the dot at the left end of the line one below becomes the read position, and this is repeated to read the display data for one screen.

The display control means 4 has a read cycle of 1 time, and the display memory 5 has a cycle of 100 ns (dot rate is 10 Mbps) and the display data 10 (8 in FIG. 3) of 8 dots of the display screen of the liquid crystal display device 2. The display data 107) is read from the display data 100. Counter circuit 16
Is 12.5n which is a cycle of 1/8 of the display data 10.
The dot clock 12 of s cycle (speed is 80 MHz) is input. The counter circuit 16 counts the dot clock 12 and outputs the count value 14 to the selector circuit 15. The selector circuit 15 inputs the display data 100, 1 according to the count value 14 from the counter circuit 16.
01, 102, 103, 104, 105, 106, 10
Select one from 7 and use ECL as display data 10a
It outputs to the conversion means 17. For example, when the count value 14 is “0”, the display data 100 is displayed, when the count value 14 is “1”, the display data 101 is displayed, and the count value 14 is displayed.
When is "2", the display data 102 is output to the ECL conversion means 17, respectively. At this time, the cycle of the display data is equal to the cycle of the dot clock 12 and is 12.5 ns.

As described above, according to the present invention, the dot rate of the display data to be transmitted can be increased. Further, the selector circuit 1 constituting the ECL interface output means 6
5, the counter circuit 16 and the ECL conversion means 17 can be easily realized, and the selector circuit 15 and the counter circuit 16 can be realized by a TTL IC which is a general-purpose IC, and the ECL conversion means 17 can be, for example, a Motorola MC10H351. Well, there is no problem in feasibility.

Further, the ECL interface output means 6
In this case, since the display data 10 is subjected to P / S conversion and conversion to the ECL signal level, the display control signal 11 output without doing anything is the propagation delay amount of the selector circuit 15 and the ECL conversion means 17. Minute timing is different. Further, even among the display data 10b subjected to the same processing, the timing is different due to the variation of the propagation delay amount of the selector circuit 15 and the like. Therefore, the ECL interface output means 6 may output the display data 10b and the display control signal 11 to the liquid crystal display device 2 after synchronizing them one or more times before outputting them to the liquid crystal display device 2.
Further, when the transmission distance between the personal computer body 1 and the liquid crystal display device 2 becomes longer, the variation in the propagation delay amount in the transmission between the respective pieces of display data 10b to be transmitted and the respective display control signals 11 becomes large, so that the liquid crystal In the ECL interface input means 7 in the display device 2, the display data 10b and the display control signal 11 which are similarly input may be synchronized. By performing such synchronization, it is possible to eliminate the variation in the amount of propagation delay in the transmission path, so that the transmission path between the personal computer body 1 and the liquid crystal display device 2 can be made longer. The dot clock 12 can be used as a synchronization clock signal for performing synchronization.

Further, the ECL interface output means 6
In the above, the dot clock 12 generated by the display control means 4 is used as the dot clock, but a clock output from a crystal oscillator or the like may be used as the dot clock 12. An embodiment in this case will be described with reference to FIG.

In FIG. 4, 1, 2, 3, 5, 15, 16, 1
7 is the same as the element shown in FIG. 2 and is given the same number. In this embodiment, 24 is a display control means, 21
Is an oscillator such as a crystal oscillator. The ECL interface output means 6 is slightly different in configuration and operation from the embodiment described with reference to FIG. ECL interface output means 6
In addition to the selector circuit 15, the counter circuit 16 and the ECL conversion means 17, the dot clock generation means 20 is provided.
In the processing means 3 and the display control means 24 of this embodiment,
The operation of updating and reading the display data 10 stored in the display memory 5 is no different from that of the above-mentioned embodiment. However, in the above-described embodiment, the dot clock 12 is generated by the liquid crystal display device 24, but in this embodiment, the dot clock 12 is generated in the ECL interface output means 6.

The oscillator 21 uses the dot clock generating means 2 in the ECL interface output means 6 to generate a clock 22 at a speed N times faster than the dot clock 12 (N is an integer of 1 or more).
Output to 0. The dot clock generation means 20 generates the dot clock 12 from the input clock 22 and outputs it to the counter circuit 16 and the ECL conversion means 17, and
A clock 23 which is a basis of a read signal of the display memory 5, a display control signal 11 and the like generated in the liquid crystal display device 24.
Is generated and output to the liquid crystal display device 24. Since the liquid crystal display device 24 generates the read signal of the display memory 5, the display control signal 11 and the like based on the clock 23 input from the dot clock generating means 20, the display data 10 and the display control signal 11 read from the display memory are generated. Is dot clock 12
It becomes the signal of the timing synchronized with. In addition, a series of the P / S conversion of the display data 10 input from the display memory 5 in the counter circuit 16, the selector circuit 15, and the ECL conversion means 17, and further conversion into ECL signal level signals for transmission to the liquid crystal display device 2. The operation is the same as in the above embodiment. As described above, the present invention can be implemented by using the clock output from the crystal oscillator or the like as the dot clock 12.

Further, in the above embodiments, the display data 1
After 0 is P / S converted, the TTL signal level signal is converted to the ECL signal level signal. However, since the dot clock 12 and the clock 22 have a short cycle, the display data 10 read from the display memory 5 is displayed. May be converted from the TTL signal level signal to the ECL signal level signal, and then the display data 10 may be P / S converted using the selector circuit 15 and the counter circuit 16. In this case, the counter circuit 16 and the selector Like the ECL conversion means 17, the circuit 15 and the dot clock generation means 20 can be easily realized by using a general-purpose IC such as 10K series. Further, the ECL interface output means 6 and the ECL interface input means 7 are, for example, HG2 manufactured by Hitachi Ltd.
It may be realized by using an LSI having a mixed TTL / ECL interface, such as the 1T series, or G
An IC or LSI using an aAs element may be used.

There are items such as the number of gates, the number of input / output pins, and the allowable power consumption as items to be examined when the LSI is formed by using the gate array method. From these factors, the ECL interface output means 6 and the ECL interface input means are included. 7 may not be realized by one package of LSI, but may be realized by a plurality of packages. An embodiment at this time will be described with reference to the drawings. FIG. 5 is a block diagram of a third embodiment of the data transmission apparatus according to the present invention, showing an embodiment in which the ECL interface output means 6 and the ECL interface input means 7 are realized by three LSIs. In this embodiment, 1, 2, 3, 4, 5, 8,
9 is the same as the embodiment described with reference to FIG. 1, and is given the same number. Reference numerals 61, 62 and 63 are characteristic E of this embodiment.
CL interface output means, 71, 72, 7
Reference numeral 3 is an ECL interface input means characteristic of this embodiment. In this embodiment, the operations of the processing unit 3, the display control unit 4, and the display memory 5 are exactly the same as those of the embodiment described with reference to FIG. In this embodiment, the display data 10 having a 144-bit width read from the display memory 5 is converted into display data 111 for red pixels, display data 112 for green pixels, and display data 113 for blue pixels.
Of 48 bits each. Then, the display data 111, the display data 112, and the display data 113 are input to the ECL interface output means 61, the ECL interface output means 62, and the ECL interface output means 63, respectively. The dot clock 12 output by the display control means 4 is the ECL interface output means 6
1, the ECL interface output means 62, the ECL interface output means 63, and the display control signal 1
1 is input only to the ECL interface output means 63. ECL interface output means 61, ECL
The interface output unit 62 and the ECL interface output unit 63 are the same as the ECL interface output unit 6 described with reference to FIGS. 1 and 2 only in that the bit width of the input / output display data is 1/3. The configuration is the same and the operation is the same. The ECL interface output means 63 uses the dot clock 12 to P / S-convert the input display data 113 having a width of 48 bits into display data 113b having a width of 1/8 and 6 bits. Further, the display data 113 after P / S conversion and the ECL signal level signal of the dot clock 12 are converted, and the display data 113 and the display control signal 11 are synchronized. The display data 113b and the display control signal 1 which have been subjected to the above processing
1. The dot clock 12b is output to the liquid crystal display device 2. ECL interface output means 61 and ECL
The interface output means 62 does not synchronize the display control signal 11 because it does not input or output the display control signal 11, but otherwise performs the same operation as the ECL interface output means 61. ECL interface input means 7
1, the ECL interface input means 72 and the ECL interface input means 73 only have a bit width of 1/3 of the display data to be input / output, and the ECL interface input means 7 described with reference to FIGS.
It has the same configuration as the above and operates in the same way. ECL
The interface input unit 73 synchronizes the display data 113b and the display control signal 11 input from the ECL interface output unit 63 by using the dot clock 12b, and further, the display data 113b and the dot clock 12 are synchronized.
Is converted from an ECL signal level signal into a TTL signal level signal and output to the liquid crystal module 9. The ECL interface input means 71 and the ECL interface input means 72 do not synchronize the display control signal 11 because they do not receive the display control signal 11, but otherwise perform the same processing as the ECL interface input means 73. In this way, it is easy to realize the ECL interface output means 6 and the ECL interface input means 7 with a plurality of packaged LSIs.

Further, in the present embodiment, since the display data synchronized by the ECL interface input means and the dot clock used as the synchronization clock are outputted from the same ECL interface output means, the time point at which they are outputted from the ECL interface output means The display data in and the dot clock are synchronized. Therefore, when the display data and the dot clock are transmitted from the personal computer body 1 to the liquid crystal display device 2, variations in the propagation delay amount in the transmission path are reduced by E.
There is an effect that the timing margin at the time of synchronization by the CL interface input means can be increased.

Further, unless a circuit for inputting / outputting and synchronizing the display control signal 11 of the LSI developed for the ECL interface output means 63 is used, the ECL interface output means 61 and the ECL interface output means 62 are used as the ECL interface output means. 63
Since it is possible to use an LSI developed for use in
The development man-hours and development costs required to develop one LSI can be realized by the development man-hours and development costs required to develop one LSI. Therefore, there is also an effect that the unit price of one LSI can be reduced. Similarly, since the ECL interface input means 71 and the ECL interface input means 72 can use the LSI developed for the ECL interface input means 73, the same effect can be obtained.

In the above-described embodiment, the timing margin when synchronizing the propagation delay variation in the transmission line when the display data and the dot clock are transmitted from the personal computer body 1 to the liquid crystal display device 2 by the ECL interface input means is large. Therefore, the dot clock 12b is output from each of the plurality of ECL interface output means, and the dot clock 12 is output to the transmission path between the personal computer body 1 and the liquid crystal display device 2.
b is transmitted, but only one of the dot clocks 12b output by the plurality of ECL interface output means is transmitted through the transmission path between the personal computer body 1 and the liquid crystal display device 2, and the transmitted one dot clock is transmitted. 12b may be input to all of the plurality of ECL interface input means in the liquid crystal display device 2. In this case, there is an effect that the number of transmission lines in the transmission line between the personal computer body 1 and the liquid crystal display device 2 can be reduced.

In this embodiment, the ECL interface output means 6 and the ECL interface input means 7 are also provided.
Are each composed of three LSIs, and the data of the red, blue, or green pixel is respectively allocated as the display data 10 to be input to one LSI, but the present invention is not limited to this, and for example, Two LS
The display data 10 may be composed of I or four LSIs, and the display data 10 to be input to each LSI does not need to be pixel data of a single color.

Further, as the liquid crystal display device 2, in the display data transmission device to which the liquid crystal display device 2 capable of displaying a gray scale of 6 bits or less (64 gray scales) in monochrome can be connected, the ECL interface described in the above embodiment is used. This can be realized by using the output means 63 and the ECL interface input means 73 one by one, and there is also an effect that there is no need to newly develop a monochrome liquid crystal display device.

Next, another example of realizing the ECL interface output means 6 in the present invention will be described with reference to FIG. FIG. 12 is a block diagram of a fourth embodiment of the data transmission device according to the present invention. This embodiment has almost the same configuration as that of FIG. 2, but the ECL interface output means 6 includes a selector circuit 15, a counter circuit 16, and an ECL conversion means 1.
7, a palette 41 which is controlled by the processing means 3 and holds data of colors to be displayed, and a display data generating means 4
It consists of 0. The display memory 5 of the above-described embodiments stores data of each pixel of the display screen of the liquid crystal display device 2 as "1" or "0". On the other hand, in this embodiment, the palette number of each dot on the display screen of the liquid crystal display device 2 is stored. The display data generation means 40 reads the palette No. from the display memory 5 and refers to the palette 41 to recognize the color to be displayed at each pixel of the display screen of the liquid crystal display device 2, and to display it as the display data 10 in the selector circuit 15. Output. The subsequent operation is the same as that of the embodiment described with reference to FIG. 2, and the description is omitted.

Further, the personal computer body 1 and the liquid crystal display device 2
There are the following methods as a method of reducing the number of signal lines transmitted through a transmission line that connects the two, and will be described with reference to two drawings. FIG. 6 is a block diagram of a fifth embodiment of the data transmission apparatus according to the present invention, and FIG. 7 is a timing chart of the personal computer main body 1 in the present embodiment. 6 and 7, the same elements as those in FIG. 2 or 3 are designated by the same reference numerals, and the description of the operation thereof will be omitted. In FIG. 7, as in FIG. 3,
The display data for the 8-bit width of the display data 10 having the 144-bit width read from the display memory 5 is disclosed. In the present embodiment, the display control signal 11 is a horizontal synchronizing signal 241 which becomes “H” during the horizontal blanking period, a vertical synchronizing signal 242 which becomes “H” during the vertical blanking period, and the display data 10.
Means four signals, a display timing signal 243 which becomes “H” when outputting the data to be displayed on the display screen and a backlight control signal 244 which becomes “H” when the backlight of the liquid crystal module 9 is turned on. To do. The ECL interface output means 6 is, in addition to the counter circuit 16, the selector circuit 15, and the ECL conversion means 17, a selector circuit which generates a display control signal 11a in which one signal is selected from the display control signals 11 consisting of four input signals. 18 and the P / S converted display data 10a and the display control signal 11a are constituted by the reference signal generating means 19 for generating the reference signal 25 for making the liquid crystal display device 2 reproducible. The selector circuit 18 inputs the count value 14 output from the counter circuit 16 and the display control signal 11 including four signal lines output from the display control means 4, and when the count value 14 of 0 to 7 is 0 to 3 , Selects one signal line from the input display control signals 11 and outputs it to the ECL conversion means 17.

In the specific operation example shown in FIG. 7, when the count value 14 is 0, the horizontal synchronizing signal 241 is set, when the count value 14 is 1, the vertical synchronizing signal 242 is set, and when the count value 14 is 2, the display timing signal 24 is set.
When 3 is 3, the backlight control signal 244 is selected and output to the ECL conversion means 17 as the display control signal 11a. The count value 14 is 4 to 7
In the case of, "L" is output. The reference signal generation means 19 inputs the count value 14 from the counter circuit 16, generates a signal which becomes “H” when the input count value 14 is 0, and E
It outputs to the CL conversion means 17. That is, the reference signal 25
Indicates the timing of transmitting the horizontal synchronizing signal 241 by the display control signal 11b. ECL conversion means 17
Converts the input display data 10a, the reference signal 25, and the display control signal 11a into ECL signal level signals.
Display data 10b of signal of L signal level, reference signal 25
b, the display control signal 11b is output to the liquid crystal display device 2.
ECL interface input means 7 in the liquid crystal display device 2
Then, by converting the display data 10b of the ECL signal level signal, the reference signal 25b, and the display control signal 11b into a signal of the TTL signal level, and using the reference signal 25, the display control signal 11a is changed to the horizontal synchronization signal 241 and the vertical synchronization signal 241. Since the synchronizing signal 242, the display timing signal 243, and the backlight control signal 244 can be reproduced, the control signal required by the liquid crystal control means 8 can be generated. As described above, since four display control signals 11b, which are required in this embodiment, can be realized by one signal line, the number of signal lines in the transmission line connecting the personal computer body 1 and the liquid crystal display device 2 can be reduced.

When the count value 14 input to the selector circuit 18 of this embodiment is 0 to 3, the display control signal 11 to the horizontal synchronizing signal 241, the vertical synchronizing signal 242, the display timing signal 243, and the backlight control signal 24 are displayed.
One of the four is selected and output to the ECL conversion means 17, but the present invention is not limited to this. For example, when the count value 14 is 0 or 1, the horizontal synchronizing signal 241 is
The vertical synchronization signal 242 may be selected at 2 or 3, the display timing signal 243 at 4 or 5, and the backlight control signal 244 at 6 or 7, respectively. Further, the reference signal 25 is changed to the display control signal 11b.
In the above description, the signal is set to "H" while the horizontal synchronizing signal 241 is being transmitted, but the signal is not limited to this. further,
An example of the case where the horizontal synchronization signal 241, the vertical synchronization signal 242, the display timing signal 243, and the backlight control signal 244 are output from the display control means 4 as the display control signal 11 has been shown, but the present invention is not limited to this.
Other signals may be used, and any number of signals may be transmitted by one signal line.

Further, in this embodiment, the reference signal 25 is newly generated in order to reproduce the display control signal 11b in which a plurality of signals are converted into one signal, but the present invention is not limited to this. For example, one of the plurality of display control signals 11 such as the horizontal synchronization signal 241 is set to the display control signal 1
1b is transmitted as it is, and the count value 14 of the counter circuit 16 is cleared (set to 0) by the horizontal synchronization signal 241.
Even in this case, each signal can be reproduced from the display control signal 11b in the ECL interface input means 7 of the liquid crystal display device 2. In this case, the reference signal generation means 19 becomes unnecessary.

In the embodiment described above, in order to convert the ECL signal level signal and the TTL signal level signal as described above, the general-purpose IC 10KH series (for example, MC10H124 and MC1 manufactured by Motorola Co., Ltd.) is used.
0H350, MC10H125, MC10H351) and LSI equipped with TTL / ECL mixed interface
This can be easily realized by using (for example, HG21T series manufactured by Hitachi, Ltd.). Below, these IC and LS
An example of the method of using the present invention using I will be described. Normal,
The ECL element connects a positive power supply voltage (hereinafter referred to as VCC) to the ground, and a negative power supply voltage (hereinafter referred to as VEE) is -5V.
To supply. As a result, the voltage level of “H”: about −
0.9V, "L" voltage level: ECL of about -1.8V
It was possible to output a signal of a signal level (hereinafter, this usage method is usually referred to as ECL usage method). However, in this usage method, in addition to the + 5V power supply for the TTL signal level,
It is necessary to supply two power supplies, a -5V power supply. Therefore, if you want to use only a single + 5V power supply, add + to VCC.
By supplying 5V and connecting VEE to ground,
A signal having a signal level of "H" voltage level: about 4.1 V and "L" voltage level: about 3.2 V may be output (hereinafter, this usage method is referred to as a pseudo ECL usage method. Is referred to as a pseudo ECL signal level). In the display data transmission device of the present invention, either the normal ECL usage method or the pseudo ECL usage method described above may be used. In addition, these ICs and LSIs express one signal by two signal lines, and when one of the two signal lines is "H", the other one is a differential signal. Input and output. Therefore, the personal computer body 1 and the liquid crystal display device 2
A differential signal having an ECL signal level or a pseudo ECL signal level is transmitted on the transmission path between them. However, in the present invention, it is not always necessary to transmit one signal as a signal of the ECL signal level to be transmitted by a differential signal expressed by two signals, and one of the two differential signals output by the IC or LSI is used. Only books may be transmitted.

Further, paying attention to the fact that the ECL signal level signal is a differential signal, the following system is proposed as a system for reducing the speed of the dot clock 12 to be transmitted by half. This method will be described with reference to the drawings. FIG. 8 is a sixth embodiment of the data transmission apparatus according to the present invention, and FIG. 9 is a timing chart of the main part thereof. In FIG.
The elements described in FIG. 2 are given the same numbers. In this embodiment, the ECL interface output means 6 characteristic of this embodiment includes a selector circuit 15 and a counter circuit 1.
6. In addition to the ECL conversion means 17, a liquid crystal display device 26 that doubles the cycle of the dot clock 12 is used. In this embodiment, the display data 1 read from the display memory 5
The operation of converting 0 to P / S, converting it to an ECL signal level signal, and transmitting it to the liquid crystal display device 2 is the same as that of the above-described embodiment, and the description thereof is omitted. However, the display control means 4
The dot clock 12 output by the
Is not directly input to the frequency division circuit 26 but is input to the frequency dividing circuit 26. The frequency dividing circuit 26 divides the frequency of the input dot clock 12, doubles the cycle, and outputs it to the ECL conversion means 17. The ECL conversion means 17 inputs the dot clock 27 having a doubled cycle, converts the dot clock 27 into an ECL signal level signal 27 b, and outputs the signal 27 b to the liquid crystal display device 2. ECL conversion means 17
The dot clock 27b whose period is doubled at the level of the ECL signal output by is the two differential signals, that is, the clock 270 and the clock 271, and these two clocks have opposite polarities. In this way, the ECL interface input means 7 in the liquid crystal display device 2 receives the clock 270, the clock 271, and the display data 10b, which are shown in FIG. Then, when synchronizing the variation in the propagation delay amount in the transmission path between the personal computer body 1 and the liquid crystal display device 2 between the display data 10b, the display data 10b is synchronized using the rising edges of the clock 270 and the clock 271. To do.
Specifically, as shown in FIG. 9, in the display data 10b, the n + 2m (m is an integer of 0 or more) -th data is clocked by the clock 270 and the n + 2m + 1 (m is an integer of 0 or more) -th clocked by the clock 271. Synchronize with. As described above, in this embodiment, the period of the dot clock 12 can be doubled, that is, the transmission speed can be halved. For this reason,
Data can be transmitted even when the dot clock transmission speed is higher than the transmission limit speed when transmitting data.

Next, a structural example of the liquid crystal display device 2 according to the present invention is shown in FIG. In FIG. 10, FIG. 1 and FIG.
The same elements as those shown in are given the same numbers. Two
Reference numeral 8 denotes a keyboard device, which is not described in the above embodiments, but the keyboard device 28 is not directly connected to the personal computer body 1 but is connected to the personal computer body 1 via the liquid crystal display device 2. There is. 29 is a power circuit, 30
Is an AC socket, 31 is a connection display LED that lights up when the liquid crystal display device 2 is connected to the personal computer body 1, 33 is a display interface board, 34 is a contrast volume, and 35 is a dimming volume. Reference numeral 32 denotes an LCM substrate, which has the liquid crystal control means 8 and the liquid crystal module 9 shown in FIG. The liquid crystal display device 2 includes the display data 111b, the display data 112b,
In addition to the display data 113b, the dot clock 12b, and the display control signal 11, an LEDON signal 36 for instructing lighting of the connection display LED 31, key switch pressing data on the keyboard device 28, key data 3 such as a key scanning clock.
Enter 8. The key data 38 is not input to the ECL interface input means 71 or the like, and is input / output as it is. Hitachi's HG21TS20 is used for the ECL interface input means 71, the ECL interface input means 72, and the ECL interface input means 73. The power supply circuit 29 obtains power from the AC socket 30 and supplies power (5V, 12V, 24V) to the liquid crystal display device 2. The LEDON signal 36 is input to the ECL interface input means 71 and outputs the LOW level to turn on the connection display LED 31. The cable connecting the personal computer body 1 and the liquid crystal display device 2 is not particularly limited, and any cable may be used, but it is resistant to noise and the diameter of the cable is large even for transmission of about 10 m. Is a multi-pair cable with a shield that shields several pairs of cables and is suitable for differential signal transmission without causing problems such as wiring routing (for example, Hitachi Cable's small diameter MA cable: UL2990-SB (MA)). ) Is used.

In the embodiment described above, the liquid crystal display device 2
The display color is approximately 260,000 colors (specifically 262144 colors), the resolution is 1280 dots horizontally, 1024 lines vertically, and the frame frequency is 60 Hz. However, the display color is not limited to this. Any color, resolution, frame frequency, etc. may be used. Further, the data of 8 dots on the display screen is read from the display memory at one time, but the present invention is not limited to this. Further, the ECL interface output means 6 performs P / S conversion on the number of signal lines of the display data 10 read from the display memory 5 to 1/8, but the present invention is not limited to this. The display color of the liquid crystal display device 2 is 4096 colors, the resolution is 1120 dots in the horizontal direction, 780 lines in the vertical direction, the frame frequency is 80 Hz, the number of dots of the display screen of the display data 10 read at once from the display memory is 4, and the ECL interface output means. The P / S conversion in 6 may be one-third. At this time, since the display color of the liquid crystal display device 2 is 4096 colors, the number of bits required to express one dot is 12 bits (2
The 12th power is 4096). This means that the brightness of each pixel of red, blue, and green is represented by 4 bits. Further, since the data of 4 dots is read from the display memory 5 at a time, the bit width of the display data read from the display memory 5 at one time is 48 bits (4 × 12 = 48).

At this time, the personal computer body 1 according to the present invention
FIG. 11 shows an example of interface specifications between the liquid crystal display device 2 and the liquid crystal display device 2. Here, the one corresponding to the embodiment of FIG. 5 is shown. In this example, the ECL interface output means is realized by using three LSIs, and each of the three LSIs is referred to as LSI0, LSI1, LSI2. In FIG. 11, A1 to A68 represent signal lines between the main body of the personal computer and the liquid crystal display device in this embodiment, and there are 68 signal lines. A
DCK0 and SC transmitted using signal lines 1 to A16
K0, DT01 to DCK06 are signals output from LSI0, and are all signals of pseudo ECL signal level,
Each signal carries that signal using two wire pairs. Among these, DCK0 is the dot clock 12b, SCK0 is the reference signal 25b, and DT01 to D
T06 is the display data 111b. Similarly, DCK1 and SCK transmitted using the signal lines A17 to A32
1, DT11 to DCK16 are signals output from the LSI 1 and all are signals of pseudo ECL signal level, and each signal transmits the signal using two pair lines.
Of these, DCK1 is the dot clock 12b, and S
CK1 is the reference signal 25b, and DT11 to DT16
Is the display data 112b. Similarly, A33 to A4
DCK2, SCK2, D transmitted using the signal line of 6
T21 to DCK25 are signals output from the LSI 2 and are all signals of pseudo ECL signal level, and each signal transmits the signal using two pair lines. Of these, DCK2 is the dot clock 12b, and SCK2
Is a reference signal 25b, DT21 to DT24 are display data 113b, and DT25 is a display control signal 11b.
Is. Display data DT01 to DT06, display data DT11 to DT16, display data DT21 to DT2
4. The display control signal DT25 is a signal obtained by P / S converting 3-bit width data into 1-bit width in each LSI, and the three signals before P / S conversion are the left of each signal in FIG. It was shown to. For example, the display data DT01 is B0
Three signals of 0, B10 and B20 are P / S in one signal.
It has been converted, and the display data DT02 is B30, B0.
The three signals 1, 1 and B11 are P / S converted into one signal, and the display control signal DT25 is HSY, VSY, DS.
Three P signals are P / S converted into one signal.
In names such as "B00", the left character indicates the color of the pixel of the data, blue for "B", green for "G",
When “R”, it means red, the number in the center means the bit number from the lower bit of the 4-bit width data expressing the brightness, and the number on the right shows the display memory 5 once. It means the number of dots from the left of the display data of 4 dots read out. For example, "B10"
Is a blue pixel, which is the second bit from the lower bit of the 4-bit width data expressing the brightness, and the first dot from the left of the display data of 4 dots read at once from the display memory 5. It means that it is data. In the signals before P / S conversion of the display control signal DT25, "HSY" is the horizontal synchronizing signal 241, "VSY" is the vertical synchronizing signal 242, and "DSP" is the display timing signal 243. Then, the SCK1 signal, SCK1
Signal, SCK1 signal is D which is P / S converted from 3 signals
The T01 signal, DT02 signal, DT25 signal, etc.
"B00", "B30", "H" shown on the left of each signal
It is a signal that becomes "H" when transmitting "SY" or the like.

In this example, the signals transmitted from the personal computer body 1 to the liquid crystal display device 2 are the LSIs 1 and L.
In addition to the signals transmitted by SI2 and LSI3, the following signals are also transmitted. TSSD transmitted using signal line A47
The signal and the TSRD signal transmitted using the signal line A49 are
Although not particularly described in the above-mentioned embodiments, the signal for controlling the brightness of the backlight of the liquid crystal module 9 performed by the liquid crystal control means 8 is a signal, and the TSSD signal is for writing.
The TSRD signal is serial data for reading. The KBDT signal transmitted using the signal line A53 is the keyboard device 28 connected to the liquid crystal display device 2 shown in FIG.
The KBCLK signal which is keyboard data which is the result of the key scanning and is transmitted using the signal line A51 is a clock signal for keyboard data transmission. Also, the signal line A5
5VKB and 1 transmitted using A57 and A59
The 2VKB signal line is a signal line for the + 5V power source for the keyboard device 28 and a signal line for the + 12V power source. The PSWON signal transmitted using the signal line A61 is connected to the switch attached to the liquid crystal display device 2, and the power supply of the personal computer body 1 and the liquid crystal display device 2 is controlled by this signal.
The LEDON signal transmitted using the signal line A63 is as shown in FIG.
This signal is a signal indicating that the connection display LED 31 indicated by 0 is turned on. The TDON signal transmitted using the signal line A65 is a signal for controlling ON / OFF of the liquid crystal module 9.
The signal ground is the signal lines A48, A50, A
52, A54, A56, A58, A60, A62, A6
4, A66, A67, A68. In addition, T
SSD signal, TSRD signal, KBCLK signal, KBDT
The signal, the PSWON signal, the LEDON signal, and the TDON signal are all signals at the TTL signal level.

Although the reference signal 25 (SCK1 signal or the like) is transmitted from all three LSIs, the present invention is not limited to this, and it may be transmitted from only one LSI.

In the above-mentioned embodiments, the description has been given by taking the form in which the personal computer main body and the liquid crystal display device are connected as an example, but the present invention is not limited to this, and instead of the personal computer main body, the workstation main body and other information. A processing device may be used, and instead of the liquid crystal display device, a plasma display device or C
Any display device such as an RT display device may be used.

[0049]

According to the present invention, good display quality can be maintained and long-distance, high-speed display data of 10 m, 80 MHz can be transmitted without increasing the number of transmission lines between the personal computer body and the liquid crystal display device. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transmission device according to the present invention.

FIG. 2 is a block diagram of a first embodiment of a data transmission device.

FIG. 3 is a timing chart of the personal computer body in the first embodiment.

FIG. 4 is a block diagram of a second embodiment of the data transmission device.

FIG. 5 is a block diagram of a third embodiment of a data transmission device.

FIG. 6 is a block diagram of a fifth embodiment of a data transmission device.

7 is a timing chart of the personal computer body in the embodiment of FIG.

FIG. 8 is a block diagram of a sixth embodiment of a data transmission device.

9 is a timing chart of the embodiment of FIG.

10 is a block diagram of an example of a liquid crystal display device corresponding to the embodiment of FIG.

FIG. 11 is an explanatory diagram of an example of interface specifications according to the present invention.

FIG. 12 is a block diagram of a fourth embodiment of a data transmission device.

[Explanation of symbols]

1 ... PC main body, 2 ... Liquid crystal display device, 3 ... Processing means,
4 ... Display control means, 5 ... Display memory 5, 6 ... ECL interface output means, 7 ... ECL interface input means 7, 8 ... Liquid crystal control means, 9 ... Liquid crystal module, 1
5 ... Selector circuit, 16 ... Counter circuit, 17 ... ECL
Conversion means, 19 ... reference signal generation means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhisa Nishimoto 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock company Hitachi Image Information Systems (72) Inventor Tetsuya Suzuki 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Inside the Hitachi Image Information System (72) Inventor Hiroaki Shirane 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock Company Inside the Hitachi Image Information System (72) Takahiro Kawai 1070 Ichige, Katsuta-shi, Hitachi Hitachi Factory Mito Factory

Claims (10)

[Claims] 1. A display data transmission device for transmitting at least display data from an information processing device body to a display device, comprising:
A display data transmission device, characterized in that at least display data and a dot clock are transmitted by signals of an ECL signal level. 2. The information processing apparatus main body comprises at least TT
An ECL interface output unit for converting an L signal level signal into an ECL signal level signal is provided, and at least an ECL signal level signal can be input to the display device.
The display data transmission device according to claim 1, further comprising CL interface input means. 3. The at least one of the ECL interface output means and the ECL interface input means is an integrated circuit.
Display data transmission device described. 4. The ECL interface output means is integrated with display data generation means for converting information represented by color numbers into color information and palette means for storing color information. The display data transmission device according to claim 3. 5. A display data and a dot clock are transmitted from each of a plurality of integrated ECL interface output means, and the ECL interface input means uses the same display data as a clock for synchronizing the display data. 4. The display data transmission device according to claim 3, wherein the dot clock transmitted by the ECL interface output means is used. 6. The ECL interface output means is provided with means for time-sharing a plurality of display control signals out of data transmitted from the information processing apparatus main body to the display device, converting the signals into one signal, and transmitting the signal. The display data transmission device according to claim 2, wherein 7. The ECL interface output means is provided with means for generating a reference signal for reproducing the display control signal, which has become a single signal by time-sharing a plurality of display control signals, in the display device. 7. The display data transmission device according to claim 6, wherein: 8. The ECL interface output means doubles a cycle of a dot clock to be transmitted and transmits two signals having a phase difference of 180 degrees as a dot clock. Display data transmission device. 9. The display data transmission device according to claim 1, wherein a shielded multi-pair cable is used as a cable for connecting the information processing device body and the display device. 10. An information processing device, which is connected to a display device by a cable and transmits at least display data to the display device via the cable, the data being transmitted by the information processing device to the display device. An information processing apparatus comprising: an ECL interface output means for converting at least a TTL signal level signal into an ECL signal level signal, and outputting an ECL signal level signal as the display data to the cable.