JPH0640657B2 - Optical scanning device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an optical scanning device used in a laser printer, a laser fax, or the like.

(Prior Art) An optical scanning device scans a surface to be scanned with a light beam,
It is known as a device for writing optical information.

In such an optical scanning device, the light beam is usually deflected at a constant angular velocity by a rotary deflector such as a polygon mirror or a holographic scanner, and in order to keep the scanning speed constant on the surface to be scanned, Uses an fθ lens. However, since the fθ lens is a special lens and has a high cost, there is also a desire to avoid using it if possible. Recently, polygon mirrors in which the scanning angular velocity of the light beam is not constant are being proposed (Japanese Patent Application No.
-274324), in such a case, even if the fθ lens is used, the scanning speed is not constant, so that the fθ lens cannot be used in such a case.

The image scanning clock is a clock signal for turning on / off the scanning light beam during optical scanning, and its frequency _k
Is given by 1 / T where T is the time allotted to writing information for one pixel. If the fθ lens is not used, the scanning speed of the surface to be scanned by the scanning light beam will not be constant. Therefore, if the image scanning clock frequency _k is kept constant, information writing will be distorted.

For example, in FIG. 4, reference numeral 30 is a photoconductive photosensitive member as a scanning object, reference numeral 32 is a polygon mirror for deflecting the light beam L at a constant angular velocity, and reference numeral 34 is the light beam L. 3 shows a condenser lens for focusing on the scan plane.
The light beam L is generally laser light from a gas laser or a semiconductor laser. If the distances and h are selected as shown in FIG. 4, h = .tan θ Letting the angular velocity of the polygon mirror 32 be ω _o (constant), the angular velocity of the scanning light beam (Constant) scan speed Is Becomes Assuming that the scanning area length is 2H and H + h = h ', Is. Assuming that there are _2no pixels in the scan area length 2H, the scan speed Vn at the nth pixel counted from the scan start side on the left side of the scan area in FIG. Is. Here, d is one pixel width. From the definition, the frequency _{k of the} image scanning clock is Vn / d in this case, Becomes Therefore, if the image scanning clock frequency _k is changed for each pixel according to the equation (1), optical scanning can be realized without causing distortion in writing of information without using the fθ lens. In this case, the frequency (timing) of the frequency of the image scanning clock is generally counted from the count value by starting the clock counting based on the synchronization signal from the optical sensor 36 placed on the scanning surface or at a position equivalent thereto. It has gained.

However, in the above-mentioned post-objective type (a type in which a converging lens is arranged before the rotary deflector) optical scanning device, when there is an error in the arrangement of the rotary deflector, the optical axis position, and the arrangement of the optical sensor, the image scanning clock The frequency correction characteristic and the actual scanning speed change characteristic are deviated, and the linearity and the magnification error are deteriorated, and the image quality is deteriorated. The linearity referred to here is, for example, the variation in pitch between lines when straight lines are drawn at equal intervals.

(Object) It is an object of the present invention to provide an optical scanning device capable of improving deterioration of image quality due to a deviation between a frequency correction characteristic of an image scanning clock and a scanning speed change characteristic.

(Structure) The present invention is an optical scanning device for continuously changing the frequency of an image scanning clock according to the scanning speed of a rotary deflector after a predetermined time has elapsed from a synchronization signal from an optical sensor, and means for varying the predetermined time. By this means, it is possible to improve the image quality by eliminating the deviation between the frequency correction characteristic of the image scanning clock and the scanning speed change characteristic.

Next, examples of the present invention will be described.

In this embodiment, in the above-described optical scanning device, the time until the frequency change of the image scanning clock starts can be changed by the synchronizing signal from the optical sensor. The image scanning clock generator in this embodiment includes an oscillator, a first frequency divider, an up / down counter, a control circuit,
It consists of a phase locked loop circuit. The phase locked loop circuit will be abbreviated as PPL hereinafter.

The oscillator generates a reference clock. The frequency of this reference clock is hereinafter referred to as _o . Of course, _o is a constant.

The first frequency divider divides the reference clock to generate a position control clock.

An up / down counter (hereinafter abbreviated as U / D counter) switches the frequency division ratio N of the first frequency divider.
N is, of course, a natural number.

The control circuit has the following functions. The scanning area is divided into K-side blocks BLi (i = 1 to K) in advance, and a predetermined finite sequence Mi (i = 1 to 1) is defined.
K), i-th block BLi (i = 1 to K)
Then, the U / D counter is driven for each Mi pulse of the position control clock to realize the stepwise switching of the frequency division ratio N in the entire scanning region. That is, if the initial value of the frequency division ratio N is No, the frequency of the position control block is initially _o / No, but if the first block BL1 counts this position control block by M1 pulses, the control is performed. The circuit switches the frequency division ratio of the first frequency divider from No to N ₁ (= No + ΔN) via the U / D counter. Then, the frequency of the position control clock is _o / N
Becomes ₁ . This new frequency clock is M1 pulse,
When counting, the frequency division ratio is further switched from N ₁ to N ₂ .
This is repeated n1 times. Next, the second block
In BL ₂ , switching of the frequency division ratio is repeated n2 times for each M2 pulse of the position control block. This process is performed for each block. In the i-th block BLi,
The frequency division ratio is switched ni times for each Mi pulse of the position control clock.

The PLL circuit is a phase detection circuit, a low pass filter, a second
It is composed of a frequency divider and a voltage controlled oscillator. The second frequency divider has a fixedly set frequency division ratio M.

This PLL circuit generates an image scanning clock whose frequency continuously changes according to the stepwise change of the frequency of the position control clock.

The image scanning clock generator will be described below with reference to the drawings.

In FIG. 2, the phase detection circuit 18 and the low-pass filter
20, the voltage-controlled oscillator 22, and the second sentence divider 24 form a PLL circuit.

The reference clock of frequency _o generated from the oscillator 10 is _divided by the first frequency divider 12 to generate the frequency _o / N.
Of the control circuit 16 and PL
Input to the phase detection circuit 18 of the L circuit.

The phase detection circuit 18 uses the position control clock and the frequency divider.
The phase of the clock CLA input from 24 is compared, and the phase difference is output to the low-pass filter 20 as a pulse signal. When the phase difference information is input to the voltage controlled oscillator 22 via the low pass filter 20, the oscillator 22 outputs a clock having a frequency according to the output voltage of the low pass filter 20. This clock becomes the image scanning clock.
The image scanning clock is divided by the frequency divider 24, and the clock CL
It is applied to the phase detection circuit 18 as A and compared in phase with the position control clock.

Now, in the PLL circuit, the frequency of the clock generated from the voltage controlled oscillator 22 does not change when there is no change in the phase difference between the clock CLA whose phase is compared in the phase detection circuit 18 and the position control clock. Such a state
This is called the balanced state of the PLL circuit.

For example, if the frequency of the position control clock is _o / N when the PLL circuit is in a balanced state, then at this time the clock CLA
Since the frequency of is also _o / N, f _k of the clock generated from the voltage controlled oscillator 22 in this state is Is. In this state, if the frequency division ratio of the frequency divider 12 is switched from N to N ', the frequency of the position control clock will be Therefore, a phase difference occurs with the clock CLA. Therefore, according to this, but also changes the frequency _k of the output clock of the voltage controlled oscillator 22, a change in the frequency _k is generated continuously, the frequency _k is From Changes continuously and monotonously.

Therefore, the frequency _{k of the} image scanning clock can be continuously changed by changing the frequency _dividing ratio N of the frequency divider 12 stepwise.

Now, the control circuit 16 uses the clock CK for outputting the preset value of the frequency division ratio in the frequency divider 12 from the U / D counter 14, the signal EN for enabling the U / D counter 14, and the up / down mode. Signal U / D that determines

In the up-down mode, the signal U / D is generated so as to switch from the up mode (or down mode) to the down mode (or up mode) near the extreme value of the scanning speed.

When the clock CK is input, the U / D counter 14 updates the preset value and switches the frequency division ratio of the frequency divider 12.

The clock CK is generated by each block BL as described above.
For each i (i = 1 to K), a finite sequence Mi (i = 1 to K)
It is carried out based on. That is, for each block,
Mi and ni are preset and the i-th block
In BLi, the clock CK is generated from the control circuit 16 every time the position control clock is input as Mi pulses, and this clock CK is generated ni times in this block BLi.

The number of blocks K and the values of Mi and ni are determined by the voltage controlled oscillator 22.
The frequency _{k of the} image scanning clock generated from the above is set so as to closely approximate the frequency change due to the change in scanning speed, for example, the expression (1). This is experimentally or theoretically determined according to design conditions.

Figure 4 shows by switching the frequency division ratio with a change in image scanning clock f _k of the ideal on (curve 4-1), an example of a step-like change of the clock f _'k. The numbers 5, 6, 10 and 16 under the stepwise frequency change are the scanning start side on the right single side of the figure.
It corresponds to M1, M2, M3 and M4 respectively. As can be seen from the figure, n1 = 6, n2 = 9, n3 = 3, n4 = 5. This figure shows only the right half of the symmetrical figure, M5 = 10, n5 =
3, M6 = 6, n6 = 9, M7 = 5, n7 = 6. As can be seen from this figure, the block BLi is a region in which a continuous curve of the frequency _k is linearly approximated, and the widths of steps are equal in each block. Clock f _'k corresponds to M times the position control clock. The clock f ′ _k itself changes stepwise, but the frequency of the actual image scanning clock changes continuously due to the action of the PLL circuit, and the curve 4-
1 is approximated well.

FIG. 2 shows a schematic timing diagram of the device shown in FIG. In order from the top, the synchronization signal, the scanning speed, the division ratio N,
The frequency _o / N of the position control clock and the frequency _{k of the} image scanning clock are shown. Since the up / down mode of the U / D counter 14 is switched in the vicinity of the extreme value of the scanning speed, both the frequency division ratios N, _o / N, fk are symmetrical with respect to the position in the vicinity of the extreme value.

The sync signal is the output of the photosensor indicated by reference numeral 36 in FIG. 3, and the first frequency divider 12 is initialized by this sync signal. The synchronization signal is also applied to the control circuit 16.

The signal EN causes the counter operation to be performed with a delay of a predetermined time Ta after receiving the synchronization signal, and to end the counter operation with a delay of Tb time after the scanning of the print area. When the counter operation is completed, the frequency division ratio N is fixed to the initial value.

As a specific example, for the rotation angle α, the deflector 2θ is A special polygon mirror as given in (Japanese Patent Application No. 59-2
A concrete example in which the one proposed in No. 74324, A and R are constants in the form of polygon) is used will be described. The change in the frequency _k (n) of the image scanning clock when using this polygon is as shown by the curve 4-1 in FIG. In this case, the frequency division ratio M of the third frequency device is 8, the frequency _o of the reference clock is 20 MHz, the switching width ΔN of the frequency division ratio N is 1, the number of pixels in the scanning region is 2n ry2400, and the element of the finite sequence m Number 7,
M1 = 5, M2 = 6, M3 = 10, M4 = 16, M5 = 10, M7 = 5
n1 = 6, n2 = 9, n3 = 3, n4 = 5, n5 = 3, n6 = 9,
When carried out with n7 = 6, a good recorded image having no discontinuity and almost no distortion was obtained. The division ratio N is
Both ends of the scanning area are 69 and the central portion 89. The variation between pixels was 2% or less.

The switch 40 is for selecting the frequency correction characteristic of the image scanning clock, and more specifically, for selecting the stepped wave indicating the frequency division ratio change of the frequency divider 12. This step wave changes the frequency of the image scanning clock according to the scanning speed of the light beam, and is generated after a predetermined time Ta from the synchronization signal from the optical sensor 36 and ends after Tc time.
The a and Tc times are switched by the switch 40. The light modulating means modulates the light beam L by an image signal input from an external device in synchronization with the image scanning clock to form an image on the photoconductor 30, and the image forming period is the step wave generation period. It is inside. The step wave is generated when the U / D counter 14 counts by the enable signal EN from the control circuit 16 and the frequency division ratio of the frequency divider 12 changes, and the control circuit 16 causes the counter 41 as shown in FIG. Also, the logic circuit 42 generates an enable signal EN, and other signals CK and U / D are generated in accordance with the enable signal EN. The counter 41 is initialized by the synchronization signal from the optical sensor 36 and counts the position control pulse from the frequency divider 12. The logic circuit 42 generates the enable signal EN until the content of the count 41 reaches the first value, and the first value and the second value are switched by the switch 40.
The timing of generation of the enable signal EN changes as shown in FIG. Here, the variable range t of the enable signal EN is t = (n−1) × Δt. Here, n is the number of enable signals EN that can be switched by the switch 40, and Δt is the time corresponding to M × Δn dots when the frequency division ratio of the frequency divider 24 is M. For example, M =
8, Δn = 2, n = 3, t = 8 × 2 × (3-
1) = 32 dots. 5 and 6 are timing charts of this embodiment.

Deflection angle 2θ FIG. 9 shows an optical system in another embodiment of the present invention using a polygon mirror 45 (disclosed in Japanese Patent Application No. 59-274324) 45 having a curvature in the scanning direction given by the above. Here, α is a rotation angle, A is a circle tangent circle radius, and R is a reflection surface curvature.
The light beam from the light source 43 enters the photoconductor 30 and the optical sensor 36 via the imaging lens 34, the mirror 44, and the polygon mirror 45. In this embodiment, the parts other than the optical system are the same as those in the above embodiment, and the frequency K (n) of the image scanning clock is used.
Changes in the tenth curve 9-1. In this case, the frequency division ratio of the frequency divider 24 is 8 and the frequency division number _o of the reference clock is 20 MH.
Switching width of Z and division ratio N ΔN = 1, number of pixels in scanning area 2n ₀ =
1968, the number of elements in the finite sequence m is 7, M1 = 2, M2 = 3, M3 =
6, M4 = 16, M5 = 6, M6 = 3, M7 = 2, n1 = 8, n2 = 1
Assuming that 9, n3 = 5, n4 = 3, n5 = 5, n6 = 19, n7 = 8, linearity (actual pitch change rate of vertical line of 12,7mm pitch in the figure) is shown in FIG. Gives a good image of ± 1%.

However, in FIG. 9, when the incident position on the polygon mirror 45 is 0.6 mm and the optical sensor 36 is displaced by 1 mm from the design, a deviation occurs between the actual scanning speed and the image scanning clock frequency correction characteristic, and its linearity is It deteriorates as shown in Fig. 12 and exceeds ± 1% at the edge of the image.

Therefore, if the switch 40 delays the start of the image scanning clock frequency correction by Δn = 2, that is, Δn × M = 16 dots, the linearity is improved as shown in FIG. 13 and is ± 1%.
It becomes the following. The image scanning clock frequency correction characteristic is selected by measuring and setting the deviation from the ideal characteristic of the synchronizing signal of the optical scanning device to the writing start time and the scanning speed characteristic (factory setting).

(Effect) As described above, according to the present invention, the frequency correction characteristic of the image scanning clock can be selected, so that the deterioration of the image quality due to the deviation between the frequency correction characteristic of the image scanning clock and the scanning speed change characteristic can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image scanning clock generator in an embodiment of the present invention, FIG. 2 is a timing chart of the same embodiment, and FIG. 3 is a plan view showing an example of an optical system in an optical scanning device. FIG. 4 is a characteristic diagram of the above embodiment, FIGS. 5 and 6 are timing charts of the above embodiment, FIG. 7 is a diagram for explaining the above embodiment, and FIG. 8 is a part of the above embodiment. FIG. 9 is a block diagram showing the same, FIG. 9 is a plan view showing an optical system in another embodiment of the present invention, FIG. 10 is a characteristic diagram of the same embodiment, and FIGS. 11 to 13 are diagrams for explaining the linearity of the same embodiment. FIG. 40 …… Switch, 41 …… Counter, 42 …… Logic circuit.

Claims (1)

[Claims] 1. A light beam from a light source is imaged as a minute spot on a surface of a photoconductor by a focusing lens and is scanned by a rotary deflector, and the focusing lens is arranged between the rotary deflector and the light source. Light that continuously changes the frequency of the image scanning clock in accordance with the scanning speed of the rotary deflector after a predetermined time has elapsed from the synchronization signal from the optical sensor that detects the scanning light beam in the scanning area outside the photoconductor area. An optical scanning device, comprising: a scanning device having means for varying the predetermined time.