JPH0642373Y2 - Ceramic multilayer board - Google Patents
Ceramic multilayer boardInfo
- Publication number
- JPH0642373Y2 JPH0642373Y2 JP15943188U JP15943188U JPH0642373Y2 JP H0642373 Y2 JPH0642373 Y2 JP H0642373Y2 JP 15943188 U JP15943188 U JP 15943188U JP 15943188 U JP15943188 U JP 15943188U JP H0642373 Y2 JPH0642373 Y2 JP H0642373Y2
- Authority
- JP
- Japan
- Prior art keywords
- green sheet
- land
- metal pin
- ceramic multilayer
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Combinations Of Printed Boards (AREA)
Description
【考案の詳細な説明】 〔概要〕 セラミック多層基板において、特に各層間のvia接続部
の導通性確保に関し、 via接続部の導通性を種々のずれ要素に対し確保し、且
つ抵抗値の増大を防ぐことを目的とし、 グリーンシートに導体パターンを形成し、viaに導体ペ
ーストを充填して端部にランドを設けものを複数層積層
するセラミック多層基板において、各層のグリーンシー
トの各via接続部毎に、その全長にわたってメタルピン
を一直線上に挿入装置するように構成する。[Detailed Description of the Invention] [Outline] In a ceramic multilayer substrate, with respect to ensuring conductivity of via connection portions between layers, in particular, ensure conductivity of via connection portions with respect to various shift elements and increase resistance. For the purpose of prevention, in a ceramic multilayer substrate in which a conductor pattern is formed on a green sheet, a via is filled with a conductor paste, and a land is provided at the end to laminate multiple layers, each via connection part of the green sheet of each layer In addition, the metal pin is configured to be inserted in a straight line over its entire length.
本考案は、セラミック多層基板において、特に各層間の
via接続部の導通性確保に関する。The present invention relates to a ceramic multi-layer substrate, especially between each layer.
Concerning the continuity of via connection.
近年、プリント配線板の高密度、高速、小型化等の要求
に対し高多層化が考えられ、これをセラミック基板にお
いて実現しようとする動きが盛んである。このセラミッ
ク基板の多層化方法の1つとして、アルミナグリーンシ
ートを用い、このグリーンシートに導体パターンを印刷
したものをviaで層間導通しながら多層に積層し、焼成
して一体化するグリーンシート多層法がある。In recent years, in order to meet the demands for high density, high speed, miniaturization, etc. of printed wiring boards, it has been considered to increase the number of layers, and there are active movements to realize this in a ceramic substrate. As one of the multilayer methods for this ceramic substrate, a green sheet multilayer method in which an alumina green sheet is used, and a conductor pattern is printed on this green sheet is laminated in multiple layers while conducting vias with vias, and baked to integrate. There is.
そこで、従来上記グリーンシート多層法によるセラミッ
ク多層基板は、例えば第3図(a)に示すような構成で
ある。即ち、符号L1、L2、・・・は各層であり、1つの
層L1について述べると、薄いグリーンシート1の表面に
導体パターン2が印刷して形成される。また、グリーン
シート1の層間接続部には小径のvia3が明けられ、この
via3に導体ペースト4を充填し、via3の端部にはそれよ
り径の大きいランド5が上下層のviaとの導通を確保す
るように設けられる。そして、各層L1、L2、・・・のグ
リーンシート1を図示のように精度良く位置決めして積
層し、焼成するものである。Therefore, the conventional ceramic multilayer substrate by the green sheet multilayer method has a structure as shown in FIG. 3 (a), for example. That is, reference numerals L 1 , L 2 , ... Represent each layer, and when describing one layer L 1 , the conductor pattern 2 is formed by printing on the surface of the thin green sheet 1. Also, a small diameter via3 is opened in the interlayer connection part of the green sheet 1.
The via 3 is filled with the conductive paste 4, and a land 5 having a larger diameter is provided at the end of the via 3 so as to ensure electrical continuity with the vias in the upper and lower layers. Then, the green sheets 1 of the respective layers L 1 , L 2 , ... Are accurately positioned and laminated as shown in the drawing, and are fired.
ここで、上述グリーンシート1は高温雰囲気で焼成され
るため、焼成後は数%〜数10%の収縮を生じる。従っ
て、焼成前のグリーンシート1は予め収縮を見込んで形
成される。この場合の収縮で特に影響が大きいのはvia
接続部であり、ランド5の大きさ等は収縮によりずれて
も導通を図るようになっている。Here, since the green sheet 1 is fired in a high temperature atmosphere, shrinkage of several% to several tens% occurs after firing. Therefore, the green sheet 1 before firing is preliminarily formed in consideration of shrinkage. The contraction in this case is particularly affected by via
This is a connection portion, and the land 5 is designed to be electrically connected even if the size and the like of the land 5 deviate due to contraction.
ところで、上記従来例のものにあっては、各層L1、L2、
・・・のグリーンシート1にvia3とランド5を単独に形
成したものを単に積層するだけであるから、via3とラン
ド5の位置関係のみで導通性が決まる。ここで、焼成前
に高精度で各層L1、層L2、・・・のvia3とランド5を位
置決めするものの、各グリーンシート1の加工誤差等に
より数10μ位のずれγは生じ得る。また、積層時の圧力
分布不均一等により層間のグリーンシート1自体がずれ
たり、焼成時の収縮によるずれも加わる。一方、ランド
5の大きさは配線密度の制約を受けてあまり大きくでき
ない。以上の要因により、(b)のように焼成後に種々
のずれ要素で1つの層L2のvia3が上下層L1、L3のものか
ら完全に離脱して断線するケースがあった。By the way, in the above conventional example, each layer L 1 , L 2 ,
Since only the green sheet 1 having the via 3 and the land 5 formed separately is simply laminated, the conductivity is determined only by the positional relationship between the via 3 and the land 5. Here, the vias 3 and the lands 5 of the layers L 1 , L 2 , ... Are positioned with high accuracy before firing, but a deviation γ of several tens of μ may occur due to a processing error of each green sheet 1. In addition, the green sheets 1 themselves between the layers may be displaced due to uneven pressure distribution during lamination, or may be displaced due to shrinkage during firing. On the other hand, the size of the land 5 cannot be increased so much due to the restriction of the wiring density. Due to the above factors, in some cases, after firing, the via 3 of one layer L 2 is completely separated from the upper and lower layers L 1 and L 3 and is disconnected due to various misalignment elements as shown in (b).
また、via3には導体ペースト4のみが充填されるため、
その充填不足により焼成時にボイド等を生じて抵抗値の
増大及び信頼性の低下を招くこともあった。Also, since the via 3 is filled only with the conductor paste 4,
Due to the insufficient filling, voids or the like may occur during firing, leading to an increase in resistance and a decrease in reliability.
本考案は、かかる問題点に鑑みなされたもので、その目
的とするところは、via接続部の導通性を種々のずれ要
素に対し確保し、且つ抵抗値の増大を防ぎ且つ信頼性の
高いセラミック多層基板を提供することにある。The present invention has been made in view of the above problems, and an object thereof is to ensure the conductivity of the via connection portion with respect to various displacement elements, prevent an increase in resistance value, and have high reliability. It is to provide a multilayer substrate.
上記目的を達成するため、本考案のセラミック多層基板
は、 各層のグリーンシートのvia接続部にメタルピンを挿入
するのであり、この場合にvia接続部が1層又は複数層
に及ぶものにおいて、各via接続部毎にその全長に通し
てメタルピンを挿入設置するものである。In order to achieve the above object, the ceramic multilayer substrate of the present invention inserts a metal pin into the via connecting portion of the green sheet of each layer. In this case, in the case where the via connecting portion has one or more layers, A metal pin is inserted and installed along the entire length of each connection part.
上記構成に基づき、via接続部が特に複数層にまたがる
場合は、各グリーンシート相互のviaとランドがメタル
ピンによりずれないように位置決め保持され、これによ
り焼成後もvia接続部はメタルピンによる小さい抵抗値
で導通が確保されるようになる。Based on the above configuration, when the via connection part extends over multiple layers, the vias and lands of each green sheet are positioned and held by the metal pin so that they do not shift, and the via connection part after firing has a small resistance value due to the metal pin. This will ensure continuity.
以下、本考案の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図と第2図において、符号L1、L2、・・・は各層、
1はグリーンシート、2は導体パターン、3はvia、4
は導体ペースト、5はランドであり、各グリーンシート
1はvia3に半練りの導体ペースト4を充填しながらvia3
とランド5を位置決めして積層される。そこで、このグ
リーンシート積層の際に、via3の内部でランド5との間
に細いメタルピン6が挿入される。ここで、1層のvia
に接続部7aでは、メタルピン6がその長さに切断して1
個のvia3の中心に挿入される。2又は3層にわたるvia
接続部7b、7cでは、メタルピン6がそれらと略同一の長
さを有し、途中のランド5を貫通して2又は3個のvia3
の間に一直線上に通して挿入され、こうしてメタルピン
6は2又は3枚のグリーンシート1の間にまたがって挿
入設置される。そして、via3内に挿入されたメタルピン
6は導体ペースト4の粘性で支持される。In FIGS. 1 and 2, symbols L 1 , L 2 , ...
1 is a green sheet, 2 is a conductor pattern, 3 is via, 4
Is a conductor paste, 5 is a land, and each green sheet 1 is via3 while filling the via3 with the semi-kneaded conductor paste 4.
The lands 5 are positioned and stacked. Therefore, a thin metal pin 6 is inserted between the land 3 and the land 5 when the green sheets are laminated. Here, one layer of via
At the connecting part 7a, the metal pin 6 is cut to its length and
Inserted in the center of each via3. Via over 2 or 3 layers
In the connecting portions 7b and 7c, the metal pin 6 has substantially the same length as those of the connecting portions 7b and 7c, and penetrates the land 5 in the middle to penetrate two or three vias 3.
The metal pin 6 is inserted and installed so as to straddle between the two or three green sheets 1. The metal pin 6 inserted into the via 3 is supported by the viscosity of the conductor paste 4.
かかるグリーンシート積層後にプレスされ更に高温で焼
成され、このときプレス圧の不均一によるずれ、焼成収
縮によるずれを生じるが、特に複数層にまたがるvia接
続部7b、7cではメタルピン6によりグリーンシート1相
互のずれが規制される。このため、少なくともvia接続
部7b、7cの個所ではvia3、ランド5と共にメタルピン6
が一直線上に位置決め保持され、こうしてvia接続部7
b、7cの導通性が確保されるのである。また、各接続部7
a、7b、7cではメタルピン6が抵抗値の小さい導体とし
て機能する。After the green sheets are laminated and pressed at a higher temperature, deviations due to uneven press pressure and deviations due to firing contraction occur. Deviation is regulated. For this reason, at least the via connection portions 7b and 7c, the metal pin 6 together with the via 3 and the land 5 are formed.
Are aligned and held, thus the via connection 7
The conductivity of b and 7c is secured. Also, each connection 7
In a, 7b, and 7c, the metal pin 6 functions as a conductor having a small resistance value.
尚、メタルピン6はvia3の導体ペースト4と同一材質の
方が機械的、電気的に好ましいが、これに限定されな
い。また、メタルピン6は棒状のみならず筒状でも良
く、熱変形、ペーストとの整合性等を考慮して種々の形
状、本数が考えられる。The metal pin 6 is preferably made of the same material as the conductor paste 4 of the via 3 mechanically and electrically, but is not limited to this. The metal pin 6 may have a cylindrical shape as well as a rod shape, and various shapes and numbers can be considered in consideration of thermal deformation, compatibility with the paste, and the like.
以上述べてきたように、本考案によれば、 セラミック多層基板において、各via接続部の全長にわ
たりメタルピンが挿入されてずれを規制するので、焼成
後のvia接続部の断線が防止されて、via接続信頼性が向
上する。As described above, according to the present invention, in the ceramic multi-layer substrate, the metal pin is inserted over the entire length of each via connecting portion to regulate the deviation, so that the disconnection of the via connecting portion after firing is prevented, and the via connecting portion is prevented. Connection reliability is improved.
viaの部分のメタルピンにより一定の小さい抵抗値で導
通するので、電気特性が向上する。Since the metal pin in the via portion conducts electricity with a constant small resistance value, the electrical characteristics are improved.
メタルピンによるvia接続部の位置決めで、ランドの形
状は小さくできて配線密度の向上を促し、積層の作業性
が向上する。また、基板は局部的な位置決めで、全体的
にも収縮、変形が規制されて有利になる。By positioning the via connection part with a metal pin, the land shape can be made smaller, which promotes the improvement of wiring density and improves the workability of stacking. Further, the substrate is locally positioned, and shrinkage and deformation are restricted as a whole, which is advantageous.
第1図は本考案のセラミック多層基板の実施例を示す断
面図、 第2図は第1図のII−II断面図、 第3図(a)は従来例の断面図、(b)は断線状態を示
す断面図である。 図において、 1はグリーンシート、 2は導体パターン、 3はvia、 4は導体ペースト、 5はランド、 6はメタルピン、 7a、7b、7cはvia接続部である。FIG. 1 is a sectional view showing an embodiment of a ceramic multilayer substrate of the present invention, FIG. 2 is a sectional view taken along line II-II of FIG. 1, FIG. 3 (a) is a sectional view of a conventional example, and FIG. It is sectional drawing which shows a state. In the figure, 1 is a green sheet, 2 is a conductor pattern, 3 is a via, 4 is a conductor paste, 5 is a land, 6 is a metal pin, and 7a, 7b and 7c are via connecting portions.
Claims (1)
(2)を形成し、via(3)に導体ペースト(4)を充
填して端部にランド(5)を設けたものを複数層積層す
るセラミック多層基板において、 各層のグリーンシート(1)の各via接続部(7a、7b、7
c)毎に、その全長にわたってメタルピン(6)を一直
線上に挿入設置することを特徴とするセラミック多層基
板。1. A plurality of layers in which a conductor pattern (2) is formed on a green sheet (1), a via (3) is filled with a conductor paste (4) and a land (5) is provided at an end thereof. In the ceramic multilayer substrate, each via connection part (7a, 7b, 7) of the green sheet (1) of each layer
For each c), a metal multi-layered board in which metal pins (6) are inserted and installed in a straight line over their entire length.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15943188U JPH0642373Y2 (en) | 1988-12-09 | 1988-12-09 | Ceramic multilayer board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15943188U JPH0642373Y2 (en) | 1988-12-09 | 1988-12-09 | Ceramic multilayer board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0281085U JPH0281085U (en) | 1990-06-22 |
| JPH0642373Y2 true JPH0642373Y2 (en) | 1994-11-02 |
Family
ID=31440641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15943188U Expired - Lifetime JPH0642373Y2 (en) | 1988-12-09 | 1988-12-09 | Ceramic multilayer board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642373Y2 (en) |
-
1988
- 1988-12-09 JP JP15943188U patent/JPH0642373Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0281085U (en) | 1990-06-22 |
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