JPH0281085U - - Google Patents

Info

Publication number
JPH0281085U
JPH0281085U JP15943188U JP15943188U JPH0281085U JP H0281085 U JPH0281085 U JP H0281085U JP 15943188 U JP15943188 U JP 15943188U JP 15943188 U JP15943188 U JP 15943188U JP H0281085 U JPH0281085 U JP H0281085U
Authority
JP
Japan
Prior art keywords
green sheet
ceramic multilayer
multilayer board
vias
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15943188U
Other languages
Japanese (ja)
Other versions
JPH0642373Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15943188U priority Critical patent/JPH0642373Y2/en
Publication of JPH0281085U publication Critical patent/JPH0281085U/ja
Application granted granted Critical
Publication of JPH0642373Y2 publication Critical patent/JPH0642373Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案のセラミツク多層基板の実施例
を示す断面図、第2図は第1図の―断面図、
第3図aは従来例の断面図、bは断線状態を示す
断面図である。 図において、1はグリーンシート、2は導体パ
ターン、3はVia、4は導体ペースト、5はラ
ンド、6はメタルピン、7a,7b,7cはvi
a接続部である。
FIG. 1 is a cross-sectional view showing an embodiment of the ceramic multilayer substrate of the present invention, and FIG. 2 is a cross-sectional view of FIG. 1.
FIG. 3a is a sectional view of a conventional example, and FIG. 3b is a sectional view showing a disconnected state. In the figure, 1 is a green sheet, 2 is a conductor pattern, 3 is a via, 4 is a conductor paste, 5 is a land, 6 is a metal pin, 7a, 7b, 7c are vias
This is the a connection part.

Claims (1)

【実用新案登録請求の範囲】 グリーンシート1に導体パターン2を形成し、
via3に導体ペースト4を充填して端部にラン
ド5を設けたものを複数層積層するセラミツク多
層基板において、 各層のグリーンシート1の各via接続部7a
,7b,7c毎に、その全長にわたつてメタルピ
ン6を一直線上に挿入設置することを特徴とする
セラミツク多層基板。
[Claims for Utility Model Registration] A conductor pattern 2 is formed on a green sheet 1,
In a ceramic multilayer board in which multiple layers of vias 3 are filled with conductive paste 4 and lands 5 are provided at the ends are laminated, each via connection portion 7a of the green sheet 1 of each layer is
, 7b, 7c, metal pins 6 are inserted and installed in a straight line over the entire length of the ceramic multilayer board.
JP15943188U 1988-12-09 1988-12-09 Ceramic multilayer board Expired - Lifetime JPH0642373Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15943188U JPH0642373Y2 (en) 1988-12-09 1988-12-09 Ceramic multilayer board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15943188U JPH0642373Y2 (en) 1988-12-09 1988-12-09 Ceramic multilayer board

Publications (2)

Publication Number Publication Date
JPH0281085U true JPH0281085U (en) 1990-06-22
JPH0642373Y2 JPH0642373Y2 (en) 1994-11-02

Family

ID=31440641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15943188U Expired - Lifetime JPH0642373Y2 (en) 1988-12-09 1988-12-09 Ceramic multilayer board

Country Status (1)

Country Link
JP (1) JPH0642373Y2 (en)

Also Published As

Publication number Publication date
JPH0642373Y2 (en) 1994-11-02

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