JPH064342A - Area specified trace method - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object of the present invention to make it possible to execute program debugging as efficiently as possible with regard to the area designation trace method in the program operation collecting apparatus which records the program running address of the processing apparatus by the map trace method. [Arrangement] An information collecting area designating unit 300 for recording an address of an instruction in a predesignated storage area that has accessed data in the predesignated storage area is provided, and an instruction in the predesignated storage area is read. The information collecting area designating means 400 for recording the address of the accessed data in the predesignated storage area is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an area designation trace method in a program operation collecting apparatus for recording (single name tracing) a program running address of a processing apparatus by a map trace method.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing an example of a conventional program debug device, FIG. 9 is a diagram showing an example of information collection by map trace, and FIG. Figure (b) shows an example of the collection results.

The program debug device 1 illustrated in FIG. 7 is provided with a plurality of trace devices 3 for recording the program running addresses of the processors 2 by the map trace method illustrated in FIG. 9, respectively. It is connected to each processor 2 to be recorded via 4.

When the trace executor executes the trace of the processor 2 by the program debug device 1, first the workstation 5 controls the switching device 4 via the communication control device 6 to trace the processor 2 to be traced.
And the corresponding trace device 3 are connected.

Next, the trace executor issues a trace start command specifying the trace device number, the trace type (map trace this time), the trace-to-memory area, etc. from the workstation 5 via the communication control device 6. When input to the trace device 3, the trace device 3 that has received the command monitors the program running address of the trace target processor 2 and shows the running address in the storage area specified by the received command in FIG. 9 (b). It is recorded in the map format as described above.

For example, when the processor 2 executes a program from the address (10000) _H [where H indicates hexadecimal display] to (1000F) _H , as shown in FIG. 3 sets the area corresponding to the addresses (10000) _{H to} (1000F) _{H of the} trace memory (not shown) to the logic "1". [In FIG. 9 (b), the storage area set to the logical "1" in the trace memory (TRM) 31 is indicated by (*), and the logical "0" is displayed.
The storage area set to No. is displayed by (•). Next, after the processor 2 jumps from the address (1000F) _H to the address (10030) _H , the address (10
When the programs up to _H are executed, the trace device 3 determines the address (10030) _H in the trace memory.
Through (10035) _H corresponding area is set to logical “1”.

Similarly, the processor 2 is assigned the address (1
0073) _H through (10082) _H , address (100A
8) _{H to} (100B7) _H , address (10086) _{H to} (1008A) _H , address (10012) _{H to} (10
When the _H program is sequentially executed, the tracing device 3 changes the program running address of the processor 2 to that shown in FIG.
Record as illustrated in.

In the trace memory, the storage area corresponding to the running address is recorded in the logical "1", and the storage area corresponding to the non-running address is the logical "0".

[0009]

As is apparent from the above description, in the conventional program debug device,
Since the trace device 3 has unconditionally recorded the program running address of the trace target processor 2, for example, the address of the instruction that accessed the data in the memory area of particular interest is recorded, or the program running address of the memory area of particular interest is recorded. Since it was impossible to collect detailed trace information such as recording the address of the data accessed from the instruction, there was a problem that accurate and efficient program debugging could not be executed.

An object of the present invention is to enable program debugging by the map trace method to be executed as efficiently as possible.

[0011]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, reference numeral 100 is a processing device which is a target of information collection (trace), and 200 is a program operation collection device which is a target of the present invention.

Reference numeral 300 is an information collecting area designating means provided in the program operation collecting apparatus 200 according to the present invention (claim 1). Reference numeral 400 is an information collecting area designating unit provided in the program operation collecting apparatus 200 according to the present invention (claim 2).

[0013]

The program operation collecting device 200 is the processing device 1
The program running address of 00 is recorded by the map trace method.

The information collection area designating means 300 records the address of the instruction in the predesignated storage area that has accessed the data in the predesignated storage area. The information collection area designating means 400 records the address of the data in the predesignated storage area accessed by the instruction in the predesignated storage area.

Therefore, it is possible to accurately collect only the required information, such as recording the address of the instruction to be accessed by designating the data to be accessed, or recording the address of the data to be accessed by designating the instruction to be accessed. Therefore, the efficiency of program debugging by the program operation collecting apparatus is significantly improved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing a program debug device according to one embodiment of the present invention, FIG. 3 is a diagram showing a command format according to one embodiment of the present invention, and FIG. 4 is an example of an area designation unit in FIG. 5 is a diagram showing an example of input / output information of the read-only memory in FIG. 4, FIG. 6 is a diagram showing an example of a relationship between an access source instruction and access destination data, and FIG. 7 is a diagram. It is a figure which shows an example of the trace object in 6. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, the processing apparatus 1 in FIG.
1, the program debug device 1 is shown as the program operation collecting device 200 in FIG. 1, and the area specifying unit 7 is provided in each trace device 3 as the information collecting area specifying means 300 and 400 in FIG. It is provided.

In FIG. 4, a trace memory (TRM) provided in the trace device 3 together with the area designating section 7 is shown.
31 is shown. The trace memory (TRM) 31 shown in FIG. 2 has a storage capacity of 1 mega word × 1 bit, and the running address of the trace target processor 2 can be traced within the area of 1 mega word by the map trace method. .

A read-only memory (ROM) 751 provided in the area designating section 7 has eight kinds of head addresses every 128 kilowords when a 1-megaword storage area in the processor 2 is set as a trace object. , And the trace memory (TRM) 31 plays a role of address conversion so that data can be collected in the order of addresses.

Which of the eight types of leading addresses is adopted is
Input bit (I₃, I_Four, I
_Five). For example, input to the register 705
Bit (I₃, I_Four, I_Five) = (0,0,1) _B[However,
B indicates binary display] is set, the read-only
The input bit (I₀Through I₂)When
Upper address of the processor output address (f)
(F₁₇, F₁₈, F₁₉) = (0,0,1)_B, (0,
1,0) _B, ..., (1, 1, 1)_B, (0,0,0)
_BAre (0, 0, 0) respectively_B, (0, 0, 1)_B,
... (1,1,0)_B, (1, 1, 1)_BIs converted to
Output bit (O₀Through O₂) Is output as a tray
Address bit (A₁₇Through A
₁₉), The trace memory (TRM) 3
It will be recorded from the (0) word of 1 to the maximum area.
In addition, the input bit (I₃, I_Four,
I_Five) = (0,1,0)_BIf you set to
Input bit (I₀Through
I₂Output address (f) input as
Upper bit (f₁₇, F₁₈, F₁₉) = (0,1,
0)_B, (0,1,1)_B, ..., (1, 1, 1)_B,
(0, 0, 0)_B, (0, 0, 1)_BRespectively
(0, 0, 0)_B, (0, 0, 1)_B, ……, (1,
0, 1)_B, (1, 1, 0)_B, (1, 1, 1)_BStrange
Output bit (O₀Through O₂) Is output as
Address bits (A₁₇
Through A₁₉), So trace memory
It is recorded from the (0) word of (TRM) 31 to the maximum area.
The Rukoto.

In FIGS. 2 to 7, when the trace executor executes the trace of the processor 2 by the program debug device 1, first, the switching device 4 is controlled from the workstation 5 via the communication control device 6. , The trace target processor 2 and the corresponding trace device 3 are connected.

Next, the trace executor inputs a command as illustrated in FIG. 3 from the workstation 5 to the trace device 3 via the communication control device 6. The input command is composed of a trace device number (EN), a command type (CM), a trace mode (M), an access source area (SA) and an access destination area (DA) as illustrated in FIG. .

The trace device number (EN) designates the trace device 3 which executes the map trace this time, the command type (CM) designates the execution of the map trace this time, and the trace mode (M) designates the map map. Of the three types of trace modes included in the trace, that is, which one of the instruction trace, the access source trace, and the access destination trace is executed this time, the access source area (SA) is the storage area of the trace target instruction. Is designated, and the access destination area (DA) designates the storage area of the trace target data.

Here, the instruction trace is a map trace for recording the address of the executed instruction in the storage area designated by the access source area (SA), like the conventional map trace, and is also referred to as the access source trace. Is a map trace for recording the address of the instruction in the storage area specified by the access source area (SA) that has accessed the data in the storage area specified by the access destination area (DA). Is a map trace that collects the address of the data in the storage area specified by the access destination area (DA), which is accessed from the instruction in the storage area specified by the access source area (SA).

First, the command specifying the instruction trace as the trace mode (M) is the work station 5
The case of input from is explained. The trace device 3 analyzes the received command, the command type (CM) is the map trace command, and the trace mode (M).
Recognizes that the instruction trace is an instruction trace, the instruction trace start address / end address (a) designated in the access source area (SA) of the received command is set in the register 701 in the area designation unit 7, and is set in the registers 702 and 703. Is not set, and the access source trace signal (d) and the access destination trace signal (e) input to the area designating section 7 are set to a logic "0".

Further, the trace device 3 sets the trace data signal (j) input to the trace memory (TRM) 31 to a logical "0" and initializes all the storage areas of the trace memory (TRM) 31 to a logical "0". After setting, the trace data signal (j) is set to logic "1".

When the access source trace signal (d) is set to logic "0", the selector (SEL) 731
Selects the data input from the input terminal (0) and outputs it from the output terminal (X), and the access source trace signal (d) and the access destination trace signal (e) are both set to logic "0". Selector (SEL) 732
Selects the data input from the input terminal (0) and outputs it from the output terminal (X).

When the processor 2 executes the program in such a state, the tracing device 3 monitors the program running state of the processor 2, and the processor output address (f), instruction fetch signal (g), operand access signal (h), The latch timing signal (i) or the like is input to the area designating unit 7.

In the area designating unit 7, the processor output address (f) input to the comparing unit 711 is compared with the instruction trace start address / end address (a) set in the register 701 to obtain the processor output address ( When f) is recognized to exist in the access source area (SA) designated by the instruction trace start address / end address (a), the output signal q ₇₁₁ to be output is set to logic "1".

When the processor 2 executes the instruction fetch at the processor output address (f), the instruction fetch signal (g) input to the area designating unit 7 becomes logical "1", so that the output of the gate 722 is output. Signal q ₇₂₂ is set to a logical "1".

The selector (SEL) 731 outputs the processor output address (f) input to the input terminal (0) from the output terminal (X), and the lower 17 bits (f _{0 to} f).
₁₆ ) are input to the trace memory (TRM) 31 as address bits (A _{0 to} A ₁₆ ), and the upper 3 bits (f _{17 to} f ₁₉ ) are input bits (I _{0 to} I ₂ ) to the read-only memory (ROM) 751. ), Converted as described above, output as output bits (O _{0 to} O ₂ ), and output to the trace memory (TRM) 31 as address bits (A _{17 to} A ₂ ).
₁₉ ) Enter as.

The selector (SEL) 732 outputs the output signal q _{72 2} (logic "1") input to the input terminal (0).
Is output from the output terminal (X) and input to the write control unit 741.

The write controller 741 is a selector (SEL).
When the output signal q ₇₂₂ (logic “1”) is input from 732, the input terminal (WE) of the trace memory (TRM) 31.
The write signal (we) input to is set to logic "1".

As a result, the trace memory (TRM) 31
Address bit (A₀Through A ₁₉) Is entered as
Trace to the converted processor output address (f)
The data signal (j) (= logical “1”) is recorded,
Map trace of each instruction executed by
It

Next, a case where a command designating an access source trace as the trace mode (M) is input from the workstation 5 will be described. Trace device 3
Analyzes the received command, and the command type (CM)
Is a map trace command, and when the trace mode (M) recognizes that it is an access source trace, the access source trace start address / end address (b) specified in the access source area (SA) of the received command is assigned to the area designating section. 7 is set in the register 702, the access destination trace start address / end address (c) specified in the access destination area (DA) of the received command is set in the register 703, and nothing is set in the register 701. Instead, the access source trace signal (d) input to the area designation unit 7 is set to logic "1", and the access destination trace signal (e) is set to logic "0".

As described above, the trace device 3 initializes the entire storage area of the trace memory (TRM) 31 to logic "0" and then sets the trace data signal (j) to logic "1".

When the access source trace signal (d) is set to logic "1", the selector (SEL) 731 selects the data input from the input terminal (1) and outputs it from the output terminal (X). Access source trace signal (d)
If either of the access destination trace signal (e) and the access destination trace signal (e) is set to logic "1", the selector (SEL) 732 selects the data input from the input terminal (1) and outputs it from the output terminal (X). .

In this state, when the processor 2 fetches an instruction, the trace unit 3 monitors the program running state of the processor 2 and outputs the processor output address (f),
The instruction fetch signal (g), the latch timing signal (i), etc. are input to the area designating section 7.

In the area designating unit 7, the processor output address (f) input to the comparing unit 712 is compared with the access source trace start address / end address (b) set in the register 702 to obtain the processor output address. (F) is the access source area (SA) specified by the access source trace start address / end address (b)
When it is recognized that the output signal q ₇₁₂ exists, the output signal q ₇₁₂ to be output is set to the logic "1".

Further when the instruction fetch signal is input to the area specifying unit 7 (g) and latch timing signal (i) is set to a logic "1", the output signal q ₇₂₁ of the gate 721
Is set to logic “1” and input to the register 704 and the flip-flop (FF) 761.

The register 704 stores the processor output address (f) input to the register 704 when the output signal q ₇₂₁ is set to logic "1". Selector (S
EL) 731 is the processor output address (f) stored in the register 704 which is input to the input terminal (1).
From the output terminal (X), and the upper 3 bits (f _{17 to} f ₁₉ ) are read-only memory (ROM) 7 in the same manner as described above.
Trace memory (TRM) 31 after conversion by 51
Address bits (A _{0 to} A ₁₉ ).

Next, when the processor 2 accesses the operand (data) designated by the fetched instruction, the trace device 3 monitors the program running state of the processor 2, and outputs the processor output address (f) and the operand access signal (h). ) Or the like is input to the area designation unit 7.

In the area designation unit 7, the processor output address (f) input to the comparison unit 713 is compared with the access destination trace start address / end address (c) set in the register 703 to determine the processor output address. (F) is the access destination area (DA) specified by the access destination trace start address / end address (c)
When it recognizes that the output signal q ₇₁₃ exists, the output signal q ₇₁₃ to be output is set to logic "1".

The gate 723 is a flip-flop (F
The output signal q ₇₆₁ of F) 761, the output signal q ₇₁₃ of comparator 713 is set to a logic "1", and the operand access signal input (h) is set to a logic "1",
Set output signal q ₇₂₃ to logic "1".

The selector (SEL) 732 outputs the output signal q ₇₂₃ (logic “1”) input to the input terminal (1) from the output terminal (X) and inputs it to the write control section 741. When the output signal q ₇₂₃ (logic “1”) is input from the selector (SEL) 732, the write control unit 741 inputs the write signal (we) input to the input terminal (WE) of the trace memory (TRM) 31. Is set to logic "1".

As a result, the trace memory (TRM) 31
Indicates that the processor output address (f) at the time of fetching the instruction that accesses the data existing in the area of the access destination trace start address / end address (c) set in the register 703 is the read-only memory (RO).
M) 751 is converted and input as address bits (A _{0 to} A ₁₉ ), and a trace data signal (j) (= logical “1”) is input to an input terminal (DI) and recorded by a map trace method. To be done.

Next, a case will be described in which a command specifying the access destination trace as the trace mode (M) is input from the workstation 5. Trace device 3
Analyzes the received command, and the command type (CM)
Is a map trace command, and when the trace mode (M) recognizes that it is an access destination trace, the access source trace start address / end address (b) designated in the access source area (SA) of the received command is assigned to the area designating section. 7 is set in the register 702, the access destination trace start address / end address (c) specified in the access destination area (DA) of the received command is set in the register 703, and nothing is set in the register 701. Instead, the access destination trace signal (e) input to the area designating section 7 is set to logic "1", and the access source trace signal (d) is set to logic "0".

As described above, the trace device 3 initializes the entire storage area of the trace memory (TRM) 31 to logic "0" and then sets the trace data signal (j) to logic "1".

When the access source trace signal (d) is set to logic "0", the selector (SEL) 731 selects the data input from the input terminal (0) and outputs it from the output terminal (X). Access source trace signal (d)
If either of the access destination trace signal (e) and the access destination trace signal (e) is set to logic "1", the selector (SEL) 732 selects the data input from the input terminal (1) and outputs it from the output terminal (X). .

When the processor 2 fetches an instruction in such a state, the trace device 3 inputs the processor output address (f), the instruction fetch signal (g), the latch timing signal (i) and the like to the area designating section 7.

In the area designation unit 7, the processor output address (f) input to the comparison unit 712 is compared with the access source trace start address / end address (b) set in the register 702, and the processor output address (F) is the access source area (SA) specified by the access source trace start address / end address (b)
When it is recognized that the output signal q ₇₁₂ exists, the output signal q ₇₁₂ to be output is set to the logic "1".

[0052] Also, when an instruction fetch signal is input to the area specifying unit 7 (g) and latch timing signal (i) is set to a logic "1", the output signal q ₇₂₁ of the gate 721
Is set to logic “1” and input to the register 704 and the flip-flop (FF) 761.

The input processor output address (f) is passed through the selector (SEL) 731 and the read-only memory (ROM) 751 to the trace memory (TRM).
However, since the write signal (we) is not input to the input terminal (WE) at this stage, the trace data signal (j) (= logical “1”) is not recorded.

When the output signal q ₇₂₁ is set to the logic "1", the register 704 stores the processor output address (f) input to the register 704, but the selector (SEL) 731 inputs the input terminal (1). ), The trace data (TRM) 31
Will not be transmitted to.

Next, when the processor 2 accesses the operand (data) designated by the fetched instruction, the trace device 3 monitors the program running state of the processor 2, and outputs the processor output address (f) and the operand access signal (h). ) Or the like is input to the area designation unit 7.

In the area designating section 7, the selector (SE
L) 731 outputs the processor output address (f) input to the input terminal (0) from the output terminal (X), and only the upper 3 bits (f _{17 to} f ₁₉ ) are read-only memory (RO).
M) 751 performs necessary conversion, and then inputs the address bits (A _{0 to} A ₁₉ ) to the trace memory (TRM) 31, and the comparison unit 713 registers the input processor output address (f) with the register. In the access destination area (DA) in which the processor output address (f) is specified by the access destination trace start address / end address (c) by comparing with the access destination trace start address / end address (c) set in 703. When it is recognized that the output signal q ₇₁₃ exists, the output signal q ₇₁₃ to be output is set to the logic “1”.

The gate 723 is a flip-flop (F
The output signal q ₇₆₁ of F) 761, the output signal q ₇₁₃ of comparator 713 is set to a logic "1", and the operand access signal input (h) is set to a logic "1",
Set output signal q ₇₂₃ to logic "1".

The selector (SEL) 732 outputs the output signal q ₇₂₃ (logic “1”) input to the input terminal (1) from the output terminal (X) and inputs it to the write control unit 741. When the output signal q ₇₂₃ (logic “1”) is input from the selector (SEL) 732, the write control unit 741 inputs the write signal (we) input to the input terminal (WE) of the trace memory (TRM) 31. Is set to logic "1".

As a result, the trace memory (TRM) 31
Is accessed by an instruction existing in the area of the access source trace start address / end address (b) set in the register 702, and the access destination trace start address / end address (c) set in the register 703 is accessed. The processor output address (f) of the data existing in the area of is converted by the read only memory (ROM) 751 and input as address bits (A _{0 to} A ₁₉ ), and the trace data signal (j) (= Logic "1") is input to the input terminal (DI) and recorded by the map trace method.

FIGS. 6 and 7 exemplify trace objects in three kinds of trace modes (M), that is, instruction trace, access source trace and access destination trace.

In FIG. 6, access source area (SA) =
Instructions (k ₁ ) to (k ₄ ) existing in 0 to (1M-1) words (where M represents a mega), access source area (S
A) = 1 instructions (k ₃ ) to (k ₇ ) existing in 1M word to (2M−1) word, and access source area (SA)
= 2M words to (3M-1) words, the processor 2 that has executed the instruction (k ₈ ) has access destination area (DA) = 0.
Term to (1M-1) data present in the word (p ₁₎ to (p _3), access area (DA) = 1M word to (2M
-1) data (p ₄ ) and (p ₅ ) existing in word, access destination area (DA) = data (p ₆ ) and (p ₇ ) existing in 2M word to (3M-1) word, and access Destination area (DA) = data existing in 3M words or more (p ₈ )
To each of the

In such a case, as shown in FIG. 7, when the instruction trace is designated as the trace mode (M) and the access source area (SA) = 0 word to (1M-1) word is designated, the instruction (k ₁ ) To (k ₄ ) addresses are recorded, and if the access source area (SA) = 1 megaword to (2M−1) words is specified as the instruction trace start address / end address (a), instructions (k ₅ ) to (K ₇ )
Address is recorded, and the access source area (SA) = as the instruction trace start address / end address (a)
2M word to (3M-1) words and designating an instruction address of (k ₈₎ is recorded.

The access source trace is specified as the trace mode (M), and the access destination area (DA) = 1.
When M words to (2M-1) words are specified and the access source area (SA) = 0 words to (1M-1) words are specified, the address of the instruction (k ₃ ) is recorded, and the access source area (SA) is also recorded. SA) = 1M word to (2M-1) word is specified, the address of the instruction (k ₇ ) is recorded, and access source area (SA) = 2M word to (3M-1) word is specified. Does not exist.

Further, the access destination trace is designated as the trace mode (M), and the access source area (SA) = 0.
When the word to (1M-1) word is specified and the access destination area (DA) = 0 word to (1M-1) word is specified, the addresses of the data (p ₁ ) and (p ₂ ) are recorded, and When the access destination area (DA) = 1M word to (2M-1) word is specified, the address of the data (p ₄ ) is recorded, and when the access destination area (DA) = 2M word to (3M-1) word is specified. There is no data recorded.

As is clear from the above description, according to the present embodiment, the instruction mode is designated as the trace mode (M) and the access source area (SA) is designated, or the trace mode (M). By specifying the access source trace or the access destination trace as and the access source area (SA) and the access destination area (DA), detailed trace information more suited to the purpose can be recorded by the map trace method. Become.

It is to be noted that FIGS. 2 to 7 are merely examples of the present invention until now, and for example, the instruction (k) existing in the access source area (SA) and the data (p existing in the access destination area (DA)). ) Is not limited to what is shown in the figure, and many other modifications can be considered, but in any case, the effect of the present invention does not change. Further, the conversion format of the processor output address (f) is not limited to that shown in the figure, and many other modifications can be considered, but in any case, the effect of the present invention does not change. Further, the information collection area designating means 300 and 400 which is the object of the present invention is not limited to the area designating part 7 shown in the figure, and various modifications can be considered. The effect of does not change. Further, it goes without saying that the program operation collecting apparatus 200 which is the object of the present invention is not limited to the program debug apparatus 1 shown in the figure.

[0067]

As described above, according to the present invention, in the program operation collecting apparatus, the address of the instruction to be accessed by designating the data to be accessed is recorded, or the data to be accessed by designating the instruction to be accessed is recorded. It becomes possible to accurately collect only necessary information such as recording the address, and the program debugging efficiency by the program operation collecting apparatus is significantly improved.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a program debug device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a command format according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of an area designating section in FIG.

5 is a diagram showing an example of input / output information of the read-only memory in FIG.

FIG. 6 is a diagram showing an example of a relationship between an access source instruction and access destination data.

7 is a diagram showing an example of a trace target in FIG.

FIG. 8 is a diagram showing an example of a conventional program debug device.

FIG. 9 is a diagram showing an example of information collection by map trace, in which FIG. 9A shows an example of a trace target program running process, and FIG. 9B shows an example of a collection result.

[Explanation of symbols]

 1 Program Debugging Device 2 Processor 3 Tracing Device 4 Switching Device 5 Workstation 6 Communication Control Device 7 Area Designating Unit 31 Trace Memory (TRM) 100 Processing Device 200 Program Action Collecting Device 300, 400 Information Collecting Region Designating Means 701 to 705 Register 711 To 713 comparator 721 to 723 gates 731 and 732 selector (SEL) 741 write controller 751 read only memory (ROM) 761 flip-flop (FF)

Claims (2)

[Claims] 1. A program operation collection device (200) for recording a program running address of a processing device (100) by a map trace method, wherein a data in a predesignated storage region is accessed and a predesignated storage region is accessed. Area designation trace system characterized by comprising an information collection area designation means (300) for recording the address of the instruction. 2. A program operation collection device (200) for recording a program running address of a processing device (100) by a map trace method, which is accessed from an instruction in a prespecified storage area,
An area designation trace system characterized by comprising an information collection area designation means (400) for recording an address of data in a designated storage area.