JPH064362A - Synchronous trace system - Google Patents

Abstract

(57) [Summary] [Object] A synchronous trace method in an information collecting device for recording the program running progress of a plurality of processing devices, and an object thereof is to enable a plurality of processors to be synchronously traced. [Configuration] Each information collecting unit 200 has its own information collecting unit 200
If the condition to start recording is set in the table, the satisfaction of the recording start condition is monitored, and when the satisfaction of the recording start condition is detected, all information collecting units 200 are instructed to start the recording. A means 400 is provided to start and record the elapsed time of recording in each information collecting unit 200, or to record the elapsed time of recording in the own information collecting unit 200 to all other information collecting units 200. Configure to notify and record.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous trace method in an information collecting device for recording (single name tracing) program running progress of a plurality of processing devices.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an example of a multiprocessor trace device 1 to which the present invention is applied, FIG. 8 is a diagram showing an example of a conventional trace device, and FIG. It is a figure showing an example of
The figure (a) shows an example of the instruction sequence to be traced, and the figure (b)
Shows an example of the collection result.

The multiprocessor trace device 1 illustrated in FIG. 7 is provided with a plurality of trace devices 3 for recording the program running progress of the processor 2, respectively.
It is connected to each processor 2 to be recorded through the switching device 4.

As shown in FIG. 8, each trace device 3 includes a processor interface unit (PIF) 31 for interfacing with the recording target processor 2, an instruction unit associated with nibble access to the memory of the recording target processor 2, and An alignment processing unit (RAC) 32 that arranges the access order of the data unit, and an overlay control unit (OV) that performs address conversion processing with the overlay processing of the recording target processor.
C) 33 and a trap control unit (TRP) that determines whether the set trace start condition and trace end condition are satisfied.
34, a trace condition selection unit (TRS) 35 for selecting an address, an instruction and data (trace information) where the set trace condition is satisfied, and a trace condition selection unit (TR
S) 35, a trace controller (TRC) 36 that controls recording of trace information, a trace memory (TRM) 37 that records trace information under the control of the trace controller (TRC) 36, and a multiprocessor trace. A microprocessor (MP that controls the entire device 1
U) 38.

When the trace executor executes the traces of the plurality of processors 2 by the multiprocessor trace device 1, first, the switching device 4 is controlled from the workstation 5 via the communication control device 6, and each trace target is controlled. The processor 2 and the corresponding trace device 3 are connected.

[0006] Next, the trace executor determines that each trace device 3
On the other hand, when the trace start condition, the trace end condition and the trace condition are sequentially input from the workstation 5 through the communication control unit 6, the microprocessor (MPU) 38 in each trace unit 3 receives the input trace start condition. , The trace end condition and the trace condition are set in the trap control unit (TRP) 34 and the trace condition selection unit (TRS) 35, respectively.

Subsequently, when the trace executor inputs a trace activation instruction to all the trace devices 3 from the work station 5, the microprocessor (MPU) 38 in each trace device 3 operates in the trace device 3. Start each part.

The microprocessor (MPU) 38 shows the progress of the program running of the trace target processor 2, the processor interface unit (PIF) 31, the alignment processing unit (RAC) 32, the overlay control unit (OVC) 33 and the trap control unit (TRP). ) 34, and when the trap start condition is satisfied by the trap control unit (TRP) 34, the trace condition selecting unit (TRS) 35
The trace information (address, instruction or data content, elapsed time) detected by the trace control unit (TRC) 36 is traced by the trace memory (TRM) 3
Record at 7.

The information collecting method as illustrated in FIG. 9 is called a dynamic trace. FIG. 9 (a) shows a part of the instruction sequence executed by the trace target processor 2.
Part (b) of the trace information corresponding to part (a) of the same figure is shown.

The elapsed time depends on the trace controller (TR
C) A timer provided in 36 and initially set to "0" before the start of tracing measures elapsed time by a predetermined clock signal.

[0011]

As is apparent from the above description, in the conventional multiprocessor trace device, each trace device 3 is targeted based on the set trace start condition, trace end condition and trace condition. Since each processor 2 to be traced is independently traced and recorded together with the elapsed time at which each clocking has started independently, each tracing device can be operated even when the respective processors 2 to be traced are operating in association with each other. Three
There was a problem that it was impossible to analyze the trace information of the above in synchronization.

An object of the present invention is to enable a plurality of processors to be traced synchronously.

[0013]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, reference numeral 300 denotes an information collecting apparatus which is a target of the present invention, 100 denotes a plurality of processing apparatuses which are targets of information collection (trace), and 200 denotes an information collecting which records a program running progress of each target processing apparatus 100. It is a department.

Reference numeral 400 denotes each information collecting unit 20 according to the present invention.
It is another starting means provided in 0.

[0015]

The other activating means 400 monitors the satisfaction of the recording start condition when the condition for starting the recording is set in the own information collecting section 200, and when the satisfaction of the recording start condition is detected, Instruct all the information collecting units 200 to start recording.

The other starting means 400 includes the information collecting units 2
At the same time as instructing 00 to start recording, each information collecting unit 20
It is considered that the elapsed time of the recording is started and recorded within 0, and the elapsed time of the recording measured within the own information collecting unit 200 is notified to all other information collecting units 200,
Recording is considered.

Therefore, all the information collecting units in the information collecting apparatus start collecting information all at once based on the satisfaction of the condition notified from the specific information collecting unit whose recording start condition is set in advance, and Since it is recorded together with the unified elapsed time in the collecting device, the program running progress of each processing device can be recorded in synchronization, and more effective information can be collected regarding a plurality of processors operating in cooperation.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing a trace device according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the synchronization unit in FIG. 2, and FIG. 4 is a diagram showing an example of a signal transmission means to another trace device. 5 is a diagram showing a trace processing process according to an embodiment of the present invention, and FIG. 6 is a diagram showing another example of the synchronization unit in FIG. The same reference numerals denote the same objects throughout the drawings. The target multiprocessor trace device is as shown in FIG.

2 and 7, a processor 2 is shown as the processing device 100 in FIG. 1, and FIG.
The multiprocessor trace device 1 is shown as the information collecting device 300 in FIG.
The tracing device 3 is shown as 00, and the synchronization unit (SYN) 7 is provided in the trace control unit (TRC) 36 as the other starting means 400 in FIG.

2 to 5, a trace executor executes a trace for a plurality of (for example, three) processors 2 (individual processors are referred to as 2 ₁ , 2 ₂ and 2 _3, and so on). In this case, as described above, after connecting the respective trace target processors 2 ₁ , 2 ₂ and 2 ₃ and the corresponding trace devices 3 ₁ , 3 ₂ and 3 ₃ ,
A trace device 3 ₂ that traces one processor 2 (for example, the processor 2 ₂ ) is defined as a trace reference, and a trace start condition / trace end condition and a synchronous trace are set for the selected trace device 3 ₂ . Commands for setting the trace end condition and the synchronous trace for the other trace devices 3 ₁ and 3 ₃ are input from the workstation 5 via the communication control device 6 respectively.

Selected tracing device 3₂In
Microprocessor (MPU) 38 ₂Input commands
Analyze and first set trace start condition / trace end condition
Trap control unit (TRP) 3
Four₂Set the trace start condition in the
1), and then input command for synchronization trace setting command
(Step S2), the trace controller (T
RC) 36₂Synchronizing unit (SYN) 7₂To type in
Period trace signal (a) in synchronous mode (eg logic
Set to "1") (step S3), and further trap control
Department (TRP) 34₂If you set the trace end condition in
Together (step S4), the trap control unit (TRP) 34
₂Sync to indicate that the trace start condition has been set to
Conversion part (SYN) 7 ₂No trace start condition input to
Set the signal (b) to the set state (for example, logic "0")
It

In the other tracing device 3 ₁ (3 ₃ ), the microprocessor (MPU) 38 ₁ (38 ₃ )
Analyzes the input command and recognizes it as a synchronous trace setting command (step S2), the trace control unit (TR
C) Synchronizing unit (SYN) 7 ₁ (7 ₃ ) in 36 ₁ (36 ₃ ).
_After setting the synchronous trace signal (a) input to ₃ ) to the synchronous mode (logical "1") (step S3) and setting the trace end condition in the trap control unit (TRP) 34 ₁ (34 ₃ ), In order to indicate that the trace start condition is not set, the trace start condition non-setting signal (b) input to the synchronizing unit (SYN) 7 ₁ (7 ₃ ) is set to the non-setting state (for example, logic “1”). Set.

Next, the trace executor determines that each trace device 3
_When commands for setting the trace conditions for ₁ , 3, ₂ and 3 ₃ are input from the workstation 5 through the communication control unit 6, each microprocessor (M
PU) 38 ₁ , 38 ₂ and 38 ₃ analyze the input command and recognize that it is a trace condition setting command, each trace condition selecting section (TRS) 35 ₁ , 35 ₂ and 3
Each trace condition is set within 5 ₃ (step S5).

Here, each of the microprocessors (MPUs) 38 ₁ , 38 ₂ and 38 of the trace devices 3 _{1 to} 3 ₃ is
₃ sets the trace command setting signal (e) input to each of the synchronizing units (SYN) 7 ₁ , 7 ₂ and 7 ₃ to the setting state (for example, logic “1”), and waits for the trace activation state setting.

Next, the trace executor determines that the trace device 3 ₂
When a command to set the trace activation state is input from the workstation 5 via the communication control unit 6, each microprocessor (MPU) 38 ₂ analyzes the input command and recognizes it as the trace activation state setting command. The trace activation signal (g) is input to the synchronization unit (SYN) 7 ₂ in the trace control unit (TRC) 36 ₂ (step S6).

Synchronizer (SYN) 7₂Input to
The source start signal (g) is the other trace device illustrated in FIG.
Via the signal transmission means to the storage device 3₁And
And 3 ₃Synchronization unit (SYN) 7₁And 7₃In addition,
It is input as a race start signal (h).

[0027] Trace activation state setting tracer 3 ₂ input commands, monitors the operation state of the corresponding processor 2 _2, that trace start condition is satisfied in the processor 2 _2, the trap controller (TRP) 34
_When it is detected by ₂ (step S7), the synchronization unit (SY
N) Trace start condition satisfaction signal input to 7 ₂ (c)
Is a established state (for example, logic “1”).

[0028] In the synchronization unit (SYN) 7 ₂ are synchronous trace signal (a) is the the set flip-flop 701 is set to a logic "1", to set the output signal q ₇₀₁ to a logic "1" , Trace start condition satisfied signal (c)
Setting the but is set to a logic "1", the output signal q ₇₂₁ of gate 721 is also set to logic "1", other trace start condition satisfaction output signal output from the driver 731 (k) to a logic "1" And the output signal q of the gate 724.
_{724 is} also set to logic "1".

Since the trace command setting signal (e) is also set to logic "1", the flip-flop 702 is also set, the output signal q ₇₀₂ is set to logic "1", and the trace start signal (g) is set. _Is also set to logic "1", the output signal q 725 of the gate 725 is also set to logic "1", and as a result, the output signal q _{726 of the} gate 726 is also set to logic "1". 703 is set and the output signal q _{70 3} is set to logic "1".

As described above, the trace start condition satisfaction signal (c) is set to the logic "1", whereby the gate 7
27 output signal q ₇₂₇ is set to a logic "1" and flip-flop 704 is set to set output signal q ₇₀₄ to a logic "1".

When the output signal q ₇₀₄ is set to the logic "1", the timer 711 starts counting the counting clock signal (j), and the elapsed time signal (n) which is initially set to "0". Is incremented for each counting clock signal (j) and transmitted to the trace memory (TRM) 37 ₂ .

When the trace condition selection unit (TRS) 35 ₂ detects that the trace condition is satisfied in the corresponding processor 2 ₂ , the trace unit 3 ₂ inputs the trace condition to the synchronization unit (SYN) 7 _2. The coincidence signal (i) is set to the established state (for example, logic "1").

The trace condition described here is a combination of the address condition / data condition / function condition of the information desired by the trace executor, for example, the instruction execution result of the necessary address range and the necessary instruction. It is used to narrow down the trace information to extract only When each condition is set to unconditional, all accesses after the trace start condition is satisfied are traced.

[0034] In the synchronization unit (SYN) 7 _2, when the trace condition match signal (i) is set to a logic "1",
The write control signal (m) output from the gate 728 is set to logic "1" and transmitted to the trace memory (TRM) 37 ₂ .

The trace memory (TRM) 37 ₂ has a write control signal (m) transmitted from the synchronizing section (SYN) 7 _2.
Is set to logic "1", the processor 2 ₂ to the processor interface unit (PIF) 31 ₂ , the alignment processing unit (RAC) 32 ₂ and the overlay control unit (OVC) 3
The trace information collected via 3 ₂ is recorded in the trace memory (TRM) 37 ₂ together with the elapsed time signal (n) transmitted from the synchronization unit (SYN) 7 ₂ .

Further, the recorded trace information is sequentially read by the microprocessor (MPU) 38 _{2 and} repeated until there is no more data (step S10 or S1).
1).

Now, a situation in which the other trace start condition satisfaction output signal (k) output from the trace device 3 ₂ is transmitted to the trace devices 3 ₁ and 3 ₃ will be described with reference to FIG.

In FIG. 4, the driver 731 and the gate 723 which are directly related to the transmission of the other trace start condition fulfillment output signal (k) of each synchronization unit (SYN) 7 in each trace control unit (TRC) 36. Is shown and the others are omitted, and a subscript for identifying each of the trace devices 3 _{1 to} 3 ₃ is added to the signal such as the output signal (k) for satisfying the other trace start condition.

In FIG. 4, the trace controller (TRC)
36 When the synchronization portion of the ₂ (SYN) 7 ₂ other trace start condition satisfaction output signal output from the (k ₂₎ is set to a logic "1", the gate of the trace control unit (TRC) 36 in ₂ 362 _The front stage transmission signal (x _D2 ) output from ₂ and the rear stage transmission signal (x _U2 ) output from the gate 363 ₂ are set to logic "1", respectively.

Pre-stage transmission signal (x_D2) Is the trace controller
(TRC) 36₁Inside gate 361 ₁Is input to
Gate 361₁Other trace start condition output from is satisfied
Input signal (d₁) Is also set to logic "1" and the synchronization unit
(SYN) 7₁Entered in.

Since the subsequent transmission signal (x _U2 ) is input to the gate 361 ₃ in the trace controller (TRC) 36 ₃ , another trace start condition satisfaction input signal (d ₃ ) output from the gate 361 _3. Is also set to logic "1" and input to the synchronization section (SYN) 7 ₃ .

The trace activation signal (g) output from the synchronization unit (SYN) 7 ₂ is also synchronized with the synchronization unit (SY) by the same means as the other trace start condition satisfied output signal (k).
N) The signal is transmitted to the other trace activation signal (h) to 7 ₁ and 7 ₃ and waits for the other trace start condition satisfied output signal (k).

[0043] In the synchronization unit (SYN) 7 ₁ is synchronous trace signal (a) is the the set flip-flop 701 is set to a logic "1", to set the output signal q ₇₀₁ to a logic "1" , the other trace start condition satisfaction input signal (d) is set to a logic "1", the output signal q ₇₂₃ of gate 723 is also set to logic "1", the output signal q ₇₂₄ of gate 724 is also a logic "1" Is set to.

The trace command setting signal (e) is also logical.
Since it is set to "1", the flip-flop 702 is also
Set, output signal q₇₀₂Is set to logic "1",
Other trace activation signal (h) is also set to logic "1"
Therefore, the output signal q of the gate 725₇₂₅Is also a logical "1"
Set, resulting in output signal q of gate 726₇₂₆Also logic
Since it is set to "1", the flip-flop 703
Set, output signal q ₇₀₃Is set to logic "1"
It

As described above, the other trace start condition establishment input signal (d) is set to logic "1", the output signal q ₇₂₇ of the gate 727 is set to logic "1", and the flip-flop 704 is set. Output signal q
Set ₇₀₄ to logic "1".

When the output signal q ₇₀₄ is set to logic "1", the timer 711 starts counting the counting clock signal (j), and the elapsed time signal (n) initially initialized to "0". Is incremented for each counting clock signal (j) and transmitted to the trace memory (TRM) 37 ₁ .

When the trace device 3 ₁ detects that the trace condition is satisfied in the corresponding processor 2 ₁ by the trace condition selecting unit (TRS) 35 ₁ , the microprocessor (MPU) 38 ₁ synchronizes with the synchronizing unit (SY).
N) The trace condition match signal (i) input to 7 ₁ is set to the established state (for example, logic "1").

[0048] In the synchronization unit (SYN) 7 _1, when the trace condition match signal (i) is set to a logic "1",
The write control signal (m) output from the gate 728 is set to logic "1" and transmitted to the trace memory (TRM) 37 ₁ .

The trace memory (TRM) 37 ₁ has a write control signal (m) transmitted from the synchronizing section (SYN) 7 _1.
Is set to a logical "1", the processor 2 ₁ to the processor interface unit (PIF) 31 ₁ , the alignment processing unit (RAC) 32 ₁ and the overlay control unit (OVC) 3
The trace information collected via 3 ₁ is recorded in the trace memory (TRM) 37 ₁ together with the elapsed time signal (n) transmitted from the synchronization unit (SYN) 7 ₁ (step S10 or S11?).

[0050] Also in the synchronization unit (SYN) 7 _3, the other trace start condition satisfaction input signal (d) is a logic "1", in the same process as in the synchronization unit (SYN) 7 _1, timer 711 transmits the elapsed time signal which has been initially set to the initial "0" (n), is incremented for each counting clock signal (j) to notwithstanding et trace memory (TRM) 37 _3,
When the trace condition match signal (i) is set to logic "1", the write control signal (m) output from the gate 728 is set to logic "1" and the trace memory (TR) is set.
M) 37 ₃ and trace memory (TRM) 37 ₃
In addition, the trace information collected from the processor 2 ₃ via the processor interface unit (PIF) 31 ₃ , the alignment processing unit (RAC) 32 ₃ and the overlay control unit (OVC) 33 ₃ together with the elapsed time signal (n). Record.

Eventually, when the tracing device 3 ₂ detects that the trace end condition is satisfied in the corresponding processor 2 ₂ by the trap control unit (TRP) 34 ₂ (step S12), the synchronization unit (SYN) 7 ₂ is informed. The trace end condition satisfaction signal (f) that is input becomes a satisfaction condition (for example, logic “1”).

[0052] In the synchronization unit (SYN) 7 _2, when the trace end condition establishing signal (f) is set to a logic "1", the flip-flops 701 to 704 are reset output signal q ₇₀₁ to q ₇₀₄ respectively Since it is set to logic "0", the write control signal (m) output from the gate 311 is set to logic "0", the timer 711 is also restored, and the elapsed time signal (n) is set to "0". Initialize.

[0053] As is clear from the above description, according to the present embodiment, when tracing a three units of the processor 2 ₁ to 2 _3, a tracer 3 ₂ for one processor 2 ₂ traced Trace defined as a reference, only enter the trace start condition for the selected trace 3 _2,
After setting each tracer 3 ₁ to 3 ₃ to trace condition, by tracing start only tracer 3 _2, all traces apparatus 3 ₁ to 3 ₃ are synchronized for each processor 2 ₁ 2 ₃ Since the trace is started and the time measurement of the elapsed time signal (n) is also started, the trace information synchronized with the trace memories (TRM) 37 _{1 to} 37 ₃ can be recorded.

2 to 5 and 7 are merely one embodiment of the present invention, and for example, the synchronizing section (SYN) 7 is used.
Is not limited to that shown in FIG. 3, and, for example, as shown in FIG. 6, the trace devices 3 ₁ and 3 ₃ output from the timer 711 in the synchronizing units (SYN) 7 ₁ and 7 ₃ , respectively. instead of transmitting the elapsed time signal (n) to the trace memory (TRM) 37 ₁ and 37 ₃ being, synchronizer in the trace device 3 ₂ selected (SY
N) 7 ₂ and the elapsed time signal (n) transmitted as the other elapsed time signal (o) and transmitted to the corresponding trace memories (TRM) 37 ₁ and 37 ₃ , respectively.
Many other modifications can be considered, but in any case, the effect of the present invention does not change.

[0055] The trace device selected as a reference rather than be limited to 3 _2, although other numerous variations are considered, the effect does not change the present invention in any case. Further, the processing device 100 and the information collecting device 3 which are the subject of the present invention
It goes without saying that 00 and the information collecting unit 200 are not limited to the illustrated processor 2, multiprocessor trace device 1 and trace device 3.

[0056]

As described above, according to the present invention, all the information collecting units in the information collecting apparatus collectively perform information processing based on the satisfaction of the condition notified from the specific information collecting unit in which the recording start condition is preset. Since the collection of data is started and recorded together with the elapsed time unified in the information collecting device, the program running progress of each processing device can be recorded synchronously, which is more effective for a plurality of processors operating in a linked manner. Information can be collected.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a trace device according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a synchronization unit in FIG.

FIG. 4 is a diagram showing an example of a signal transmission means to another tracing device.

FIG. 5 is a diagram showing a trace processing process according to an embodiment of the present invention.

FIG. 6 is a diagram showing another example of the synchronization unit in FIG.

FIG. 7 is a diagram showing an example of a multiprocessor trace device to which the present invention is applied.

FIG. 8 is a diagram showing an example of a conventional tracing device.

9A and 9B are diagrams showing an example of information collection by dynamic trace, where FIG. 9A shows an example of a trace target instruction sequence, and FIG. 9B shows an example of a collection result.

[Explanation of symbols]

 1 Multiprocessor Trace Device 2 Processor 3 Trace Device 4 Switching Device 5 Workstation 6 Communication Control Device 7 Synchronization Unit (SYN) 31 Processor Interface Unit (PIF) 32 Alignment Processing Unit (RAC) 33 Overlay Control Unit (OVC) 34 Trap Control unit (TRP) 35 Trace condition selection unit (TRS) 36 Trace control unit (TRC) 37 Trace memory (TRM) 38 Microprocessor (MPU) 100 Processing device 200 Information collecting unit 300 Information collecting device 361 to 363, 721 to 729 Gate 400 Other starting means 701 to 704 Flip-flop 711 Timer 731 Driver 741 Selector

Claims (3)

[Claims] 1. An information collecting device (300) comprising a plurality of information collecting units (200) for respectively recording a program running progress of a processing device (100), wherein each information collecting unit (200) collects its own information. Department (20
When the condition for starting the recording is set in 0), the satisfaction of the condition for starting the recording is monitored, and when the satisfaction of the condition for starting the recording is detected, all the information collecting units (200) A synchronous trace method characterized in that another starting means (400) for instructing the start of recording is provided. 2. The other activation means (400) instructs the information collecting units (200) to start recording, and at the same time, starts counting the elapsed time of the recording in each of the information collecting units (200). The synchronization trace method according to claim 1, wherein the synchronization trace method is recorded. 3. The other activating means (400) notifies all other information collecting units (200) of the elapsed time of the recording timed in the own information collecting unit (200) and causes the information to be recorded. The synchronization trace method according to claim 1, wherein: