JPH0644249B2 - Cache device - Google Patents

Description

The present invention relates to a cache device used in an electronic computer, and in particular, receives address information in the form of a logical address from an access request source and converts it into a physical address. The present invention relates to a cache device of a system for registering and searching a data array and a directory array.

[Conventional technology]

Conventionally, this type of cache device has been realized by any of the following methods.

1) A method of simultaneously performing an address translation cycle and a cache search cycle.

According to this method, only the relative address within the space within the logical address is used for the addresses of the directory array and the data array, and the logical space address within the logical address is converted into the physical space address by the address conversion circuit and registered as the cache directory. And is used for cache hit detection.

2) A method of separating the address translation cycle and the cache search cycle.

In this method, first, a logical space address in a logical address is converted into a physical space address by an address conversion circuit, and this is combined with a spatial relative address in the logical address to generate a physical address and store it in a register.
Next, a part of the stored physical address is used as the directory, and the rest is used as the addresses of the directory array and the data array.

[Problems to be Solved by the Invention]

The conventional cache device has been realized by any of the above-mentioned methods, but it has a problem that it is difficult to achieve both high-speed response and large capacity of the cache. That is, in the case of the former method 1), since only the relative address in space is used as the address of the directory array and the data array, it is impossible to freely increase the address width only on the hardware. Therefore, the capacity of one compartment cannot be increased to increase the cache hit rate, and it is difficult to increase the capacity. In the latter method 2), since the physical address after the address conversion is used as the address of the directory array and the data array, the capacity per one compartment of the cache can be increased freely, but the address conversion and the cache search Since the cycles are separated, the responsiveness is worse than that of the former method 1).

The present invention has been made in view of such circumstances,
It is an object of the present invention to provide a cache device having both the high speed response of the conventional method 1) and the easiness of expanding the cache capacity of the conventional method 2).

[Means for Solving the Problems]

In order to achieve the above object, the present invention provides a logical address register for storing a logical address composed of a logical space address and a relative address within a space, and a physical address with a logical space address in the output of this logical address register as an input. An address conversion circuit that outputs a spatial address, a directory array that registers and searches a part of the physical address obtained by combining the physical space address and the relative address in space as an address, and the other part as a directory, and this directory array In the cache device, there is provided a data array for registering and retrieving data with the same address, and a hit detection circuit for detecting a cache hit by comparing the output of the directory array with a part of the physical address. Output physical space address of The physical space address register to be stored is compared with the physical space address of the output of this physical space address register and the new physical space address output from the address conversion circuit, and if they do not match, the execution inhibit signal is output. A signal generation circuit, combining the physical space address of the output of the physical space address register and the relative address in space which is a part of the output of the logical address register, and the address of the directory array and the data array and the directory. It has a configuration of a physical address used for the directory portion of the array.

[Action]

In the cache device of the present invention, the physical space address register for storing the physical space address output from the address conversion circuit holds the physical space address for the previous access, and the new logical address is stored in the logical address register. Then, the address translation circuit starts the operation of translating the logical space address in the output into the physical space address, and at the same time, the address in the space in the output of the logical address register and the physical space address register are started. The directory array and the data array are searched with a part of the physical address obtained by combining the physical space address related to the access just before being held as the address, and the directory detected by the hit detection circuit from the directory array by the above search. And the combination of By comparing the portion of the physical address to detect the presence or absence of a cache hit. Further, when the conversion operation of the address conversion circuit is completed and a physical space address corresponding to the current logical space address is newly output, the execution inhibit signal generation circuit is held in the physical space address and the physical space address register. Is compared with the physical space address immediately before the access, and if they do not match, an execution inhibit signal is output. Here, if the physical space address for this access is the same as the physical space address for the previous access, the physical address generated using the physical space address held by the physical space address register is the correct physical address. Therefore, the search of the directory array and the data array and the operation of the hit detection circuit, which were performed in parallel with the address conversion operation of the address conversion circuit, become effective, and in the case of a cache hit, the corresponding data is promptly returned. be able to. If the physical space address for this access and the physical space address for the previous access are different, an execution inhibit signal is output from the execution inhibit signal generation circuit and the physical space address held in the physical space address register is changed. The search operation according to the erroneous physical address generated by the use is invalidated, and the search by the physical address generated by using the physical space address newly generated by the address conversion circuit is performed.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of a cache device of the present invention.

In the figure, a logical address register 30 stores the logical address 10 transmitted from the main memory address operation unit of the data processing device which employs a virtual memory system such as segmentation and paging. The stored logical address is composed of a logical space address 11 including a segment number and a page number for indicating a certain logical space, and an in-space relative address 12 of the logical space. The logical space address 11 is input to the address conversion circuit 31, converted into a physical space address 13 which means a base address of a certain physical area, and output. The output physical space address 13 is stored in the physical space address register 32.

The physical space address 15 at the output of the physical space address register 32 is combined with the in-space relative address 12 to form the physical address 16. The physical address 16 is divided into an input directory 17 and an array address 18 as needed. The array address 18 becomes an address of the directory array 35 and the data array 38, and is used for searching and registering each array. Input directory 17
In order to detect a cache hit at the time of cache search, is compared with the output directory 19 of the directory array 35 by the hit detection circuit 36. When registering a cache such as a cache miss, it is registered as input data of the directory array 35 under the control of the directory array write control circuit 34. The cache hit signal 20 output from the hit detection circuit 36 is given to the selection circuit 39,
The selection circuit 39 selects the cache data 22 or the main memory data 21 as the read data 23 according to the cache hit signal 20. When a cache miss occurs, the main memory data 21 is registered in the data array 38 under the control of the data array write control circuit 37.

The execution inhibiting signal generation circuit 33 inputs the physical space address 13 output from the address conversion circuit 31 and the physical space address 15 output from the physical space address register 32, and compares them. If the physical space address 13 is valid, the execution inhibit signal 14 is sent. When the execution inhibiting signal 14 is sent, the storage of the next logical address is inhibited, and the directory search operation at that time is also invalidated. Further, the physical space address register 32 stores the physical space address 13 while the execution inhibiting signal 14 is transmitted. As a result, the physical space address 13 and the physical space address 15 match, and the transmission of the execution inhibition signal ends. These series of operations have the following meanings.

When the logical address 10 is calculated according to the main memory read instruction and stored in the logical address register 30, address conversion is performed next. At this time, the physical space address register 32 stores the physical space address at the time of the immediately preceding main memory read instruction. Here, if the physical space address after the address conversion is equal to the physical space address accessed immediately before, it is not necessary to perform the address conversion. That is, the cache can be searched in the address conversion cycle by using the physical space address 15 stored in the physical space address register 32 at that time in place of the physical space address after the address conversion. Therefore, the read data 23 can be returned in the cycle next to the main memory read instruction. However, when the physical space address 13 after the address conversion and the physical space address 15 accessed immediately before do not match, the physical space address 13 after the address conversion must be used, and therefore the execution inhibit signal 14 is sent. At that time, the physical space address 13 is stored in the physical space address register 32.

According to the present embodiment, read data can be returned in the next cycle of the main memory read instruction, and all bits of the physical address after address conversion can be used for the cache search, so that one compartment is used. It is possible to increase the capacity per hit freely. Although a method of increasing the number of compartments and increasing the cache capacity is generally known, it goes without saying that the method can also be applied to the present invention.

〔The invention's effect〕

As described above, in the cache device of the present invention, the physical space address generated by the address conversion circuit for the previous access is held in the physical space address register, and the logical address for the next access is given. When the address translation circuit starts the operation of translating the logical space address in the logical address into the physical space address, in parallel with this, the relative address in space in the logical address and the physical space address register described above are The physical address consisting of the physical space address related to the access just before being held is used to search the directory array and the cache hit, and the physical space address related to this access is the physical space immediately before. If it is the same as the address and there is a cache hit, promptly It is possible to return the over data.
Further, since the physical address is used as the cache search address, it is possible to easily increase the cache capacity per compartment.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of essential parts of an embodiment of a cache device of the present invention. In the figure, 10 ... Logical address 11 ... Logical space address 12 ... Space relative address 13 ... Physical space address (current address) 14 ... Execution inhibit signal 15 ... Physical space address (requires previous access 16) Physical address 17 ... Input directory 18 ... Array address 19 ... Output directory 20 ... Cache hit signal 21 ... Main memory data 22 ... Cache data 23 ... Read data 30 ... Logical address register 31 ... Address conversion circuit 32 ... Physical space address register 33 ... Execution inhibition signal generation circuit 34 ... Directory array write control circuit 35 ... Directory array 36 ... Hit detection circuit 37 ... Data array write control circuit 38 ... Data array 39 ... Selection circuit

Claims (1)

[Claims] 1. A logical address register for storing a logical address composed of a logical space address and a relative address within the space, and an address conversion for outputting a physical space address with the logical space address being output from the logical address register as an input. A circuit, a directory array for registering and searching a part of a physical address obtained by combining a physical space address and a relative address in space as an address and the other part as a directory, and registering data by the same address as the directory array. In a cache device comprising a data array to be searched and a hit detection circuit for detecting a cache hit by comparing the output of the directory array with a part of the physical address, the physical space address of the output of the address conversion circuit is set. Physical space address register to store And an execution inhibit signal generation circuit that compares the physical space address output from the physical space address register with the physical space address newly output from the address conversion circuit and outputs an execution inhibit signal when they do not match. A physical space address of the output of the physical space address register and a relative address in space that is a part of the output of the logical address register are combined to combine the address of the directory array and the data array and the directory portion of the directory array. A cache device having a configuration of a physical address used for.