JPH0644579B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0644579B2 JPH0644579B2 JP63150557A JP15055788A JPH0644579B2 JP H0644579 B2 JPH0644579 B2 JP H0644579B2 JP 63150557 A JP63150557 A JP 63150557A JP 15055788 A JP15055788 A JP 15055788A JP H0644579 B2 JPH0644579 B2 JP H0644579B2
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- copper
- layer
- semiconductor device
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 (イ)産業上の利用分野 本発明は半導体装置およびその製造方法に関し、特に半
田と融着するチップ裏面の電極およびその製造方法に関
するものである。The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an electrode on the back surface of a chip that is fused with solder and a method for manufacturing the same.
(ロ)従来の技術 一般に半導体装置はレジンモールドされているが、この
レジンモールド型の半導体装置の場合は、リード線と界
面を通じて湿気が浸入したり、また樹脂自体が水分を吸
収したりして、半導体装置内に湿気が取込まれる。(B) Conventional technology Generally, semiconductor devices are resin-molded.However, in the case of this resin-molded semiconductor device, moisture may infiltrate through the lead wire and the interface, or the resin itself may absorb moisture. Moisture is trapped in the semiconductor device.
シリコン系樹脂の場合には、樹脂自体の吸湿は非常に少
ないがリード線とのなじみが悪く、リードと樹脂界面を
通じた進入が中心となる。一方、エポキシ系の樹脂の場
合には、一般にリード線と樹脂とのなじみが良く、リー
ド線と樹脂界面を通じた湿気の浸入は少なく、樹脂自体
の吸湿が主体である。In the case of a silicon-based resin, the resin itself absorbs very little moisture, but is poorly compatible with the lead wire, and mainly enters through the interface between the lead and the resin. On the other hand, in the case of an epoxy resin, generally, the lead wire and the resin are well compatible with each other, the infiltration of moisture through the interface between the lead wire and the resin is small, and the moisture absorption of the resin itself is the main component.
いずれに於いても、レジンモールド型では、外気中の湿
気はある時間後にはＩＣ素子本体の表面に到達する。In either case, in the resin mold type, moisture in the outside air reaches the surface of the IC element body after a certain time.
そのためトランジスタのhFEの変動、配線金属間のリー
ク電流の増大やショートの発生、配線金属の腐蝕による
抵抗の増大や断線の発生が生じてしまう。As a result, the hFE of the transistor may fluctuate, the leak current between the wiring metals may increase, a short circuit may occur, and the resistance of the wiring metal may increase due to the corrosion of the wiring metals or the wiring may break.
本発明の内容である半導体基板に形成される裏面電極
も、前述の湿気により問題を生じている。The back electrode formed on the semiconductor substrate, which is the subject matter of the present invention, also has a problem due to the above-mentioned moisture.
例えば特開昭５６−４８１４２号公報（第２図）の如
く、半導体ウェハ(21)にトランジスタ等を形成した後
に、この半導体ウェハ(21)の裏面にCr-Cu-Auの裏面電極
(22)を蒸着する。For example, as disclosed in Japanese Unexamined Patent Publication No. 56-48142 (FIG. 2), after a transistor or the like is formed on a semiconductor wafer (21), a Cr-Cu-Au back surface electrode is formed on the back surface of the semiconductor wafer (21).
(22) is vapor deposited.
更にスクライブにより夫々の半導体ペレット(21)に分割
し、この半導体ペレット(21)をフレーム(23)上に載置す
る。Further, it is divided into individual semiconductor pellets (21) by scribing, and the semiconductor pellets (21) are placed on the frame (23).
ここでフレーム(23)上には、予め半田プリフォーム(24)
が載置されており、熱圧着法で固定される。Here, on the frame (23), pre-solder preform (24)
Is mounted and fixed by thermocompression bonding.
(ハ)発明が解決しようとする課題 前述の構成の半導体装置は、第３図のＰＣＴ試験のよう
に、接触抵抗が徐々に増加してしまう欠点を有してい
た。ここで測定方法は、第４図の如く、フレーム(23)と
チップ(21)上に金ワイヤ(25)を接続し、チップ(21)にプ
ラス、フレーム(23)にマイナスを印加して測定した場合
（順方向）と、逆にチップ(21)にマイナス、フレーム(2
3)にプラスを印加して測定した場合（逆方向）の２種類
に分けて、測定している。(C) Problem to be Solved by the Invention The semiconductor device having the above-described structure has a drawback that the contact resistance gradually increases as in the PCT test of FIG. Here, the measuring method is as shown in FIG. 4, in which the gold wire (25) is connected to the frame (23) and the chip (21), and the chip (21) is applied with plus and the frame (23) is applied with minus. If it is (forward), the tip (21) is negative and the frame (2
The measurement is performed by dividing it into two types, that is, when applying a plus to 3) (reverse direction).
一方、この原因は、Si基板とCrの界面にH2O（湿気）が
徐々に浸入する現象によるものであると考えられる。On the other hand, this cause is considered to be due to the phenomenon that H 2 O (moisture) gradually penetrates into the interface between the Si substrate and Cr.
第５図は、前記ＰＴＣ試験のある経過時間毎に、ペレッ
ト(21)とフレーム(23)を剥離し、ペレット裏面に見える
シリコンの割合を調べたものである。図からも判る通
り、ＰＣＴ試験投入前は、半田部分で剥離していたもの
が、ＰＣＴ試験の時間経過に伴って、Si基板(21)と裏面
電極(22)の界面で剥離が生じている事が判る。FIG. 5 is a graph in which the pellet (21) and the frame (23) are peeled off at a certain elapsed time of the PTC test, and the proportion of silicon visible on the back surface of the pellet is examined. As can be seen from the figure, what was peeled off at the solder portion before the PCT test was put into place, but peeled off at the interface between the Si substrate (21) and the back electrode (22) with the lapse of time in the PCT test. I understand.
つまりSi基板(21)と裏面電極(22)の接着力が弱くなって
来ているのが原因と考えられる。In other words, it is considered that the adhesive force between the Si substrate (21) and the back electrode (22) is weakening.
(ニ)課題を解決するための手段 本発明は、前述の問題点に鑑みてなされ、シリコンペレ
ット(1)とフレーム(5)との間に、シリコンペレット(1)
から順に、アルミニウム(2)、アルミニウム−銅(3)、銅
層(4)および半田層(6)を備えることで解決するものであ
り、一方、製造方法としては、半導体ウェハの裏面に、
順次アルミニウム、銅および金を蒸着し、チップ(1)に
分割した後、フレーム(5)上に半田(6)を介して固着し、
このチップ(1)とフレーム(5)を熱処理することで解決す
るものである。(D) Means for Solving the Problems The present invention has been made in view of the above problems, and between the silicon pellet (1) and the frame (5), the silicon pellet (1)
From the order, aluminum (2), aluminum-copper (3), is to solve by providing a copper layer (4) and a solder layer (6), on the other hand, as a manufacturing method, on the back surface of the semiconductor wafer,
After sequentially depositing aluminum, copper and gold and dividing into chips (1), they are fixed on the frame (5) via solder (6),
This is solved by heat-treating the chip (1) and the frame (5).
(ホ)作用 Crの酸化物は、水に可溶性であるため、一度酸化が進め
ば、どんどん反応が進行してしまうが、本発明の構成
は、アルミニウム(2)の酸化物であるAl2O3は、水に不溶
な物質のため、前記反応が生ずることがなく信頼性が向
上する。(E) Action Since the oxide of Cr is soluble in water, once the oxidation proceeds, the reaction progresses rapidly, but the constitution of the present invention is Al 2 O which is an oxide of aluminum (2). No. 3 is a substance insoluble in water, so that the above reaction does not occur and reliability is improved.
(ヘ)実施例 以下に本発明の実施例を図面を参照しながら詳述する。(F) Example An example of the present invention will be described in detail below with reference to the drawings.
先ず製造方法を説明する。第１に、従来通りシリコン半
導体基板（半導体ウェハ）(1)内に、周知の技術を活用
して半導体素子を形成する工程がある。First, the manufacturing method will be described. First, there is a conventional step of forming a semiconductor element in a silicon semiconductor substrate (semiconductor wafer) (1) by utilizing a well-known technique.
ここで半導体素子は、ディスクリートでもＩＣでも良
い。Here, the semiconductor element may be discrete or IC.
第２に、この半導体ウェハ(1)表面に所望パターンの電
極およびパッシベイション膜を形成する工程がある。Secondly, there is a step of forming an electrode and a passivation film having a desired pattern on the surface of the semiconductor wafer (1).
第３に、前記半導体ウェハ(1)の裏面に、順次アルミニ
ウム、銅および金を蒸着する工程がある。Thirdly, there is a step of sequentially depositing aluminum, copper and gold on the back surface of the semiconductor wafer (1).
ここではアルミニウムを６００Å〜１２００Å、銅を８
０００Å、金を１２００Åの厚さに連続蒸着する。従っ
て順次アルミニウム(2)、アルミニウム−銅(3)、銅層
(4)が形成される。Here, 600Å ~ 1200Å for aluminum and 8 for copper
000Å, gold is continuously vapor-deposited to a thickness of 1200Å. Therefore sequentially aluminum (2), aluminum-copper (3), copper layer
(4) is formed.
第４に、この半導体ウェハ(1)を分割してチップ(1)にす
る工程があり、第５に、前記チップ(1)を、主成分が銅
より成るフレーム(5)上に、半田(6)を介して固着する工
程がある。Fourthly, there is a step of dividing the semiconductor wafer (1) into chips (1), and fifthly, the chips (1) are soldered onto a frame (5) whose main component is copper. There is a step of fixing via 6).
ここでは半導体ウェハも半導体チップも同じ図番とし
た。またリード・フレーム(5)は、通常用いられる銅を
主成分としたものであり、半田(6)も同じく通常用いら
れるものである。また金は、半田に拡散してしまい、層
としては残らないので図面上では省略した 第６に、前記チップ(1)の固着されたフレーム(5)を熱処
理する工程がある。Here, the semiconductor wafer and the semiconductor chip have the same drawing number. The lead frame (5) is mainly composed of copper, which is usually used, and the solder (6) is also usually used. The gold diffuses into the solder and does not remain as a layer, so it is omitted in the drawing. Sixth, there is a step of heat-treating the frame (5) to which the chip (1) is fixed.
本工程は、本発明の特徴とする所であり、温度約３００
℃で約１０秒の熱処理を施し、第１図の点線の如く、前
記アルミニウム層(2)、アルミニウム−銅層(3)、および
銅層(4)の外部に露出する面に、酸化アルミニウム層(7)
を形成することに特徴を有する。This step is a feature of the present invention, and the temperature is about 300
A heat treatment is performed at about 10 seconds for about 10 seconds, and as shown by the dotted line in FIG. (7)
It is characterized by forming.
ここではアルミニウム層(2)はもちろん、アルミニウム
−銅層(3)にも酸化アルミニウム(7)が形成され、この酸
化アルミニウムは非水溶性であるため、従来例のCr層の
如く反応が進まず、安定化する。Here, aluminum oxide (7) is formed not only on the aluminum layer (2) but also on the aluminum-copper layer (3). Since this aluminum oxide is insoluble in water, the reaction does not proceed like the Cr layer in the conventional example. , Stabilize.
以上の製造方法からも判る通り、シリコン半導体チップ
(1)の裏面には、アルミニウム層(2)、アルミニウム−銅
の相互拡散層(3)、銅層(4)および半田層(6)が残る。ま
た点線で示すように、酸化アルミニウム(7)が、外部に
露出する部分およびその近傍に生じている。As can be seen from the above manufacturing method, silicon semiconductor chips
An aluminum layer (2), an aluminum-copper interdiffusion layer (3), a copper layer (4) and a solder layer (6) remain on the back surface of (1). Further, as shown by the dotted line, aluminum oxide (7) is generated in the portion exposed to the outside and the vicinity thereof.
以上の製造方法および構成の半導体装置をＰＣＴ試験に
かけた結果を、第６図および第７図に示す。測定法は、
第４図の説明と同様に、測定したものである。第７図
は、アルミニウム層の厚さを、３００Å、６００Åおよ
び１２００Åに分け、第６図と同じ試験をした時の結果
を示す。The results of subjecting the semiconductor device having the above manufacturing method and configuration to the PCT test are shown in FIGS. 6 and 7. The measurement method is
As in the explanation of FIG. 4, it was measured. FIG. 7 shows the result when the thickness of the aluminum layer was divided into 300 Å, 600 Å and 1200 Å and the same test as in FIG. 6 was conducted.
この結果より、アルミニウムの厚みは６００Å以上必要
であることが判る。これはアルミニウムが薄いと、アル
ミニウムが銅と合金化して、銅の中に取込まれてしまう
ためである。From this result, it is understood that the thickness of aluminum needs to be 600 Å or more. This is because when aluminum is thin, it alloys with copper and is taken up by the copper.
一方、これを防止するには、数百Åのクロム層を形成す
ると良い。クロム層は、アルミニウムと合金層を形成
し、アルミニウムと銅の反応を防ぎ、H2Oに対してはア
ルミニウムがバリアとして働くために、安定すると考え
られる。On the other hand, to prevent this, it is advisable to form a chromium layer of several hundred liters. The chromium layer is considered to be stable because it forms an alloy layer with aluminum, prevents the reaction between aluminum and copper, and acts as a barrier against H 2 O.
(ト)発明の効果 以上の説明からも明らかな如く、アルミニウム（６００
Å〜）、銅（８０００Å）、金（１２００Å）を順次蒸
着し、熱処理によってアルミニウムの外部露出部分を酸
化アルミニウムに形成することで、接触抵抗の増加が防
止でき、信頼性を向上させることができる。(G) Effects of the Invention As is clear from the above description, aluminum (600
Å ~), copper (8000 Å), gold (1200 Å) are vapor-deposited in sequence, and by heat treatment to form the externally exposed portion of aluminum into aluminum oxide, increase in contact resistance can be prevented and reliability can be improved. .
第１図は本発明の半導体装置の断面図、第２図は従来の
半導体装置の断面図、第３図は従来の裏面接触抵抗のＰ
ＣＴ試験結果を示す図、第４図は、接触抵抗の測定法を
示す図、第５図は、ＰＣＴ試験の各時間におけるシリコ
ンペレット裏面全体に占めるSiとPbの割合を示す図、第
６図は本発明の半導体装置のＰＣＴ試験結果を示す図、
第７図は、第６図に於いてアルミニウムの膜厚を変えた
時のＰＣＴ試験結果を示す図である。 (2)……アルミニウム層、(3)……アルミニウム−銅層、
(4)……銅層、(6)……半田、(7)……酸化アルミニウム
層。FIG. 1 is a sectional view of a semiconductor device of the present invention, FIG. 2 is a sectional view of a conventional semiconductor device, and FIG. 3 is a conventional backside contact resistance P.
The figure which shows the CT test result, FIG. 4 is a figure which shows the measuring method of contact resistance, FIG. 5 is the figure which shows the ratio of Si and Pb which occupy the whole silicon pellet back surface at each time of PCT test, FIG. Is a diagram showing a PCT test result of the semiconductor device of the present invention,
FIG. 7 is a diagram showing a PCT test result when the film thickness of aluminum is changed in FIG. (2) …… Aluminum layer, (3) …… Aluminum-copper layer,
(4) …… Copper layer, (6) …… Solder, (7) …… Aluminum oxide layer.
Claims (2)
ンペレットを固着する半導体装置に於いて、前記シリコ
ンペレットとフレームとの間に、前記シリコンペレット
側から順に、アルミニウム、アルミニウム−銅、銅、半
田層を少なくとも備え、且つ前記アルミニウム、アルミ
ニウム−銅層の外部に露出する面にアルミニウムの酸化
物を有することを特徴とした半導体装置。1. In a semiconductor device in which silicon pellets are fixed on a frame whose main component is copper, aluminum, aluminum-copper and copper are provided between the silicon pellets and the frame in order from the silicon pellet side. A semiconductor device comprising at least a solder layer and having an aluminum oxide on a surface exposed to the outside of the aluminum or aluminum-copper layer.
ンペレットを固着する半導体装置に於いて、前記シリコ
ンペレットとフレームとの間に、前記シリコンペレット
側から順に、アルミニウム、クロム、銅、半田層を少な
くとも備え、且つ前記アルミニウム層の外部に露出する
面にアルミニウムの酸化物を有することを特徴とした半
導体装置。2. A semiconductor device in which a silicon pellet is fixed on a frame whose main component is copper. Between the silicon pellet and the frame, aluminum, chromium, copper, and solder are arranged in order from the silicon pellet side. A semiconductor device comprising at least a layer and having an oxide of aluminum on a surface exposed to the outside of the aluminum layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63150557A JPH0644579B2 (en) | 1988-06-17 | 1988-06-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63150557A JPH0644579B2 (en) | 1988-06-17 | 1988-06-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01318236A JPH01318236A (en) | 1989-12-22 |
| JPH0644579B2 true JPH0644579B2 (en) | 1994-06-08 |
Family
ID=15499485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63150557A Expired - Lifetime JPH0644579B2 (en) | 1988-06-17 | 1988-06-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644579B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9214442B2 (en) * | 2007-03-19 | 2015-12-15 | Infineon Technologies Ag | Power semiconductor module, method for producing a power semiconductor module, and semiconductor chip |
| WO2011004469A1 (en) * | 2009-07-08 | 2011-01-13 | トヨタ自動車株式会社 | Semiconductor device and method for manufacturing same |
| JP2011054624A (en) * | 2009-08-31 | 2011-03-17 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP5714280B2 (en) * | 2010-09-17 | 2015-05-07 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device |
| US10566267B2 (en) | 2017-10-05 | 2020-02-18 | Texas Instruments Incorporated | Die attach surface copper layer with protective layer for microelectronic devices |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856345A (en) * | 1981-09-30 | 1983-04-04 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS58101432A (en) * | 1981-12-11 | 1983-06-16 | Hitachi Ltd | Back surface electrode structure for semiconductor pellet |
| JPS61156824A (en) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | Semiconductor device |
| JPS61168958A (en) * | 1985-01-22 | 1986-07-30 | Nippon Kogaku Kk <Nikon> | Gold-diffusion preventing layer |
-
1988
- 1988-06-17 JP JP63150557A patent/JPH0644579B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01318236A (en) | 1989-12-22 |
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