JPH01318236A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01318236A JPH01318236A JP63150557A JP15055788A JPH01318236A JP H01318236 A JPH01318236 A JP H01318236A JP 63150557 A JP63150557 A JP 63150557A JP 15055788 A JP15055788 A JP 15055788A JP H01318236 A JPH01318236 A JP H01318236A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- copper
- semiconductor device
- frame
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置およびその製造方法に関し、特に半
田と融着するチップ裏面の電極およびその製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an electrode on the back surface of a chip that is fused with solder and a method of manufacturing the same.
（ロ）従来の技術
一般に半導体装置はレジンモールドされているが、この
レジンモールド型の半導体装置の場合は、リード線と界
面を通じて湿気が浸入したり、また樹脂自体が水分を吸
収したりして、半導体装置内に湿気が取込まれる。(b) Conventional technology Semiconductor devices are generally resin-molded, but in the case of resin-molded semiconductor devices, moisture can enter through the lead wires and the interface, and the resin itself can absorb moisture. , moisture is introduced into the semiconductor device.
シリコン系樹Ｊ指の場合には、樹脂自体の吸湿は非常に
少ないがリード線とのなじみが悪く、リードと樹脂界面
を通じた進入が中心となる。一方、エポキシ系の樹脂の
場合には、一般にリード線と樹脂とのなじみが良く、リ
ード線と樹脂界面を通じた湿気の浸入は少なく、樹脂自
体の吸湿が主体である。In the case of silicone-based J fingers, the resin itself absorbs very little moisture, but it is poorly compatible with the lead wire, and moisture mainly enters through the interface between the lead and the resin. On the other hand, in the case of epoxy resin, the lead wire and the resin generally fit well together, and there is little moisture infiltration through the interface between the lead wire and the resin, and moisture is mainly absorbed by the resin itself.
いずれに於いても、レジンモールド型では、外気中の湿
気はある時間後にはＩＣ素子本体の表面に到達する。In any case, in the resin mold type, moisture in the outside air reaches the surface of the IC element body after a certain period of time.
そのためトランジスタのｈ□の変動、配線金属間のリー
ク電流の増大やショートの発生、配線金属の腐蝕による
抵抗の増大や断線の発生が生じてしまう。As a result, fluctuations in h□ of the transistor, an increase in leakage current and occurrence of short circuits between wiring metals, and an increase in resistance and occurrence of wire breakage due to corrosion of the wiring metals occur.
本発明の内容である半導体基板に形成される裏面電極も
、前述の湿気により問題を生じている。The back electrode formed on the semiconductor substrate, which is the content of the present invention, also has problems due to the above-mentioned moisture.
例えば特開昭５６−４８１４２号公報（第２図）の如く
、半導体ウェハ（２１）にトランジスタ等を形成した後
に、この半導体ウェハ（２１）の裏面にＣｒ−Ｃｕ−Ａ
ｕの裏面電極（２２）を蒸着する。For example, as in JP-A-56-48142 (Fig. 2), after forming transistors etc. on a semiconductor wafer (21), Cr-Cu-A
A back electrode (22) of u is deposited.
更にスクライプにより夫々の半導体ペレット（２！）に
分割し、この半導体ペレット（２１）をフレーム（２３
）上に載置する。Furthermore, the semiconductor pellets (21) are divided into individual semiconductor pellets (2!) by a scribe, and then the semiconductor pellets (21) are attached to a frame (23).
).
ここでフレーム（２３）上には、予め半［ロブリフォー
ム（２４）が戟、置されており、熱圧着法で固定される
。Here, on the frame (23), a half-rotary foam (24) is placed in advance and fixed by thermocompression bonding.
（八）発明が解決しようとする課題
前述の構成の半導体装置は、第３図のＰＣＴ試験のよう
に、接触抵抗が徐々に増加してしまう欠点を有していた
。ここで測定方法は、第４図の如く、フレーム（２３）
とチップ（２１）上に金ワイヤ（２５）を接続し、チッ
プ（２１）にプラス、フレーム（２３）にマイナスを印
加して測定した場合（順方向）と、逆にチップ（２１）
にマイナス、フレーム（２３〉にプラスを印加して測定
した場合（逆方向）の２種類に分けて、測定している。(8) Problems to be Solved by the Invention The semiconductor device having the above-mentioned structure has a drawback that the contact resistance gradually increases as shown in the PCT test shown in FIG. Here, the measurement method is as shown in Fig. 4.
When measuring by connecting a gold wire (25) to the chip (21) and applying a positive voltage to the chip (21) and a negative voltage to the frame (23) (forward direction), and vice versa
The measurement is divided into two types: a negative voltage is applied to the frame (23), and a positive voltage is applied to the frame (23>) (reverse direction).
一方、この原因は、Ｓｉ基板とＣｒの界面にＨ，０（湿
気）が徐々に浸入する現象によるものであると考えられ
る。On the other hand, the cause of this is thought to be a phenomenon in which H,0 (moisture) gradually enters the interface between the Si substrate and Cr.
第５図は、前記ＰＴＣ試験のある経過時間毎に、ペレッ
ト（２１）とフレーム（２３）を剥離し、ペレット裏面
に見えるシリコンの割合を調べたものである０図からも
判る通り、ＰＣＴ試験投入前は、半田部分で剥離してい
たものが、ＰＣＴ試験の時間経過に伴って、Ｓｉ基板（
２１）と裏面電極（２２）の界面で剥離が生じている事
が判る。Figure 5 shows the result of peeling off the pellet (21) and frame (23) at each elapsed time of the PTC test and examining the proportion of silicon visible on the back side of the pellet.As can be seen from Figure 0, the PCT test Before inputting, the solder part had peeled off, but as time passed during the PCT test, the Si substrate (
It can be seen that peeling occurs at the interface between the back electrode (21) and the back electrode (22).
つまりＳｉ基板〈２１）と裏面電極（２２）の接着力が
弱くなって来ているのが原因と考えられる。In other words, it is thought that the cause is that the adhesive force between the Si substrate (21) and the back electrode (22) is becoming weaker.
（ニ）課題を解決するための手段
本発明は、前述の問題点に鑑みてなされ、シリコンペレ
ッＩ−（１＞とフレーム（５）との間に、アルミニウム
（２）、アルミニウム−銅（３）、銅層（４）および半
田層（６）を備えることで解決するものであり、一方、
製造方法としては、半導体ウェハの裏面に、順次アルミ
ニウム、銅および金を蒸着し、チップ（１）に分割した
後、フレーム（５）上に半田（６）を介して固着し、こ
のチップ（１）とフレーム（５）を熱処理することで解
決するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes aluminum (2), aluminum-copper (3) between the silicon pellet I-(1>) and the frame (5). ), a copper layer (4) and a solder layer (6).
The manufacturing method involves sequentially vapor-depositing aluminum, copper, and gold on the back side of a semiconductor wafer, dividing it into chips (1), and then fixing them on a frame (5) via solder (6). ) and the frame (5) are heat treated.
（ネ）作用
Ｃｒの酸化物は、水に可溶性であるため、−度酸化が進
めば、どんどん反応が進行してしまうが、本発明の構成
は、アルミニウム（２）の酸化物であるＡ １ ｍ Ｏ
ｎは、水に不溶な物質のため、前記反応が生ずることが
なく信頼性が向上する。(f) Effect Since the oxide of Cr is soluble in water, the reaction progresses more and more as the -degree oxidation progresses, but the structure of the present invention is that the oxide of aluminum (2) A1 m O
Since n is a substance insoluble in water, the above-mentioned reaction does not occur and reliability is improved.
（へ）実施例 以下に本発明の実施例を図面を参照しながら詳述する。(f) Example Embodiments of the present invention will be described in detail below with reference to the drawings.
先ず製造方法を説明する。第１に、従来通りシリコン半
導体基板（半導体ウェハ）（１）内に、周知の技術を活
用して半導体素子を形成する工程がある。First, the manufacturing method will be explained. First, there is a conventional step of forming semiconductor elements in a silicon semiconductor substrate (semiconductor wafer) (1) using well-known techniques.
ここで半導体素子は、ディスクリートでもＩＣでも良い
。Here, the semiconductor element may be a discrete or an IC.
第２に、この半導体ウェハ（１）表面に所望パターンの
電極およびパッシベイション膜を形成する工程がある。Second, there is a step of forming electrodes and a passivation film in a desired pattern on the surface of this semiconductor wafer (1).
第３に、前記半導体ウェハ（１）の裏面に、順次アルミ
ニウム、銅および金を蒸着する工程がある。Thirdly, there is a step of sequentially depositing aluminum, copper and gold on the back surface of the semiconductor wafer (1).
ここではアルミニウムを６００Ａ〜１２００人、銅を８
０００人、金を１２００人のＪヴさに連続蒸着する。従
って順次アルミニウム〈２〉、アルミニウム−鋼（３）
、銅Ｊｌ（４）が形成される。Here aluminum is 600A~1200A, copper is 8A
000 people, gold was continuously deposited on 1200 people. Therefore, sequentially aluminum <2>, aluminum-steel (3)
, copper Jl(4) is formed.
第４に、この半導体ウェハ（１）を分割してチップ（１
）にする工程があり、第５に、前記チップ（１）を、主
成分が銅より成るフレーム（５）上に、半田（６）を介
して固着する工程がある。Fourth, this semiconductor wafer (1) is divided into chips (1
), and fifthly, there is a step of fixing the chip (1) onto a frame (5) whose main component is copper via solder (6).
ここでは半導体ウェハも半導体チップも同じ図番とした
。またリード・フレーム（５）は、通常用いられる銅を
主成分としたものであり、半田（６）も同じく通常用い
られるものである。また金は、半田に拡散してしまい、
層としては残らないので図面上では省略した
第６に、前記チップ（１）の固着されたフレーム＜５）
を熱処理する工程がある。Here, both the semiconductor wafer and the semiconductor chip are given the same figure number. Further, the lead frame (5) is mainly made of commonly used copper, and the solder (6) is also commonly used. Also, the gold will diffuse into the solder,
Sixth, which is omitted in the drawing because it does not remain as a layer, is the frame to which the chip (1) is fixed (<5).
There is a process of heat treatment.
本工程は、本発明の特徴とする所であり、温度的３００
°Ｃで約１０秒の熱処理を施し、第１図の点線の如く、
前記アルミニウム層（２）、アルミニウム−銅層（３）
、および銅層（４）の外部に露出する面に、酸化アルミ
ニウム層（７）を形成することに特徴を有する。This step is a feature of the present invention, and is
After heat treatment at °C for about 10 seconds, as shown in the dotted line in Figure 1,
The aluminum layer (2), aluminum-copper layer (3)
, and an aluminum oxide layer (7) is formed on the surface exposed to the outside of the copper layer (4).
ここではアルミニウム層（２）はもちろん、アルミニウ
ム−鋼層（３）にも酸化アルミニウム（７）が形成され
、この酸化アルミニウムは非水溶性である、ため、従来
例のＣｒ層の如く反応が進まず、安定化する。Here, aluminum oxide (7) is formed not only on the aluminum layer (2) but also on the aluminum-steel layer (3), and since this aluminum oxide is water-insoluble, the reaction proceeds as in the conventional Cr layer. First, stabilize.
以上の製造方法からも判る通り、シリコン半導体チップ
（１）の裏面には、アルミニウム層（２）、アルミニウ
ム−銅の相互拡散層（３）、銅層（４）および半田層（
６）が残る。また点線で示すように、酸化アルミニウム
（７）が、外部に露出する部分およびその近傍に生じて
いる。As can be seen from the above manufacturing method, the back surface of the silicon semiconductor chip (1) includes an aluminum layer (2), an aluminum-copper interdiffusion layer (3), a copper layer (4), and a solder layer (
6) remains. Further, as shown by the dotted line, aluminum oxide (7) is generated in the exposed portion and its vicinity.
以上の製造方法および構成の半導体装置をＰＣＴ試験に
かけた結果を、第６図および第７図に示す、測定法は、
第４図の説明と同様に、測定したものである。第７図は
、アルミニウム層の厚さを、３００人、６００人および
１２００人に分け、第６図と同じ試験をした時の結果を
示す。The results of subjecting the semiconductor device manufactured by the above manufacturing method and configuration to the PCT test are shown in FIGS. 6 and 7. The measurement method was as follows:
Measurements were made in the same manner as described in FIG. FIG. 7 shows the results when the same test as in FIG. 6 was conducted with the thickness of the aluminum layer divided into 300, 600 and 1200 layers.
この結果より、アルミニウムの厚みは６００Å以上必要
であることが判る。これはアルミニウムが薄いと、アル
ミニウムが銅と合金化して、銅の中に取込まれてしまう
ためである。From this result, it can be seen that the thickness of aluminum is required to be 600 Å or more. This is because if the aluminum is thin, the aluminum will be alloyed with the copper and incorporated into the copper.
一方、これを防止するには、数百人のクロム層を形成す
ると良い、クロム層は、アルミニウムと合金層を形成し
、アルミニウムと銅の反応を防ぎ、ＨＩＯに対してはア
ルミニウムがバリアとして働くために、安定すると考え
られる。On the other hand, to prevent this, it is good to form a chromium layer of several hundred people.The chromium layer forms an alloy layer with aluminum, preventing the reaction between aluminum and copper, and aluminum acts as a barrier against HIO. Therefore, it is considered to be stable.
（ト）発明の効果
以上の説明からも明らかな如く、アルミニウム（６００
人〜）、銅（８０００人）、金（１２００人）を順次蒸
着し、熱処理によってアルミニウムの外部露出部分を酸
化アルミニウムに形成することで、接触抵抗の増加が防
止でき、信頼性を向上させることができる。(g) Effect of the invention As is clear from the above explanation, aluminum (600
), copper (8,000 people), and gold (1,200 people) are sequentially vapor-deposited, and the externally exposed parts of the aluminum are formed into aluminum oxide through heat treatment, thereby preventing an increase in contact resistance and improving reliability. I can do it.
第１図は本発明の半導体装置の断面図、第２図は従来の
半導体装置の断面図、第３図は従来の裏面接触抵抗のＰ
ＣＴ試験結果を示す図、第４図は、接触抵抗の測定法を
示す図、第５図は、ＰＣＴ試験の各時間におけるシリコ
ンペレット裏面全体に占めるＳｉとＰｂの割合を示す図
、第６図は本発明の半導体装置のＰＣＴ試験結果を示す
図、第７図は、第６図に於いてアルミニウムの膜厚を変
えた時のＰＣＴ試験結果を示す図である。
（２）・・・アルミニウム層、（３）・・・アルミニウ
ム−銅層、 （４）・・・銅層、 （６）・・・半田、
（７）・・・酸化アルミニウム層。FIG. 1 is a sectional view of the semiconductor device of the present invention, FIG. 2 is a sectional view of a conventional semiconductor device, and FIG. 3 is a sectional view of the conventional back contact resistance P.
Figure 4 shows the CT test results, Figure 4 shows the contact resistance measurement method, Figure 5 shows the ratio of Si and Pb to the entire back surface of the silicon pellet at each time of the PCT test, Figure 6 7 is a diagram showing the PCT test results of the semiconductor device of the present invention, and FIG. 7 is a diagram showing the PCT test results when the aluminum film thickness is changed in FIG. 6. (2)...aluminum layer, (3)...aluminum-copper layer, (4)...copper layer, (6)...solder,
(7)...Aluminum oxide layer.
Claims (6)
ットを固着する半導体装置に於いて、前記シリコンペレ
ットとフレームとの間にアルミニウム、アルミニウム−
銅、銅、半田層を少なくとも備えることを特徴とした半
導体装置。(1) In a semiconductor device in which a silicon pellet is fixed on a frame whose main component is copper, there is a space between the silicon pellet and the frame such as aluminum or aluminum.
A semiconductor device comprising at least copper, a copper layer, and a solder layer.
露出する面にアルミニウムの酸化物を有する請求項第１
項記載の半導体装置。(2) Claim 1 comprising aluminum oxide on the externally exposed surface of the aluminum and aluminum-copper layer.
1. Semiconductor device described in Section 1.
求項第２項記載の半導体装置。(3) The semiconductor device according to claim 2, wherein a chromium layer is provided between the aluminum and copper layers.
する工程と、前記半導体ウェハの裏面に順次アルミニウ
ム、銅および金を蒸着する工程と、前記半導体ウェハを
分割してチップとする工程と、前記チップを主成分が銅
より成るフレーム上に半田を介して固着する工程と、前
記チップの固着されたフレームを熱処理する工程とを少
なくとも有することを特徴とした半導体装置の製造方法
。(4) forming elements and metal wiring on the front surface of the semiconductor wafer; sequentially depositing aluminum, copper, and gold on the back surface of the semiconductor wafer; and dividing the semiconductor wafer into chips; 1. A method for manufacturing a semiconductor device, comprising at least the steps of fixing a chip onto a frame mainly made of copper via solder, and heat-treating the frame to which the chip is fixed.
求項第４項記載の半導体装置の製造方法。(5) The method for manufacturing a semiconductor device according to claim 4, wherein chromium is vapor-deposited after the aluminum is vapor-deposited.
または第５項記載の半導体装置の製造方法。(6) The method for manufacturing a semiconductor device according to claim 4 or 5, wherein the aluminum has a thickness of 600 Å or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63150557A JPH0644579B2 (en) | 1988-06-17 | 1988-06-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63150557A JPH0644579B2 (en) | 1988-06-17 | 1988-06-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01318236A true JPH01318236A (en) | 1989-12-22 |
| JPH0644579B2 JPH0644579B2 (en) | 1994-06-08 |
Family
ID=15499485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63150557A Expired - Lifetime JPH0644579B2 (en) | 1988-06-17 | 1988-06-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644579B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008235898A (en) * | 2007-03-19 | 2008-10-02 | Infineon Technologies Ag | Power semiconductor module, power semiconductor module manufacturing method, and semiconductor chip |
| WO2011004469A1 (en) * | 2009-07-08 | 2011-01-13 | トヨタ自動車株式会社 | Semiconductor device and method for manufacturing same |
| JP2011054624A (en) * | 2009-08-31 | 2011-03-17 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2012064826A (en) * | 2010-09-17 | 2012-03-29 | On Semiconductor Trading Ltd | Semiconductor device |
| CN111344860A (en) * | 2017-10-05 | 2020-06-26 | 德州仪器公司 | Die Attach Surface Copper Layer with Protective Layer for Microelectronic Devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856345A (en) * | 1981-09-30 | 1983-04-04 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS58101432A (en) * | 1981-12-11 | 1983-06-16 | Hitachi Ltd | Back surface electrode structure for semiconductor pellet |
| JPS61156824A (en) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | Semiconductor device |
| JPS61168958A (en) * | 1985-01-22 | 1986-07-30 | Nippon Kogaku Kk <Nikon> | Gold-diffusion preventing layer |
-
1988
- 1988-06-17 JP JP63150557A patent/JPH0644579B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856345A (en) * | 1981-09-30 | 1983-04-04 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS58101432A (en) * | 1981-12-11 | 1983-06-16 | Hitachi Ltd | Back surface electrode structure for semiconductor pellet |
| JPS61156824A (en) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | Semiconductor device |
| JPS61168958A (en) * | 1985-01-22 | 1986-07-30 | Nippon Kogaku Kk <Nikon> | Gold-diffusion preventing layer |
Cited By (8)
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|---|---|---|---|---|
| JP2008235898A (en) * | 2007-03-19 | 2008-10-02 | Infineon Technologies Ag | Power semiconductor module, power semiconductor module manufacturing method, and semiconductor chip |
| WO2011004469A1 (en) * | 2009-07-08 | 2011-01-13 | トヨタ自動車株式会社 | Semiconductor device and method for manufacturing same |
| US8426972B2 (en) | 2009-07-08 | 2013-04-23 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| JP5327233B2 (en) * | 2009-07-08 | 2013-10-30 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method thereof |
| JP2011054624A (en) * | 2009-08-31 | 2011-03-17 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2012064826A (en) * | 2010-09-17 | 2012-03-29 | On Semiconductor Trading Ltd | Semiconductor device |
| CN111344860A (en) * | 2017-10-05 | 2020-06-26 | 德州仪器公司 | Die Attach Surface Copper Layer with Protective Layer for Microelectronic Devices |
| US12074096B2 (en) | 2017-10-05 | 2024-08-27 | Texas Instruments Incorporated | Die attach surface copper layer with protective layer for microelectronic devices |
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| Publication number | Publication date |
|---|---|
| JPH0644579B2 (en) | 1994-06-08 |
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